mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
99debc76ef
This is the lowest ddr bandwidth that puts CX at a corner high enough such that GMU can run at 550 Mhz. This is to get better GMU performance at no extra power cost. Change-Id: I4ac794b91139073c1914f8e8e39a29db03a3f09d
149 lines
3.5 KiB
Plaintext
149 lines
3.5 KiB
Plaintext
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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&soc {
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msm_gpu: qcom,kgsl-3d0@3d00000 {
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compatible = "qcom,kgsl-3d0",
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"qcom,adreno-gpu-a621";
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status = "ok";
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reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
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<0x3de0000 0x10000>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_HUB_AON_CLK>,
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<&gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&aoss_qmp>;
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clock-names = "gcc_gpu_memnoc_gfx",
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"gcc_gpu_snoc_dvm_gfx",
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"gpu_cc_ahb",
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"gpu_cc_hlos1_vote_gpu_smmu",
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"gpu_cc_cx_gmu",
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"gpu_cc_hub_aon",
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"gpu_cc_hub_cx_int",
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"apb_pclk";
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qcom,chipid = <0x06020100>;
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <3>;
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qcom,no-nap;
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qcom,initial-pwrlevel = <0>;
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interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
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interconnect-names = "gpu_icc_path";
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qcom,bus-table-ddr =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(200, 4)>, /* index=1 */
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<MHZ_TO_KBPS(451, 4)>, /* index=2 */
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<MHZ_TO_KBPS(547, 4)>, /* index=3 */
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<MHZ_TO_KBPS(681, 4)>, /* index=4 */
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<MHZ_TO_KBPS(768, 4)>, /* index=5 */
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<MHZ_TO_KBPS(1017, 4)>, /* index=6 */
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<MHZ_TO_KBPS(1353, 4)>, /* index=7 */
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<MHZ_TO_KBPS(1555, 4)>, /* index=8 */
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<MHZ_TO_KBPS(1708, 4)>, /* index=9 */
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<MHZ_TO_KBPS(2092, 4)>, /* index=10 */
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<MHZ_TO_KBPS(2133, 4)>; /* index=11 */
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qcom,bus-table-cnoc =
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<0>, /* Off */
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<100>; /* On */
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zap-shader {
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memory-region = <&gpu_microcode_mem>;
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};
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <320000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <8>;
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qcom,bus-max = <8>;
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};
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x03da0000 0x20000>;
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vddcx-supply = <&gpu_cc_cx_gdsc>;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x0 0x401>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x2 0x400>;
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qcom,iommu-dma = "disabled";
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};
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};
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gmu: qcom,gmu@3d6a000 {
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compatible = "qcom,gpu-gmu";
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reg = <0x3d6a000 0x30000>,
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<0xb290000 0x10000>;
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reg-names = "kgsl_gmu_reg",
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"kgsl_gmu_pdc_cfg";
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interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
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<0 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
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regulator-names = "vddcx", "vdd";
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iommus = <&kgsl_smmu 0x5 0x400>;
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qcom,iommu-dma = "disabled";
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vddcx-supply = <&gpu_cc_cx_gdsc>;
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vdd-supply = <&gpu_cc_gx_gdsc>;
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&aoss_qmp>;
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clock-names = "gmu_clk", "cxo_clk", "axi_clk",
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"memnoc_clk", "ahb_clk", "hub_clk",
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"smmu_vote", "apb_pclk";
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qcom,gmu-freq-table = <220000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
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<550000000 RPMH_REGULATOR_LEVEL_SVS>;
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/* GPU-MPROC IPC page */
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qcom,ipc-core = <0x0ed19000 0x1000>;
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qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(681, 4)>;
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};
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};
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