mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
a52b2d4241
Update gpu, cdsp based config mitiation rules for quiet-therm and NSP thermal zones as per latest recommondation for diwali. Change-Id: I04e7ffaeb74f8675281b34036f935df4ecbdc294
205 lines
4.9 KiB
Plaintext
205 lines
4.9 KiB
Plaintext
#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "diwali-pmic-overlay.dtsi"
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#include "diwali-thermal-overlay.dtsi"
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&soc {
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gpio_keys {
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compatible = "gpio-keys";
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label = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&key_vol_up_default>;
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vol_up {
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label = "volume_up";
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gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
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linux,input-type = <1>;
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linux,code = <KEY_VOLUMEUP>;
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gpio-key,wakeup;
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debounce-interval = <15>;
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linux,can-disable;
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};
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};
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};
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&qupv3_se0_i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "ok";
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qcom,i2c-touch-active = "novatek,NVT-ts";
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novatek@62 {
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compatible = "novatek,NVT-ts";
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reg = <0x62>;
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interrupt-parent = <&tlmm>;
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interrupts = <51 0x2008>;
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pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
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"pmx_ts_release";
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pinctrl-0 = <&ts_active>;
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pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
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pinctrl-2 = <&ts_release>;
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novatek,reset-gpio = <&tlmm 17 0x00>;
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novatek,irq-gpio = <&tlmm 51 0x2008>;
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novatek,trusted-touch-mode = "vm_mode";
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novatek,touch-environment = "pvm";
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novatek,trusted-touch-spi-irq = <566>;
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novatek,trusted-touch-io-bases = <0x980000 0x910000>;
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novatek,trusted-touch-io-sizes = <0x1000 0x4000>;
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novatek,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0
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&tlmm 3 0 &tlmm 17 0 &tlmm 51 0x2008>;
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};
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focaltech@38 {
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compatible = "focaltech,fts_ts";
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reg = <0x38>;
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interrupt-parent = <&tlmm>;
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interrupts = <51 0x2008>;
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focaltech,reset-gpio = <&tlmm 17 0x00>;
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focaltech,irq-gpio = <&tlmm 51 0x2008>;
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focaltech,max-touch-number = <5>;
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focaltech,display-coords = <0 0 1080 2340>;
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focaltech,touch-type = "primary";
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vdd-supply = <&L3C>;
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pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
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pinctrl-0 = <&ts_active>;
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pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
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pinctrl-2 = <&ts_release>;
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};
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synaptics_dsx@22 {
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compatible = "synaptics,dsx-i2c";
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reg = <0x22>;
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interrupt-parent = <&tlmm>;
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interrupts = <51 0x2008>;
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avdd-supply = <&L3C>;
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vdd-supply = <&L12C>;
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pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
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pinctrl-0 = <&ts_active>;
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pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
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pinctrl-2 = <&ts_release>;
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synaptics,pwr-reg-name = "avdd";
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synaptics,bus-reg-name = "vdd";
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synaptics,ub-i2c-addr = <0x22>;
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synaptics,max-y-for-2d = <1859>;
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synaptics,irq-gpio = <&tlmm 51 0x2008>;
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synaptics,reset-gpio = <&tlmm 17 0x00>;
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synaptics,irq-on-state = <0>;
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synaptics,power-delay-ms = <200>;
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synaptics,reset-delay-ms = <200>;
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synaptics,reset-on-state = <0>;
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synaptics,reset-active-ms = <20>;
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};
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atmel_mxt_ts@4a {
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compatible = "atmel,maxtouch";
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reg = <0x4a>;
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interrupt-parent = <&tlmm>;
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interrupts = <51 0x2008>;
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avdd-supply = <&L3C>;
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vdd-supply = <&L12C>;
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pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
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pinctrl-0 = <&ts_active>;
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pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
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atmel,xy_switch;
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atmel,inverty;
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atmel,invertx;
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reset-gpios = <&tlmm 17 0x00>;
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irq-gpios = <&tlmm 51 0x2008>;
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atmel,panel-coords = <0 0 479 799>;
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atmel,display-coords = <0 0 339 729>;
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};
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};
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&qupv3_se9_i2c {
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status = "ok";
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qcom,clk-freq-out = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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nq@28 {
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compatible = "qcom,sn-nci";
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reg = <0x28>;
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qcom,sn-irq = <&tlmm 41 0x00>;
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qcom,sn-ven = <&tlmm 38 0x00>;
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qcom,sn-firm = <&tlmm 40 0x00>;
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qcom,sn-clkreq = <&tlmm 39 0x00>;
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qcom,sn-vdd-1p8-supply = <&L18B>;
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qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
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qcom,sn-vdd-1p8-current = <157000>;
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interrupt-parent = <&tlmm>;
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interrupts = <41 0>;
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interrupt-names = "nfc_irq";
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pinctrl-names = "nfc_active", "nfc_suspend";
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pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
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pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
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};
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};
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&sdhc_2 {
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status = "ok";
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vdd-supply = <&L9C>;
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qcom,vdd-voltage-level = <2960000 2960000>;
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qcom,vdd-current-level = <0 800000>;
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vdd-io-supply = <&L6C>;
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qcom,vdd-io-voltage-level = <1800000 2960000>;
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qcom,vdd-io-current-level = <0 22000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc2_on>;
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pinctrl-1 = <&sdc2_off>;
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cd-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
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};
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v4-diwali";
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vdda-phy-supply = <&L10C>;
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vdda-pll-supply = <&L6B>;
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vdda-phy-max-microamp = <88100>;
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vdda-pll-max-microamp = <18300>;
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status = "ok";
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};
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&ufshc_mem {
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vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
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vcc-supply = <&L7B>;
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vcc-max-microamp = <1100000>;
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vccq-supply = <&L9B>;
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vccq-max-microamp = <1200000>;
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vccq2-supply = <&L19B>;
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vccq2-max-microamp = <800000>;
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qcom,vddp-ref-clk-supply = <&L9B>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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/*
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* ufs-dev-types and nvmem entries are for ufs device
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* identification using nvmem interface. Use number of
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* ufs devices supported for ufs-dev-types, and nvmem handle
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* added by pmic for sdam register.
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*/
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ufs-dev-types = <2>;
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nvmem-cells = <&ufs_dev>;
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nvmem-cell-names = "ufs_dev";
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status = "ok";
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};
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