mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
cda7be44f6
The correlated clk of the tpdm is not able to enable from kernel, so disable this tpdm. Change-Id: Icec57017759c8fdf7c6f447f7d2afa839c485aea
3242 lines
59 KiB
Plaintext
3242 lines
59 KiB
Plaintext
&soc {
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stm: stm@10002000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb962>;
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reg = <0x10002000 0x1000>,
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<0x16280000 0x180000>;
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reg-names = "stm-base", "stm-stimulus-base";
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atid = <16>;
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coresight-name = "coresight-stm";
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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stm_out_funnel_in0: endpoint {
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remote-endpoint =
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<&funnel_in0_in_stm>;
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};
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};
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};
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};
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snoc: snoc {
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compatible = "qcom,coresight-dummy";
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coresight-name = "coresight-snoc";
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qcom,dummy-source;
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atid = <125>;
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out-ports {
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port {
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snoc_out_funnel_in0: endpoint {
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remote-endpoint =
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<&funnel_in0_in_snoc>;
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};
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};
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};
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};
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csr: csr@10001000 {
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compatible = "qcom,coresight-csr";
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reg = <0x10001000 0x1000>;
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reg-names = "csr-base";
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coresight-name = "coresight-csr";
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qcom,usb-bam-support;
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qcom,hwctrl-set-support;
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qcom,set-byte-cntr-support;
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qcom,blk-size = <1>;
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};
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swao_csr: csr@10b11000 {
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compatible = "qcom,coresight-csr";
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reg = <0x10b11000 0x1000>,
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<0x10b110f8 0x50>;
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reg-names = "csr-base", "msr-base";
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coresight-name = "coresight-swao-csr";
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qcom,timestamp-support;
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qcom,msr-support;
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qcom,blk-size = <1>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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};
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audio_etm0 {
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compatible = "qcom,coresight-remote-etm";
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coresight-name = "coresight-audio-etm0";
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qcom,inst-id = <5>;
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atid = <40 41>;
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out-ports {
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port {
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audio_etm0_out_funnel_lpass_lpi: endpoint {
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remote-endpoint =
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<&funnel_lpass_lpi_in_audio_etm0>;
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};
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};
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};
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};
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lpass_stm: lpass_stm {
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compatible = "qcom,coresight-dummy";
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coresight-name = "coresight-lpass-stm";
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qcom,dummy-source;
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atid = <25>;
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out-ports {
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port {
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lpass_stm_out_funnel_lpass_lpi: endpoint {
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remote-endpoint =
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<&funnel_lpass_lpi_in_lpass_stm>;
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};
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};
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};
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};
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tpdm_lpass_lpi: tpdm@10b46000 {
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compatible = "qcom,coresight-dummy";
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coresight-name = "coresight-tpdm-lpass-lpi";
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qcom,dummy-source;
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atid = <26>;
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out-ports {
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port {
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tpdm_lpass_lpi_out_funnel_lpass_lpi: endpoint {
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remote-endpoint =
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<&funnel_lpass_lpi_in_tpdm_lpass_lpi>;
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};
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};
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};
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};
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turing_etm0: turing_etm0 {
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compatible = "qcom,coresight-remote-etm";
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coresight-name = "coresight-turing-etm0";
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qcom,inst-id = <13>;
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atid = <38 39>;
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out-ports {
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port {
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turing_etm0_out_funnel_turing_dup: endpoint {
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remote-endpoint =
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<&funnel_turing_dup_in_turing_etm0>;
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};
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};
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};
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};
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tpdm_swao_prio0: tpdm@10b09000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10b09000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-swao-prio-0";
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atid = <71>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_swao_prio0_out_tpda_aoss: endpoint {
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remote-endpoint =
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<&tpda_aoss_in_tpdm_swao_prio0>;
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};
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};
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};
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};
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tpdm_swao_prio1: tpdm@10b0a000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10b0a000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-swao-prio-1";
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atid = <71>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_swao_prio1_out_tpda_aoss: endpoint {
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remote-endpoint =
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<&tpda_aoss_in_tpdm_swao_prio1>;
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};
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};
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};
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};
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tpdm_swao_prio2: tpdm@10b0b000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10b0b000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-swao-prio-2";
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atid = <71>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_swao_prio2_out_tpda_aoss: endpoint {
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remote-endpoint =
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<&tpda_aoss_in_tpdm_swao_prio2>;
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};
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};
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};
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};
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tpdm_swao_prio3: tpdm@10b0c000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10b0c000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-swao-prio-3";
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atid = <71>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_swao_prio3_out_tpda_aoss: endpoint {
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remote-endpoint =
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<&tpda_aoss_in_tpdm_swao_prio3>;
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};
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};
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};
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};
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tpdm_lpass: tpdm@10844000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10844000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-lpass";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_lpass_out_funnel_lpass_dl: endpoint {
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remote-endpoint =
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<&funnel_lpass_dl_in_tpdm_lpass>;
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};
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};
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};
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};
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tpdm_ddr_ch0: tpdm@10d20000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10d20000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-ddr-ch0";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_ddr_ch0_out_funnel_ddr_ch0: endpoint {
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remote-endpoint =
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<&funnel_ddr_ch0_in_tpdm_ddr_ch0>;
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};
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};
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};
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};
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tpdm_ddr: tpdm@10d00000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10d00000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-ddr";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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status = "disabled";
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out-ports {
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port {
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tpdm_ddr_out_funnel_ddr0: endpoint {
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remote-endpoint =
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<&funnel_ddr0_in_tpdm_ddr>;
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};
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};
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};
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};
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tpdm_shrm: tpdm@10d01000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10d01000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-shrm";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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status = "disabled";
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out-ports {
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port {
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tpdm_shrm_out_funnel_ddr0: endpoint {
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remote-endpoint =
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<&funnel_ddr0_in_tpdm_shrm>;
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};
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};
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};
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};
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tpdm_video: tpdm@10830000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10830000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-video";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_video_out_funnel_video: endpoint {
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remote-endpoint =
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<&funnel_video_in_tpdm_video>;
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};
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};
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};
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};
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tpdm_mdss: tpdm@10c60000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10c60000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-mdss";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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status = "disabled";
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out-ports {
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port {
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tpdm_mdss_out_tpda_dl_center: endpoint {
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remote-endpoint =
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<&tpda_dl_center_in_tpdm_mdss>;
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};
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};
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};
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};
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tpdm_dlmm: tpdm@10c08000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10c08000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-mm";
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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atid = <79>;
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out-ports {
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port {
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tpdm_dlmm_out_funnel_dlmm: endpoint {
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remote-endpoint =
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<&funnel_dlmm_in_tpdm_dlmm>;
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};
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};
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};
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};
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tpdm_rdpm: tpdm@10c38000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10c38000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-rdpm";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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status = "disabled";
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out-ports {
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port {
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tpdm_dl_west0_out_funnel_dl_west: endpoint {
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remote-endpoint =
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<&funnel_dl_west_in_tpdm_dl_west0>;
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};
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};
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};
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};
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tpdm_rdpm_mx: tpdm@10c39000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10c39000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-rdpm-mx";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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status = "disabled";
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out-ports {
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port {
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tpdm_dl_west1_out_funnel_dl_west: endpoint {
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remote-endpoint =
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<&funnel_dl_west_in_tpdm_dl_west1>;
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};
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};
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};
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};
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tpdm_turing: tpdm@10980000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10980000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-turing";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_turing_out_funnel_turing: endpoint {
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remote-endpoint =
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<&funnel_turing_in_tpdm_turing>;
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};
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};
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};
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};
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tpdm_turing_llm: tpdm@10981000 {
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compatible = "qcom,coresight-dummy";
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coresight-name = "coresight-tpdm-turing-llm";
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qcom,dummy-source;
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out-ports {
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port {
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tpdm_turing_llm_out_funnel_turing: endpoint {
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remote-endpoint =
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<&funnel_turing_in_tpdm_turing_llm>;
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};
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};
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};
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};
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tpdm_gpu: tpdm@10900000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10900000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-gpu";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_gpu_out_funnel_gpu_dl: endpoint {
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remote-endpoint =
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<&funnel_gpu_dl_in_tpdm_gpu>;
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};
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};
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};
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};
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tpdm_prng: tpdm@10841000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x10841000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-prng";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_prng_out_tpda_dl_center: endpoint {
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remote-endpoint =
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<&tpda_dl_center_in_tpdm_prng>;
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};
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};
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};
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};
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tpdm_qm: tpdm@109d0000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x109d0000 0x1000>;
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reg-names = "tpdm-base";
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|
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coresight-name = "coresight-tpdm-qm";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_qm_out_tpda_dl_center: endpoint {
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remote-endpoint =
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<&tpda_dl_center_in_tpdm_qm>;
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};
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};
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};
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};
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tpdm_gcc: tpdm@1082c000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x1082c000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-gcc";
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atid = <78>;
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clocks = <&aoss_qmp>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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tpdm_gcc_out_tpda_dl_center: endpoint {
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remote-endpoint =
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<&tpda_dl_center_in_tpdm_gcc>;
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};
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};
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|
};
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};
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|
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tpdm_vsense: tpdm@10840000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10840000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-vsense";
|
|
atid = <78>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_vsense_out_tpda_dl_center: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_in_tpdm_vsense>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_pimem: tpdm@10850000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10850000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-pimem";
|
|
atid = <78>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_pime_out_tpda_dl_center: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_in_tpdm_pime>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_dlct0: tpdm@10c28000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10c28000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-dlct";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
atid = <78>;
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_dl_ct0_out_tpda_dl_center: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_in_tpdm_dl_ct0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_dlct1: tpdm@10c29000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10c29000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-ipcc";
|
|
atid = <78>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_dl_ct1_out_tpda_dl_center: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_in_tpdm_dl_ct1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_swao: tpdm@10b0d000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10b0d000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-swao-1";
|
|
atid = <71>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_swao_out_tpda_aoss: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_aoss_in_tpdm_swao>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_dlct3: tpdm@10c30000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10c30000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-dlct3";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
atid = <79>;
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_dlct3_out_tpda_dlct3: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dlct3_in_tpdm_dlct3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_spdm: tpdm@1000f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x1000f000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-spdm";
|
|
atid = <65>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_spdm_out_tpda_qdss: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_qdss_in_tpdm_spdm>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_wpss: tpdm@10c70000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10c70000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-wpss";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
atid = <79>;
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_wpss_out_funnel_wpss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_wpss_in_tpdm_wpss>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_wpss1: tpdm@10c71000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10c71000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
atid = <97>;
|
|
coresight-name = "coresight-tpdm-wpss-1";
|
|
status = "disabled";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_wpss1_out_funnel_wpss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_wpss_in_tpdm_wpss1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
wpss_etm {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
|
|
coresight-name = "coresight-wpss-etm0";
|
|
qcom,inst-id = <3>;
|
|
atid = <44>;
|
|
|
|
out-ports {
|
|
port {
|
|
wpss_etm_out_funnel_wpss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_wpss_in_wpss_etm>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_dcc: tpdm@10003000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10003000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-dcc";
|
|
atid = <65>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,hw-enable-check;
|
|
out-ports {
|
|
port {
|
|
tpdm_dcc_out_tpda_qdss: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_qdss_in_tpdm_dcc>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_dl_north: tpdm@10ac0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10ac0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-dl-north";
|
|
atid = <97>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_dl_north_out_tpda_dl_north: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_north_in_tpdm_dl_north>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_llm_silver: tpdm@128a0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x128a0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-llm-silver";
|
|
atid = <66>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_llm_silver_out_tpda_apss: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_apss_in_tpdm_llm_silver>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_apss0: tpdm@12860000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x12860000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-actpm";
|
|
atid = <66>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_apss0_out_tpda_apss: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_apss_in_tpdm_apss0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_apss1: tpdm@12861000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x12861000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-apss";
|
|
atid = <66>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_apss1_out_tpda_apss: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_apss_in_tpdm_apss1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_sdcc5: tpdm@10c20000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10c20000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-sdcc5";
|
|
atid = <97>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
status = "disabled";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_sdcc5_out_tpda_dl_north: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_north_in_tpdm_sdcc5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_tmess_prng: tpdm@10cc9000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10cc9000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-tmess-prng";
|
|
atid = <85>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
status = "disabled";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_tmess_prng_out_tpda_tmess: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_tmess_in_tpdm_tmess_prng>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_tmess1: tpdm@10cc1000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10cc1000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-tmess-1";
|
|
atid = <85>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_tmess0_out_tpda_tmess: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_tmess_in_tpdm_tmess0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm_tmess0: tpdm@10cc0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb968>;
|
|
reg = <0x10cc0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
|
|
coresight-name = "coresight-tpdm-tmess-0";
|
|
atid = <85>;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
port {
|
|
tpdm_tmess1_out_tpda_tmess: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_tmess_in_tpdm_tmess1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
|
|
funnel_lpass_lpi: funnel@10b44000 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-lpass_lpi";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_lpass_lpi_in_audio_etm0: endpoint {
|
|
remote-endpoint =
|
|
<&audio_etm0_out_funnel_lpass_lpi>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
funnel_lpass_lpi_in_lpass_stm: endpoint {
|
|
remote-endpoint =
|
|
<&lpass_stm_out_funnel_lpass_lpi>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
funnel_lpass_lpi_in_tpdm_lpass_lpi: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_lpass_lpi_out_funnel_lpass_lpi>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_lpass_lpi_out_funnel_aoss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_aoss_in_funnel_lpass_lpi>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_gpu_dl: funnel@10902000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10902000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-gpu_dl";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_gpu_dl_in_tpdm_gpu: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_gpu_out_funnel_gpu_dl>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_gpu_dl_out_tpda_dl_center: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_in_funnel_gpu_dl>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_video: funnel@10832000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10832000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-video";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_video_in_tpdm_video: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_video_out_funnel_video>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_video_out_funnel_dlmm: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dlmm_in_funnel_video>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
|
|
funnel_dlmm: funnel@10c0a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10c0a000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-dlmm";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_dlmm_in_funnel_video: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_video_out_funnel_dlmm>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
funnel_dlmm_in_tpdm_dlmm: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_dlmm_out_funnel_dlmm>;
|
|
};
|
|
};
|
|
|
|
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_dlmm_out_tpda_dlct3_2: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dlct3_2_in_funnel_dlmm>;
|
|
source = <&tpdm_video>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_dlmm_out_tpda_dlct3_5: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dlct3_5_in_funnel_dlmm>;
|
|
source = <&tpdm_dlmm>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_lpass_dl: funnel@10846000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10846000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-lpass_dl";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_lpass_dl_in_tpdm_lpass: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_lpass_out_funnel_lpass_dl>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_lpass_dl_out_tpda_dl_center: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_in_funnel_lpass_dl>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_ddr_ch0: funnel@10d22000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10d22000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-ddr_ch0";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_ddr_ch0_in_tpdm_ddr_ch0: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_ddr_ch0_out_funnel_ddr_ch0>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_ddr_ch0_out_funnel_ddr0: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_ddr0_in_funnel_ddr_ch0>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
|
|
funnel_ddr0: funnel@10d03000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10d03000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-ddr0";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_ddr0_in_funnel_ddr_ch0: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_ddr_ch0_out_funnel_ddr0>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
funnel_ddr0_in_tpdm_shrm: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_shrm_out_funnel_ddr0>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
funnel_ddr0_in_tpdm_ddr: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_ddr_out_funnel_ddr0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_ddr0_out_tpda_dl_center_5: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_5_in_funnel_ddr0>;
|
|
source = <&tpdm_ddr_ch0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_ddr0_out_tpda_dl_center_7: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_7_in_funnel_ddr0>;
|
|
source = <&tpdm_ddr>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
funnel_ddr0_out_tpda_dl_center_8: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_8_in_funnel_ddr0>;
|
|
source = <&tpdm_shrm>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel_wpss: funnel@10c73000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10c73000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-wpss";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_wpss_in_tpdm_wpss: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_wpss_out_funnel_wpss>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_wpss_in_tpdm_wpss1: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_wpss1_out_funnel_wpss>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
funnel_wpss_in_wpss_etm: endpoint {
|
|
remote-endpoint =
|
|
<&wpss_etm_out_funnel_wpss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_wpss_out_tpda_dlct3: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dlct3_in_funnel_wpss>;
|
|
source = <&tpdm_wpss>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_wpss_out_funnel_dlct3: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dlct3_in_funnel_wpss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_dl_west: funnel@10c3a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10c3a000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-dl_west";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
funnel_dl_west_in_tpdm_dl_west1: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_dl_west1_out_funnel_dl_west>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
funnel_dl_west_in_tpdm_dl_west0: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_dl_west0_out_funnel_dl_west>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_dl_west_out_tpda_dl_center_13: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_13_in_funnel_dl_west>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_dl_west_out_tpda_dl_center_14: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_14_in_funnel_dl_west>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel_turing_dup: funnel@10984000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10984000 0x1000>,
|
|
<0x10983000 0x1000>;
|
|
reg-names = "funnel-base-dummy", "funnel-base-real";
|
|
|
|
coresight-name = "coresight-funnel-turing_dup";
|
|
|
|
qcom,duplicate-funnel;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@3 {
|
|
reg = <3>;
|
|
funnel_turing_dup_in_turing_etm0: endpoint {
|
|
remote-endpoint =
|
|
<&turing_etm0_out_funnel_turing_dup>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
port {
|
|
funnel_turing_dup_out_funnel_turing: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_turing_in_funnel_turing_dup>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_turing: funnel@10983000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10983000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-turing";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_turing_in_tpdm_turing_llm: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_turing_llm_out_funnel_turing>;
|
|
};
|
|
};
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_turing_in_tpdm_turing: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_turing_out_funnel_turing>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
funnel_turing_in_funnel_turing_dup: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_turing_dup_out_funnel_turing>;
|
|
};
|
|
};
|
|
|
|
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_turing_out_tpda_dl_center_15: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_15_in_funnel_turing>;
|
|
source = <&tpdm_turing>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_turing_out_tpda_dl_center_16: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_16_in_funnel_turing>;
|
|
source = <&tpdm_turing_llm>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
funnel_turing_out_funnel_dl_center: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dl_center_in_funnel_turing>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda_dlct3: tpda@10c32000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb969>;
|
|
|
|
reg = <0x10c32000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
|
|
coresight-name = "coresight-tpda-dlct3";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,tpda-atid = <79>;
|
|
qcom,dsb-elem-size = <0 32>,
|
|
<2 32>,
|
|
<5 32>,
|
|
<10 32>;
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@10 {
|
|
reg = <10>;
|
|
tpda_dlct3_in_tpdm_dlct3: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_dlct3_out_tpda_dlct3>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
tpda_dlct3_2_in_funnel_dlmm: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dlmm_out_tpda_dlct3_2>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
tpda_dlct3_5_in_funnel_dlmm: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dlmm_out_tpda_dlct3_5>;
|
|
};
|
|
};
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
tpda_dlct3_in_funnel_wpss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_wpss_out_tpda_dlct3>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
tpda_dlct3_out_funnel_dlct3: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dlct3_in_tpda_dlct3>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_dlct3: funnel@10c33000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10c33000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-dlct3";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_dlct3_in_funnel_wpss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_wpss_out_funnel_dlct3>;
|
|
};
|
|
};
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_dlct3_in_tpda_dlct3: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dlct3_out_funnel_dlct3>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_dlct3_out_funnel_in1: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_in1_in_funnel_dlct3>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
tpda_tmess: tpda@10cc4000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb969>;
|
|
|
|
reg = <0x10cc4000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
|
|
coresight-name = "coresight-tpda-tmess";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,tpda-atid = <85>;
|
|
|
|
qcom,dsb-elem-size = <2 32>;
|
|
qcom,cmb-elem-size = <0 32>,
|
|
<1 32>,
|
|
<2 64>;
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
tpda_tmess_in_tpdm_tmess_prng: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_tmess_prng_out_tpda_tmess>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
tpda_tmess_in_tpdm_tmess1: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_tmess1_out_tpda_tmess>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
tpda_tmess_in_tpdm_tmess0: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_tmess0_out_tpda_tmess>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
tpda_tmess_out_funnel_tmess: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_tmess_in_tpda_tmess>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_tmess: funnel@10cc5000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10cc5000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-tmess";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_tmess_in_tpda_tmess: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_tmess_out_funnel_tmess>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_tmess_out_funnel_dl_north: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dl_north_in_funnel_tmess>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
tpda_dl_north: tpda@10ac1000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb969>;
|
|
|
|
reg = <0x10ac1000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
|
|
coresight-name = "coresight-tpda-dl_north";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
qcom,tpda-atid = <97>;
|
|
|
|
qcom,dsb-elem-size = <2 32>;
|
|
qcom,cmb-elem-size = <0 32>;
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
tpda_dl_north_in_tpdm_sdcc5: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_sdcc5_out_tpda_dl_north>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
tpda_dl_north_in_tpdm_dl_north: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_dl_north_out_tpda_dl_north>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
tpda_dl_north_out_funnel_dl_north: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dl_north_in_tpda_dl_north>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_dl_north: funnel@10ac2000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10ac2000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-dl_north";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_dl_north_in_tpda_dl_north: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_north_out_funnel_dl_north>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
funnel_dl_north_in_funnel_tmess: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_tmess_out_funnel_dl_north>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_dl_north_out_funnel_in1: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_in1_in_funnel_dl_north>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
tpda_apss: tpda@12863000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb969>;
|
|
|
|
reg = <0x12863000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
|
|
coresight-name = "coresight-tpda-apss";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,tpda-atid = <66>;
|
|
|
|
qcom,dsb-elem-size = <4 32>;
|
|
qcom,cmb-elem-size = <0 32>,
|
|
<2 64>;
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
tpda_apss_in_tpdm_llm_silver: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_llm_silver_out_tpda_apss>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
tpda_apss_in_tpdm_apss0: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_apss0_out_tpda_apss>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
tpda_apss_in_tpdm_apss1: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_apss1_out_tpda_apss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
tpda_apss_out_funnel_apss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_apss_in_tpda_apss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
ipcb_tgu: tgu@10b0e000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb999>;
|
|
|
|
reg = <0x10b0e000 0x1000>;
|
|
reg-names = "tgu-base";
|
|
|
|
tgu-steps = <3>;
|
|
tgu-conditions = <4>;
|
|
tgu-regs = <4>;
|
|
tgu-timer-counters = <8>;
|
|
|
|
coresight-name = "coresight-tgu-ipcb";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
spmi_tgu0: tgu@10b0f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb999>;
|
|
|
|
reg = <0x10b0f000 0x1000>;
|
|
reg-names = "tgu-base";
|
|
|
|
tgu-steps = <3>;
|
|
tgu-conditions = <4>;
|
|
tgu-regs = <9>;
|
|
tgu-timer-counters = <8>;
|
|
|
|
coresight-name = "coresight-tgu-spmi0";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
spmi_tgu1: tgu@10b10000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb999>;
|
|
|
|
reg = <0x10b10000 0x1000>;
|
|
reg-names = "tgu-base";
|
|
|
|
tgu-steps = <3>;
|
|
tgu-conditions = <4>;
|
|
tgu-regs = <9>;
|
|
tgu-timer-counters = <8>;
|
|
|
|
coresight-name = "coresight-tgu-spmi1";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
etm0 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb95d>;
|
|
reg = <0x12040000 0x1000>;
|
|
cpu = <&CPU0>;
|
|
|
|
coresight-name = "coresight-etm0";
|
|
qcom,skip-power-up;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
atid = <1>;
|
|
out-ports {
|
|
port {
|
|
ete0_out_funnel_ete: endpoint {
|
|
remote-endpoint = <&funnel_ete_in_ete0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm1 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb95d>;
|
|
reg = <0x12140000 0x1000>;
|
|
cpu = <&CPU1>;
|
|
|
|
coresight-name = "coresight-etm1";
|
|
qcom,skip-power-up;
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
atid = <2>;
|
|
out-ports {
|
|
port {
|
|
ete1_out_funnel_ete: endpoint {
|
|
remote-endpoint = <&funnel_ete_in_ete1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm2 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb95d>;
|
|
reg = <0x12240000 0x1000>;
|
|
cpu = <&CPU2>;
|
|
|
|
coresight-name = "coresight-etm2";
|
|
qcom,skip-power-up;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
atid = <3>;
|
|
out-ports {
|
|
port {
|
|
ete2_out_funnel_ete: endpoint {
|
|
remote-endpoint = <&funnel_ete_in_ete2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm3 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb95d>;
|
|
reg = <0x12340000 0x1000>;
|
|
cpu = <&CPU3>;
|
|
|
|
coresight-name = "coresight-etm3";
|
|
qcom,skip-power-up;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
atid = <4>;
|
|
out-ports {
|
|
port {
|
|
ete3_out_funnel_ete: endpoint {
|
|
remote-endpoint = <&funnel_ete_in_ete3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel_apss: funnel@12810000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x12810000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-apss";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_ete_in_ete0: endpoint {
|
|
remote-endpoint =
|
|
<&ete0_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_ete_in_ete1: endpoint {
|
|
remote-endpoint =
|
|
<&ete1_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
funnel_ete_in_ete2: endpoint {
|
|
remote-endpoint =
|
|
<&ete2_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
funnel_ete_in_ete3: endpoint {
|
|
remote-endpoint =
|
|
<&ete3_out_funnel_ete>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
funnel_apss_in_tpda_apss: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_apss_out_funnel_apss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_apss_out_funnel_in1: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_in1_in_funnel_apss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
tpda_dl_center: tpda@10c2b000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb969>;
|
|
|
|
reg = <0x10c2b000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
|
|
coresight-name = "coresight-tpda-dl_center";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,tpda-atid = <78>;
|
|
|
|
qcom,dsb-elem-size = <0 32>,
|
|
<4 32>,
|
|
<5 32>,
|
|
<7 32>,
|
|
<15 32>,
|
|
<17 32>,
|
|
<20 32>,
|
|
<21 32>,
|
|
<25 32>,
|
|
<26 32>;
|
|
qcom,cmb-elem-size = <0 32>,
|
|
<7 32>,
|
|
<8 64>,
|
|
<13 64>,
|
|
<14 64>,
|
|
<16 32>,
|
|
<19 32>,
|
|
<22 32>,
|
|
<25 64>,
|
|
<27 64>;
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@25 {
|
|
reg = <25>;
|
|
tpda_dl_center_in_tpdm_pime: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_pime_out_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
port@13 {
|
|
reg = <13>;
|
|
tpda_dl_center_13_in_funnel_dl_west: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dl_west_out_tpda_dl_center_13>;
|
|
};
|
|
};
|
|
|
|
port@27 {
|
|
reg = <27>;
|
|
tpda_dl_center_in_tpdm_dl_ct1: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_dl_ct1_out_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
port@15 {
|
|
reg = <15>;
|
|
tpda_dl_center_15_in_funnel_turing: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_turing_out_tpda_dl_center_15>;
|
|
};
|
|
};
|
|
|
|
port@14 {
|
|
reg = <14>;
|
|
tpda_dl_center_14_in_funnel_dl_west: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dl_west_out_tpda_dl_center_14>;
|
|
};
|
|
};
|
|
|
|
port@17 {
|
|
reg = <17>;
|
|
tpda_dl_center_in_funnel_gpu_dl: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_gpu_dl_out_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
port@16 {
|
|
reg = <16>;
|
|
tpda_dl_center_16_in_funnel_turing: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_turing_out_tpda_dl_center_16>;
|
|
};
|
|
};
|
|
|
|
port@19 {
|
|
reg = <19>;
|
|
tpda_dl_center_in_tpdm_prng: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_prng_out_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
port@22 {
|
|
reg = <22>;
|
|
tpda_dl_center_in_tpdm_vsense: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_vsense_out_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
port@26 {
|
|
reg = <26>;
|
|
tpda_dl_center_in_tpdm_dl_ct0: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_dl_ct0_out_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
port@20 {
|
|
reg = <20>;
|
|
tpda_dl_center_in_tpdm_qm: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_qm_out_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
tpda_dl_center_in_tpdm_mdss: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_mdss_out_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
tpda_dl_center_5_in_funnel_ddr0: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_ddr0_out_tpda_dl_center_5>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
tpda_dl_center_in_funnel_lpass_dl: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_lpass_dl_out_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
tpda_dl_center_7_in_funnel_ddr0: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_ddr0_out_tpda_dl_center_7>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <8>;
|
|
tpda_dl_center_8_in_funnel_ddr0: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_ddr0_out_tpda_dl_center_8>;
|
|
};
|
|
};
|
|
|
|
port@21 {
|
|
reg = <21>;
|
|
tpda_dl_center_in_tpdm_gcc: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_gcc_out_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
tpda_dl_center_out_funnel_dl_center: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dl_center_in_tpda_dl_center>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_dl_center: funnel@10c2c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10c2c000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-dl_center";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_dl_center_in_tpda_dl_center: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_dl_center_out_funnel_dl_center>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
funnel_dl_center_in_funnel_turing: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_turing_out_funnel_dl_center>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_dl_center_out_funnel_in1: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_in1_in_funnel_dl_center>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
tpda_qdss: tpda@10004000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb969>;
|
|
|
|
reg = <0x10004000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
|
|
coresight-name = "coresight-tpda-qdss";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,tpda-atid = <65>;
|
|
|
|
qcom,cmb-elem-size = <0 32>,
|
|
<1 32>;
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
tpda_qdss_in_tpdm_spdm: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_spdm_out_tpda_qdss>;
|
|
};
|
|
};
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
tpda_qdss_in_tpdm_dcc: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_dcc_out_tpda_qdss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
tpda_qdss_out_funnel_in0: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_in0_in_tpda_qdss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_in0: funnel@10041000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10041000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-in0";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_in0_in_snoc: endpoint {
|
|
remote-endpoint =
|
|
<&snoc_out_funnel_in0>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
funnel_in0_in_tpda_qdss: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_qdss_out_funnel_in0>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
funnel_in0_in_stm: endpoint {
|
|
remote-endpoint =
|
|
<&stm_out_funnel_in0>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_in0_out_funnel_merge: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_merge_in_funnel_in0>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_in1: funnel@10042000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10042000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-in1";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_in1_in_funnel_dl_north: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dl_north_out_funnel_in1>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
funnel_in1_in_funnel_dlct3: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dlct3_out_funnel_in1>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
funnel_in1_in_funnel_apss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_apss_out_funnel_in1>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
funnel_in1_in_funnel_dl_center: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_dl_center_out_funnel_in1>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_in1_out_funnel_merge: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_merge_in_funnel_in1>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_merge: funnel@10045000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10045000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-merge";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel_merge_in_funnel_in1: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_in1_out_funnel_merge>;
|
|
};
|
|
};
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel_merge_in_funnel_in0: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_in0_out_funnel_merge>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_merge_out_funnel_aoss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_aoss_in_funnel_merge>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
tpda_aoss: tpda@10b08000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb969>;
|
|
|
|
reg = <0x10b08000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
|
|
coresight-name = "coresight-tpda-aoss";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
qcom,tpda-atid = <71>;
|
|
|
|
qcom,dsb-elem-size = <2 32>;
|
|
qcom,cmb-elem-size = <0 64>,
|
|
<1 64>,
|
|
<2 64>,
|
|
<3 64>;
|
|
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
tpda_aoss_in_tpdm_swao_prio1: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_swao_prio1_out_tpda_aoss>;
|
|
};
|
|
};
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
tpda_aoss_in_tpdm_swao_prio0: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_swao_prio0_out_tpda_aoss>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
tpda_aoss_in_tpdm_swao_prio3: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_swao_prio3_out_tpda_aoss>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
tpda_aoss_in_tpdm_swao_prio2: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_swao_prio2_out_tpda_aoss>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
tpda_aoss_in_tpdm_swao: endpoint {
|
|
remote-endpoint =
|
|
<&tpdm_swao_out_tpda_aoss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
tpda_aoss_out_funnel_aoss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_aoss_in_tpda_aoss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
funnel_aoss: funnel@10b04000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb908>;
|
|
|
|
reg = <0x10b04000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
|
|
coresight-name = "coresight-funnel-aoss";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
funnel_aoss_in_funnel_lpass_lpi: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_lpass_lpi_out_funnel_aoss>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
funnel_aoss_in_funnel_merge: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_merge_out_funnel_aoss>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
funnel_aoss_in_tpda_aoss: endpoint {
|
|
remote-endpoint =
|
|
<&tpda_aoss_out_funnel_aoss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
funnel_aoss_out_tmc_etf: endpoint {
|
|
remote-endpoint =
|
|
<&tmc_etf_in_funnel_aoss>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
dummy_eud: dummy_sink {
|
|
compatible = "qcom,coresight-dummy";
|
|
|
|
coresight-name = "coresight-eud";
|
|
|
|
qcom,dummy-sink;
|
|
in-ports {
|
|
port {
|
|
eud_in_replicator_swao: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_swao_out_eud>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc_etf: tmc@10b05000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb961>;
|
|
reg = <0x10b05000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
|
|
coresight-name = "coresight-tmc-etf";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
port {
|
|
tmc_etf_in_funnel_aoss: endpoint {
|
|
remote-endpoint =
|
|
<&funnel_aoss_out_tmc_etf>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
port {
|
|
tmc_etf_out_replicator_swao: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_swao_in_tmc_etf>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator_swao: replicator@10b06000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb909>;
|
|
reg = <0x10b06000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
|
|
coresight-name = "coresight-replicator-swao";
|
|
|
|
//qcom,replicator-loses-context;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
port {
|
|
replicator_swao_in_tmc_etf: endpoint {
|
|
remote-endpoint =
|
|
<&tmc_etf_out_replicator_swao>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
replicator_swao_out_replicator_qdss: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_qdss_in_replicator_swao>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
replicator_swao_out_eud: endpoint {
|
|
remote-endpoint =
|
|
<&eud_in_replicator_swao>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator_qdss: replicator@10046000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb909>;
|
|
reg = <0x10046000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
|
|
coresight-name = "coresight-replicator-qdss";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
port {
|
|
replicator_qdss_in_replicator_swao: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_swao_out_replicator_qdss>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
replicator_qdss_out_replicator_etr: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_etr_in_replicator_qdss>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator_etr: replicator@1004e000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb909>;
|
|
reg = <0x1004e000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
|
|
coresight-name = "coresight-replicator-etr";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
port {
|
|
replicator_etr_in_replicator_qdss: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_qdss_out_replicator_etr>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
replicator_etr_out_tmc_etr: endpoint {
|
|
remote-endpoint =
|
|
<&tmc_etr_in_replicator_etr>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
replicator_etr_out_tmc_etr1: endpoint {
|
|
remote-endpoint =
|
|
<&tmc_etr1_in_replicator_etr>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc_etr: tmc@10048000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb961>;
|
|
reg = <0x10048000 0x1000>,
|
|
<0x10064000 0x16000>;
|
|
reg-names = "tmc-base", "bam-base";
|
|
|
|
qcom,iommu-dma = "bypass";
|
|
iommus = <&apps_smmu 0x00c0 0>,
|
|
<&apps_smmu 0x00a0 0>;
|
|
|
|
qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
|
|
|
|
qcom,sw-usb;
|
|
dma-coherent;
|
|
coresight-name = "coresight-tmc-etr";
|
|
|
|
coresight-csr = <&csr>;
|
|
csr-atid-offset = <0xf8>;
|
|
csr-irqctrl-offset = <0x6c>;
|
|
byte-cntr-name = "byte-cntr";
|
|
byte-cntr-class-name = "coresight-tmc-etr-stream";
|
|
|
|
interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "byte-cntr-irq";
|
|
|
|
arm,scatter-gather;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
port {
|
|
tmc_etr_in_replicator_etr: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_etr_out_tmc_etr>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc_etr1: tmc@1004f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0x000bb961>;
|
|
reg = <0x1004f000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
|
|
coresight-name = "coresight-tmc-etr1";
|
|
|
|
iommus = <&apps_smmu 0x00e0 0>;
|
|
qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
|
|
dma-coherent;
|
|
|
|
coresight-csr = <&csr>;
|
|
csr-atid-offset = <0x108>;
|
|
csr-irqctrl-offset = <0x70>;
|
|
byte-cntr-name = "byte-cntr1";
|
|
byte-cntr-class-name = "coresight-tmc-etr1-stream";
|
|
|
|
interrupts = <GIC_SPI 269 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "byte-cntr-irq";
|
|
|
|
arm,scatter-gather;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
|
|
in-ports {
|
|
port {
|
|
tmc_etr1_in_replicator_etr: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_etr_out_tmc_etr1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qc_cti: cti@10010000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10010000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-qc_cti";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
iris_dl_cti: cti@10831000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10831000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-iris_dl_cti";
|
|
status = "disabled";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
lpass_cti: cti@10845000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10845000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-lpass_cti";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpu_cti: cti@10901000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10901000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-gpu";
|
|
status = "disabled";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
apss_cti: cti@12862000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12862000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-apss_dl_cti";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
apss_cti0: cti@128e0000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x128e0000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-apss_cti0";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
apss_cti1: cti@128f0000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x128f0000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-apss_cti1";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
apss_cti2: cti@12900000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x12900000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-apss_cti2";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cortex_m3: cti@10b13000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b13000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-cortex_m3";
|
|
|
|
status = "disabled";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cti0: cti@10c2a000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10c2a000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-cti0";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
ddr_ch01_dl_cti_0: cti@10d21000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10d21000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-ddr_ch01_dl_cti_0";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
ddr_dl_0_cti_0: cti@10d02000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10d02000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-ddr_dl_0_cti_0";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
ddr_dl_1_cti_0: cti@10d0c000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10d0c000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-ddr_dl_1_cti_0";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpu_cortex_m3: cti@10962000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10962000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-gpu_cortex_m3";
|
|
|
|
status = "disabled";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
lpass_dl_cti: cti@10845000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10845000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-lpass_dl_cti";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
lpass_lpi_cti: cti@10b41000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b41000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-lpass_lpi_cti";
|
|
|
|
status = "disabled";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
lpass_q6_cti: cti@10b4b000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b4b000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-lpass_q6_cti";
|
|
|
|
status = "disabled";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
mdss_dl_cti: cti@10c61000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10c61000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-mdss_dl_cti";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
status= "disabled";
|
|
};
|
|
|
|
riscv_cti: cti@1282b000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x1282b000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-riscv_cti";
|
|
|
|
status = "disabled";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
swao_cti: cti@10b00000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10b00000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-swao_cti";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
qcom,extended_cti;
|
|
};
|
|
|
|
tmess_cpu: cti@10cd1000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10cd1000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-tmess_cpu";
|
|
|
|
status = "disabled";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
tmess_cti_0: cti@10cc2000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10cc2000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-tmess_cti_0";
|
|
|
|
qcom,extended_cti;
|
|
status = "disabled";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
tmess_cti_1: cti@10cc3000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10cc3000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-tmess_cti_1";
|
|
|
|
qcom,extended_cti;
|
|
status = "disabled";
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
turing_dl_cti_0: cti@10982000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10982000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-turing_dl_cti_0";
|
|
|
|
qcom,extended_cti;
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
turing_q6_cti: cti@1098b000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x1098b000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-turing_q6_cti";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
wlan_q6_cti: cti@10C7B000 {
|
|
compatible = "arm,coresight-cti", "arm,primecell";
|
|
reg = <0x10C7B000 0x1000>;
|
|
|
|
arm,primecell-periphid = <0x000bb922>;
|
|
coresight-name = "coresight-cti-wlan_q6_cti";
|
|
|
|
clocks = <&aoss_qmp>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
};
|