mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
2121bad3aa
Add qseecom, smcinvoke, shmbridge and tz-logs support for ravelin. Change-Id: I820e8b54baa7e1fc46374166f5b2947dcb098564
1344 lines
30 KiB
Plaintext
1344 lines
30 KiB
Plaintext
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,camcc-ravelin.h>
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#include <dt-bindings/clock/qcom,dispcc-ravelin.h>
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#include <dt-bindings/clock/qcom,gcc-ravelin.h>
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#include <dt-bindings/clock/qcom,gpucc-ravelin.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,ravelin.h>
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/ {
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model = "Qualcomm Technologies, Inc. Ravelin";
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compatible = "qcom,ravelin";
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qcom,msm-id = <568 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen: chosen { };
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_memory: reserved-memory { };
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aliases {
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serial0 = &qupv3_se2_2uart;
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ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
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mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
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mmc1 = &sdhc_2; /* SDC2 SD card slot */
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};
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firmware: firmware {};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>;
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>;
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU6>;
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};
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core1 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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idle-states {
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entry-method = "psci";
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SILVER_CPU_OFF: silver-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <350>;
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exit-latency-us = <900>;
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min-residency-us = <1774>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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SILVER_CPU_RAIL_OFF: silver-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <800>;
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exit-latency-us = <750>;
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min-residency-us = <4090>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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GOLD_CPU_OFF: gold-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <400>;
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exit-latency-us = <1550>;
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min-residency-us = <2207>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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GOLD_CPU_RAIL_OFF: gold-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <600>;
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exit-latency-us = <1550>;
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min-residency-us = <4791>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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CLUSTER_OFF: cluster-d4 { /* D4 */
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compatible = "domain-idle-state";
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idle-state-name = "l3-off";
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entry-latency-us = <1050>;
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exit-latency-us = <2500>;
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min-residency-us = <5309>;
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arm,psci-suspend-param = <0x41000044>;
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};
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CX_RET: cx-ret { /* Cx Ret */
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compatible = "domain-idle-state";
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idle-state-name = "cx-ret";
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entry-latency-us = <1561>;
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exit-latency-us = <2801>;
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min-residency-us = <8550>;
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arm,psci-suspend-param = <0x41003344>;
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};
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};
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soc: soc { };
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};
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#include "ravelin-stub-regulator.dtsi"
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#include "msm-arm-smmu-ravelin.dtsi"
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#include "ravelin-dma-heaps.dtsi"
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#include "ravelin-reserved-memory.dtsi"
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#include "ravelin-dma-heaps.dtsi"
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#include "ravelin-usb.dtsi"
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* global autoconfigured region for contiguous allocations */
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system_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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va_md_mem: va_md_mem_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
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reusable;
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size = <0 0x1000000>;
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};
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user_contig_mem: user_contig_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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qseecom_mem: qseecom_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1400000>;
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};
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qseecom_ta_mem: qseecom_ta_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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adsp_mem_heap: adsp_heap_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0xC00000>;
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};
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};
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&firmware {
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qcom_scm {
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compatible = "qcom,scm";
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};
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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};
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qcom_smcinvoke {
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compatible = "qcom,smcinvoke";
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17200000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17200000 0x10000>, /* GICD */
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<0x17260000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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wdog: qcom,wdt@17410000 {
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compatible = "qcom,msm-watchdog";
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reg = <0x17410000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <9360>;
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qcom,ipi-ping;
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qcom,wakeup-enable;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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apps_rsc: rsc@17a00000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x17a00000 0x10000>,
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<0x17a10000 0x10000>,
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<0x17a20000 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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power-domains = <&CLUSTER_PD>;
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apps_bcm_voter: bcm_voter {
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compatible = "qcom,bcm-voter";
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};
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};
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disp_rsc: rsc@af20000 {
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lable = "disp_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0xaf20000 0x10000>;
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reg-names = "drv-0";
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
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qcom,tcs-offset = <0x1c00>;
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qcom,drv-id = <0>;
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,ravelin-pdc", "qcom,pdc";
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reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
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reg-names = "pdc-interrupt-base", "apps-shared-spi-cfg";
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qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>,
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<126 716 12>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: cpu-pd0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD1: cpu-pd1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD2: cpu-pd2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD3: cpu-pd3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD4: cpu-pd4 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD5: cpu-pd5 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD6: cpu-pd6 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD7: cpu-pd7 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CLUSTER_PD: cluster-pd {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_OFF &CX_RET>;
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};
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};
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cluster-device {
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compatible = "qcom,lpm-cluster-dev";
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power-domains = <&CLUSTER_PD>;
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};
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cpuss-sleep-stats@17800054 {
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compatible = "qcom,cpuss-sleep-stats";
|
|
reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
|
|
<0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>,
|
|
<0x17860054 0x4>, <0x17870054 0x4>, <0x17880098 0x4>,
|
|
<0x178C0000 0x10000>;
|
|
reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
|
|
"seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
|
|
"seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
|
|
"seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7",
|
|
"l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
|
|
num-cpus = <8>;
|
|
};
|
|
|
|
rpmh-sleep-stats@c3f0000 {
|
|
compatible = "qcom,rpmh-sleep-stats";
|
|
reg = <0xc3f0000 0x400>;
|
|
ss-name = "modem", "adsp", "adsp_island",
|
|
"apss", "wpss";
|
|
mboxes = <&qmp_aop 0>;
|
|
ddr-freq-update;
|
|
};
|
|
|
|
subsystem-sleep-stats@c3f0000 {
|
|
compatible = "qcom,subsystem-sleep-stats";
|
|
reg = <0xc3f0000 0x400>;
|
|
ddr-freq-update;
|
|
};
|
|
|
|
sys-pm-vx@c320000 {
|
|
compatible = "qcom,sys-pm-violators", "qcom,sys-pm-ravelin";
|
|
reg = <0xc320000 0x0400>;
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "aop";
|
|
};
|
|
|
|
memtimer: timer@17420000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17420000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@17421000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17421000 0x1000>,
|
|
<0x17422000 0x1000>;
|
|
};
|
|
|
|
frame@17423000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17423000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17425000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17425000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17427000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17427000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17429000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17429000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742b000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x1742b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742d000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x1742d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom,secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
qcom,vmid-cp-camera-preview-ro;
|
|
};
|
|
|
|
qcom,mem-buf {
|
|
compatible = "qcom,mem-buf";
|
|
qcom,mem-buf-capabilities = "supplier";
|
|
qcom,vmid = <3>;
|
|
};
|
|
|
|
qcom,mem-buf-msgq {
|
|
compatible = "qcom,mem-buf-msgq";
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x0 0x280000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x00000001>;
|
|
};
|
|
|
|
qcom_tzlog: tz-log@146AA720 {
|
|
compatible = "qcom,tz-log";
|
|
reg = <0x146AA720 0x3000>;
|
|
qcom,hyplog-enabled;
|
|
hyplog-address-offset = <0x410>;
|
|
hyplog-size-offset = <0x414>;
|
|
status = "ok";
|
|
};
|
|
|
|
qcom_qseecom: qseecom@c1700000 {
|
|
compatible = "qcom,qseecom";
|
|
memory-region = <&qseecom_mem>;
|
|
qseecom_mem = <&qseecom_mem>;
|
|
qseecom_ta_mem = <&qseecom_ta_mem>;
|
|
user_contig_mem = <&user_contig_mem>;
|
|
qcom,hlos-num-ce-hw-instances = <1>;
|
|
qcom,hlos-ce-hw-instance = <0>;
|
|
qcom,qsee-ce-hw-instance = <0>;
|
|
qcom,disk-encrypt-pipe-pair = <2>;
|
|
qcom,no-clock-support;
|
|
qcom,appsbl-qseecom-support;
|
|
qcom,commonlib64-loaded-by-uefi;
|
|
qcom,qsee-reentrancy-support = <2>;
|
|
};
|
|
|
|
ipcc_mproc: qcom,ipcc@ed18000 {
|
|
compatible = "qcom,ipcc";
|
|
reg = <0xed18000 0x1000>;
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo_board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <76800000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_0_pipe_clk: pcie_0_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_1_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_tx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
camcc: clock-controller@ade0000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "camcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "dispcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,ravelin-gcc", "syscon";
|
|
reg = <0x100000 0x1f4200>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
|
|
<&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>,
|
|
<&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>,
|
|
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
|
|
clock-names = "bi_tcxo", "sleep_clk",
|
|
"pcie_0_pipe_clk", "ufs_phy_rx_symbol_0_clk",
|
|
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
|
|
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gpucc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
rpmhcc: qcom,rpmhcc {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "rmphcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
tcsr: syscon@1fc0000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fc0000 0x30000>;
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem: qcom,smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_mem>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
sleepstate_smp2p_out: sleepstate-out {
|
|
qcom,entry-name = "sleepstate";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
sleepstate_smp2p_in: qcom,sleepstate-in {
|
|
qcom,entry-name = "sleepstate_see";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p_sleepstate {
|
|
compatible = "qcom,smp2p-sleepstate";
|
|
qcom,smem-states = <&sleepstate_smp2p_out 0>;
|
|
interrupt-parent = <&sleepstate_smp2p_in>;
|
|
interrupts = <0 0>;
|
|
interrupt-names = "smp2p-sleepstate-in";
|
|
};
|
|
|
|
qcom,smp2p-wpss {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <617>, <616>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <13>;
|
|
|
|
wpss_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
wpss_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
};
|
|
|
|
aoss_qmp: power-controller@c300000 {
|
|
compatible = "qcom,ravelin-aoss-qmp";
|
|
reg = <0xc300000 0x400>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
#power-domain-cells = <1>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,qmp = <&aoss_qmp>;
|
|
label = "aop";
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qmp_tme: qcom,qmp-tme {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,remote-pid = <14>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_TME
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "tme_qmp";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_TME
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "tme";
|
|
qcom,early-boot;
|
|
priority = <0>;
|
|
mbox-desc-offset = <0x0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qcom,chd {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "core";
|
|
qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058
|
|
0x17840058 0x17850058 0x17860058 0x17870058>;
|
|
qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060
|
|
0x17840060 0x17850060 0x17860060 0x17870060>;
|
|
};
|
|
|
|
ufsphy_mem: ufsphy_mem@1d87000 {
|
|
reg = <0x1d87000 0xe10>;
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0>;
|
|
|
|
lanes-per-direction = <2>;
|
|
clock-names = "ref_clk_src",
|
|
"ref_aux_clk", "qref_clk",
|
|
"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
|
|
"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
|
|
<&gcc GCC_UFS_0_CLKREF_EN>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
|
|
<&ufs_phy_rx_symbol_0_clk>,
|
|
<&ufs_phy_rx_symbol_1_clk>,
|
|
<&ufs_phy_tx_symbol_0_clk>;
|
|
resets = <&ufshc_mem 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ufshc_mem: ufshc@1d84000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x1d84000 0x3000>;
|
|
reg-names = "ufs_mem";
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufsphy_mem>;
|
|
phy-names = "ufsphy";
|
|
#reset-cells = <1>;
|
|
|
|
lanes-per-direction = <2>;
|
|
dev-ref-clk-freq = <0>; /* 19.2 MHz */
|
|
clock-names =
|
|
"core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"core_clk_ice",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
clocks =
|
|
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
|
freq-table-hz =
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<75000000 300000000>,
|
|
<75000000 403000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
|
|
reset-gpios = <&tlmm 136 GPIO_ACTIVE_LOW>;
|
|
resets = <&gcc GCC_UFS_PHY_BCR>;
|
|
reset-names = "rst";
|
|
|
|
iommus = <&apps_smmu 0x580 0x0>;
|
|
qcom,iommu-dma = "bypass";
|
|
dma-coherent;
|
|
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0xf0>;
|
|
vote = <44>;
|
|
perf;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x0f>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
sdhc_1: sdhci@7C4000 {
|
|
status = "disabled";
|
|
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>;
|
|
reg-names = "hc", "cqhci";
|
|
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
bus-width = <8>;
|
|
non-removable;
|
|
supports-cqe;
|
|
|
|
no-sd;
|
|
no-sdio;
|
|
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
mmc-hs400-enhanced-strobe;
|
|
|
|
cap-mmc-hw-reset;
|
|
|
|
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
|
<&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
|
|
clock-names = "iface", "core", "ice_core";
|
|
|
|
qcom,ice-clk-rates = <300000000 100000000>;
|
|
|
|
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
|
qcom,dll-hsr-list = <0x000F642C 0x0 0x01
|
|
0x2C010800 0x80040868>;
|
|
|
|
/* Add dt entry for gcc hw reset */
|
|
resets = <&gcc GCC_SDCC1_BCR>;
|
|
reset-names = "core_reset";
|
|
|
|
iommus = <&apps_smmu 0x560 0x0>;
|
|
dma-coherent;
|
|
qcom,iommu-dma = "bypass";
|
|
|
|
qos0 {
|
|
mask = <0x03>;
|
|
vote = <44>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x3f>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
sdhc_2: sdhci@8804000 {
|
|
status = "disabled";
|
|
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x08804000 0x1000>;
|
|
reg-names = "hc";
|
|
|
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
bus-width = <4>;
|
|
no-sdio;
|
|
no-mmc;
|
|
qcom,restore-after-cx-collapse;
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
|
|
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
|
qcom,dll-hsr-list = <0x0007642C 0x0 0x10
|
|
0x2C010800 0x80040868>;
|
|
|
|
iommus = <&apps_smmu 0x140 0x0>;
|
|
dma-coherent;
|
|
qcom,iommu-dma = "bypass";
|
|
|
|
qos0 {
|
|
mask = <0x03>;
|
|
vote = <44>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x3f>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
cpu_pmu: cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
qcom,msm-imem@146aa000 {
|
|
compatible = "qcom,msm-imem";
|
|
ranges = <0x0 0x146aa000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x8>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x4>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0xc>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,pil-reloc-info";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
pil@6dc {
|
|
compatible = "qcom,msm-imem-pil-disable-timeout";
|
|
reg = <0x6dc 0x4>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
dload_mode {
|
|
compatible = "qcom,dload-mode";
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
logbuf: qcom,logbuf-vendor-hooks {
|
|
compatible = "qcom,logbuf-vendor-hooks";
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
mini_dump_node {
|
|
compatible = "qcom,minidump";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,msm-adsprpc-mem {
|
|
compatible = "qcom,msm-adsprpc-mem-region";
|
|
memory-region = <&adsp_mem_heap>;
|
|
restrict-access;
|
|
};
|
|
|
|
clk_virt: interconnect@0 {
|
|
compatible = "qcom,ravelin-clk_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mc_virt: interconnect@1 {
|
|
compatible = "qcom,ravelin-mc_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
reg = <0x16E0000 0x13080>;
|
|
compatible = "qcom,ravelin-aggre1_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
reg = <0x1700000 0x1B080>;
|
|
compatible = "qcom,ravelin-aggre2_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
cnoc2: interconnect@1500000 {
|
|
reg = <0x1500000 0x6200>;
|
|
compatible = "qcom,ravelin-cnoc2";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
conc3: interconnect@1510000 {
|
|
reg = <0x01510000 0xF200>;
|
|
compatible = "qcom,ravelin-cnoc3";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
gem_noc: interconnect@19100000 {
|
|
reg = <0x19100000 0xBC080>;
|
|
compatible = "qcom,ravelin-gem_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
lpass_ag_noc: interconnect@3C40000 {
|
|
reg = <0x3C40000 0x17200>;
|
|
compatible = "qcom,ravelin-lpass_ag_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1740000 {
|
|
reg = <0x1740000 0x19080>;
|
|
compatible = "qcom,ravelin-mmss_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
pcie_anoc: interconnect@16C0000 {
|
|
reg = <0x16C0000 0x7080>;
|
|
compatible = "qcom,ravelin-pcie_anoc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
system_noc: interconnect@1680000 {
|
|
reg = <0x1680000 0x19080>;
|
|
compatible = "qcom,ravelin-system_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
video_aggre_noc: interconnect@1760000 {
|
|
reg = <0x1760000 0x1100>;
|
|
compatible = "qcom,ravelin-video_aggre_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
};
|
|
|
|
#include "ravelin-pinctrl.dtsi"
|
|
#include "diwali-gdsc.dtsi"
|
|
#include "ipcc-test-ravelin.dtsi"
|
|
#include "ravelin-qupv3.dtsi"
|
|
|
|
&qupv3_se2_2uart {
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_0_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_ufs_phy_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb30_prim_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_vcodec0_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_venus_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_camss_top_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&disp_cc_mdss_core_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&disp_cc_mdss_core_int2_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cc_cx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cc_gx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
sw-reset = <&gpu_cc_gx_sw_reset>;
|
|
status = "ok";
|
|
};
|