mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
ac8b6dfbf2
Using wrong phandle for PCIe root complex pcie_pipe_clk_ext_src. Therefore, update to use the correct phandle on sdxlemur. Change-Id: I9cb3a9b362dd72a1d08be7e6de4c6db7d4d86a17
118 lines
3.4 KiB
Plaintext
118 lines
3.4 KiB
Plaintext
&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x1c00000 0x3000>,
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<0x1c06000 0x2000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 57 0>;
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wake-gpio = <&tlmm 53 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_clkreq_sleep
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&pcie0_perst_default
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&pcie0_wake_default>;
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gdsc-vdd-supply = <&gcc_pcie_gdsc>;
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vreg-1.8-supply = <&pmx65_l1>;
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vreg-0.9-supply = <&pmx65_l4>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1.8-voltage-level = <1200000 1200000 30000>;
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qcom,vreg-0.9-voltage-level = <912000 912000 132000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
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qcom,bw-scale =
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<RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen1 */
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RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS 100000000>; /* Gen4 */
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interconnect-names = "icc_path";
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interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
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<&gcc GCC_PCIE_PIPE_CLK_SRC>,
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<&pcie_pipe_clk>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_0_sleep_clk", "pcie_phy_refgen_clk",
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"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
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max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>,
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<0>;
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resets = <&gcc GCC_PCIE_BCR>,
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<&gcc GCC_PCIE_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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qcom,smmu-sid-base = <0x0200>;
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iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
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<0x100 &apps_smmu 0x0201 0x1>;
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qcom,boot-option = <0x1>;
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qcom,use-19p2mhz-aux-clk;
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qcom,slv-addr-space-size = <0x40000000>;
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qcom,ep-latency = <10>;
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qcom,pcie-phy-ver = <0>;
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qcom,phy-status-offset = <0x1214>;
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qcom,phy-status-bit = <7>;
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qcom,phy-power-down-offset = <0x1240>;
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@a0000000 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0xa0000000 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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qcom,snps;
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};
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};
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