mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
72811cba6f
QUP core clock is shared among all the SE drivers, during earlybootup if any SE driver turn off the clock before real console gets probed, then the device will crash because of unclocked access by earlycon. In order to fix this move the console device definition up in DT file this ensures that console probe is called before other SE drivers. Change-Id: Ida298693b4383ba02475b89eb7891ed4aa6f02e1
751 lines
22 KiB
Plaintext
751 lines
22 KiB
Plaintext
#include <dt-bindings/interconnect/qcom,shima.h>
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&soc {
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/* QUPv3 SE Instances
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* Qup1 0: SE 0
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* Qup1 1: SE 1
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* Qup1 2: SE 2
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* Qup1 3: SE 3
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* Qup1 4: SE 4
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* Qup1 5: SE 5
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* Qup1 6: SE 6
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* Qup1 7: SE 7
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* Qup0 0: SE 8
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* Qup0 1: SE 9
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* Qup0 2: SE 10
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* Qup0 3: SE 11
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* Qup0 4: SE 12
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* Qup0 5: SE 13
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* Qup0 6: SE 14
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* Qup0 7: SE 15
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*/
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x9c0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
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<MASTER_QUP_0 SLAVE_EBI1>;
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iommus = <&apps_smmu 0x4c3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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};
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/* GPI Instance */
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gpi_dma0: qcom,gpi-dma@900000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x900000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x4d6 0x0>;
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qcom,max-num-gpii = <12>;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0xff>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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qcom,gpi-ee-offset = <0x10000>;
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status = "ok";
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};
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/* Debug UART Instance */
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qupv3_se13_2uart: qcom,qup_uart@994000 {
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compatible = "qcom,msm-geni-console";
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reg = <0x994000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se13_2uart_active>;
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pinctrl-1 = <&qupv3_se13_2uart_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "ok";
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};
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qupv3_se8_i2c: i2c@980000 {
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compatible = "qcom,i2c-geni";
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reg = <0x980000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se8_i2c_active>;
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pinctrl-1 = <&qupv3_se8_i2c_sleep>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se8_spi: spi@980000 {
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compatible = "qcom,spi-geni";
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reg = <0x980000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se8_spi_active>;
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pinctrl-1 = <&qupv3_se8_spi_sleep>;
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dmas = <&gpi_dma0 0 0 1 64 0>,
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<&gpi_dma0 1 0 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se9_i2c: i2c@984000 {
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compatible = "qcom,i2c-geni";
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reg = <0x984000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se9_i2c_active>;
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pinctrl-1 = <&qupv3_se9_i2c_sleep>;
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dmas = <&gpi_dma0 0 1 3 64 0>,
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<&gpi_dma0 1 1 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se9_spi: spi@984000 {
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compatible = "qcom,spi-geni";
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reg = <0x984000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se9_spi_active>;
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pinctrl-1 = <&qupv3_se9_spi_sleep>;
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dmas = <&gpi_dma0 0 1 1 64 0>,
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<&gpi_dma0 1 1 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se10_i2c: i2c@988000 {
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compatible = "qcom,i2c-geni";
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reg = <0x988000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se10_i2c_active>;
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pinctrl-1 = <&qupv3_se10_i2c_sleep>;
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dmas = <&gpi_dma0 0 2 3 64 0>,
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<&gpi_dma0 1 2 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se10_spi: spi@988000 {
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compatible = "qcom,spi-geni";
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reg = <0x988000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se10_spi_active>;
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pinctrl-1 = <&qupv3_se10_spi_sleep>;
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dmas = <&gpi_dma0 0 2 1 64 0>,
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<&gpi_dma0 1 2 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se11_i2c: i2c@98c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x98c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se11_i2c_active>;
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pinctrl-1 = <&qupv3_se11_i2c_sleep>;
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dmas = <&gpi_dma0 0 3 3 64 0>,
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<&gpi_dma0 1 3 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se11_spi: spi@98c000 {
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compatible = "qcom,spi-geni";
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reg = <0x98c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se11_spi_active>;
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pinctrl-1 = <&qupv3_se11_spi_sleep>;
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dmas = <&gpi_dma0 0 3 1 64 0>,
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<&gpi_dma0 1 3 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se12_i2c: i2c@990000 {
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compatible = "qcom,i2c-geni";
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reg = <0x990000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se12_i2c_active>;
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pinctrl-1 = <&qupv3_se12_i2c_sleep>;
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dmas = <&gpi_dma0 0 4 3 64 0>,
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<&gpi_dma0 1 4 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se12_spi: spi@990000 {
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compatible = "qcom,spi-geni";
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reg = <0x990000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se12_spi_active>;
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pinctrl-1 = <&qupv3_se12_spi_sleep>;
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dmas = <&gpi_dma0 0 4 1 64 0>,
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<&gpi_dma0 1 4 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se14_i2c: i2c@998000 {
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compatible = "qcom,i2c-geni";
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reg = <0x998000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se14_i2c_active>;
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pinctrl-1 = <&qupv3_se14_i2c_sleep>;
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dmas = <&gpi_dma0 0 6 3 64 0>,
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<&gpi_dma0 1 6 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se14_spi: spi@998000 {
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compatible = "qcom,spi-geni";
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reg = <0x998000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se14_spi_active>;
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pinctrl-1 = <&qupv3_se14_spi_sleep>;
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dmas = <&gpi_dma0 0 6 1 64 0>,
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<&gpi_dma0 1 6 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* HS UART Instance */
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qupv3_se15_4uart: qcom,qup_uart@99c000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x99c000 0x4000>;
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reg-names = "se_phys";
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interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 71 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "active", "sleep";
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pinctrl-0 = <&qupv3_se15_default_cts>,
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<&qupv3_se15_default_rtsrx>, <&qupv3_se15_default_tx>;
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pinctrl-1 = <&qupv3_se15_ctsrx>, <&qupv3_se15_rts>,
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<&qupv3_se15_tx>;
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pinctrl-2 = <&qupv3_se15_ctsrx>, <&qupv3_se15_rts>,
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<&qupv3_se15_tx>;
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qcom,wakeup-byte = <0xFD>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* QUPv3_1 wrapper instance */
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qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0xac0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MASTER_QUP_CORE_1 SLAVE_QUP_CORE_1>,
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<MASTER_QUP_1 SLAVE_EBI1>;
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iommus = <&apps_smmu 0x43 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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};
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/* GPI Instance */
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gpi_dma1: qcom,gpi-dma@a00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0xa00000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x56 0x0>;
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qcom,max-num-gpii = <12>;
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interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,gpii-mask = <0xff>;
|
|
qcom,ev-factor = <2>;
|
|
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
|
|
qcom,gpi-ee-offset = <0x10000>;
|
|
status = "ok";
|
|
};
|
|
|
|
qupv3_se0_i2c: i2c@a80000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa80000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se0_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
|
|
dmas = <&gpi_dma1 0 0 3 64 0>,
|
|
<&gpi_dma1 1 0 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se0_spi: spi@a80000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa80000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se0_spi_active>;
|
|
pinctrl-1 = <&qupv3_se0_spi_sleep>;
|
|
dmas = <&gpi_dma1 0 0 1 64 0>,
|
|
<&gpi_dma1 1 0 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se1_i2c: i2c@a84000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa84000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se1_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
|
|
dmas = <&gpi_dma1 0 1 3 64 0>,
|
|
<&gpi_dma1 1 1 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se1_spi: spi@a84000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa84000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se1_spi_active>;
|
|
pinctrl-1 = <&qupv3_se1_spi_sleep>;
|
|
dmas = <&gpi_dma1 0 1 1 64 0>,
|
|
<&gpi_dma1 1 1 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se2_i2c: i2c@a88000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa88000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se2_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
|
|
dmas = <&gpi_dma1 0 2 3 64 0>,
|
|
<&gpi_dma1 1 2 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se2_spi: spi@a88000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa88000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se2_spi_active>;
|
|
pinctrl-1 = <&qupv3_se2_spi_sleep>;
|
|
dmas = <&gpi_dma1 0 2 1 64 0>,
|
|
<&gpi_dma1 1 2 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se3_i2c: i2c@a8c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se3_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
|
|
dmas = <&gpi_dma1 0 3 3 64 0>,
|
|
<&gpi_dma1 1 3 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se3_spi: spi@a8c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se3_spi_active>;
|
|
pinctrl-1 = <&qupv3_se3_spi_sleep>;
|
|
dmas = <&gpi_dma1 0 3 1 64 0>,
|
|
<&gpi_dma1 1 3 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se4_i2c: i2c@a90000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa90000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se4_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
|
|
dmas = <&gpi_dma1 0 4 3 64 0>,
|
|
<&gpi_dma1 1 4 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se4_spi: spi@a90000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa90000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se4_spi_active>;
|
|
pinctrl-1 = <&qupv3_se4_spi_sleep>;
|
|
dmas = <&gpi_dma1 0 4 1 64 0>,
|
|
<&gpi_dma1 1 4 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se5_i2c: i2c@a94000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa94000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se5_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
|
|
dmas = <&gpi_dma1 0 5 3 64 0>,
|
|
<&gpi_dma1 1 5 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
qcom,shared;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se5_spi: spi@a94000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa94000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se5_spi_active>;
|
|
pinctrl-1 = <&qupv3_se5_spi_sleep>;
|
|
dmas = <&gpi_dma1 0 5 1 64 0>,
|
|
<&gpi_dma1 1 5 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* Travel adapter over 2-wire HSUART, no wakeup */
|
|
qupv3_se6_2uart: qcom,qup_uart@a98000 {
|
|
compatible = "qcom,msm-geni-serial-hs";
|
|
reg = <0xa98000 0x4000>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "active", "sleep";
|
|
pinctrl-0 = <&qupv3_se6_default_txrx>;
|
|
pinctrl-1 = <&qupv3_se6_2uart_active>;
|
|
pinctrl-2 = <&qupv3_se6_2uart_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se6_i2c: i2c@a98000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa98000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se6_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
|
|
dmas = <&gpi_dma1 0 6 3 64 0>,
|
|
<&gpi_dma1 1 6 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se6_spi: spi@a98000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa98000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se6_spi_active>;
|
|
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
|
dmas = <&gpi_dma1 0 6 1 64 0>,
|
|
<&gpi_dma1 1 6 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se7_i2c: i2c@a9c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa9c000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se7_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
|
|
dmas = <&gpi_dma1 0 7 3 64 0>,
|
|
<&gpi_dma1 1 7 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se7_spi: spi@a9c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa9c000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se7_spi_active>;
|
|
pinctrl-1 = <&qupv3_se7_spi_sleep>;
|
|
dmas = <&gpi_dma1 0 7 1 64 0>,
|
|
<&gpi_dma1 1 7 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|