mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
82fe61de79
Add 'dma-coherent-hint-cached' property to vidc context banks in order to skip explicit cache operations from vidc driver. Change-Id: I2b95b803d00f7ead89435b7760b6e01e136214e6
100 lines
3.0 KiB
Plaintext
100 lines
3.0 KiB
Plaintext
&soc {
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msm_vidc: qcom,vidc {
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compatible = "qcom,msm-vidc", "qcom,shima-vidc";
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status = "okay";
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reg = <0x0aa00000 0x00100000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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/* IOMMU Config */
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#address-cells = <1>;
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#size-cells = <1>;
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/* Supply */
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iris-ctl-supply = <&video_cc_mvs0c_gdsc>;
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vcodec-supply = <&video_cc_mvs0_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0", "gcc_video_throttle",
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"core_clk", "vcodec_clk";
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clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
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<&gcc GCC_VIDEO_MVP_THROTTLE_CORE_CLK>,
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<&videocc VIDEO_CC_MVS0C_CLK>,
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<&videocc VIDEO_CC_MVS0_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_throttle",
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"core_clk", "vcodec_clk";
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/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
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qcom,clock-configs = <0x0 0x0 0x1 0x1>;
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qcom,allowed-clock-rates = <240000000 338000000
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364800000>;
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resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
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reset-names = "video_axi_reset";
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qcom,reg-presets = <0xB0088 0x0 0x11>;
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/* Video Firmware ELF image name */
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vidc,firmware-name = "vpu20_2v";
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/* Bus Interconnects */
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interconnect-names = "venus-cnoc", "venus-ddr";
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_VENUS_CFG>,
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<&mmss_noc MASTER_VIDEO_P0
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&mc_virt SLAVE_EBI1>;
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/* Bus BW range (low, high) for each bus */
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qcom,bus-range-kbps = <1000 1000
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1000 15000000>;
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_ns";
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iommus = <&apps_smmu 0x2900 0x0400>;
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qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x25800000 0xba800000>;
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dma-coherent-hint-cached;
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};
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secure_non_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_non_pixel";
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iommus = <&apps_smmu 0x2904 0x0400>;
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qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */
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buffer-types = <0x480>;
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virtual-addr-pool = <0x01000000 0x24800000>;
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qcom,secure-context-bank;
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};
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secure_bitstream_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_bitstream";
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iommus = <&apps_smmu 0x2901 0x0404>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
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buffer-types = <0x241>;
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virtual-addr-pool = <0x00500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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secure_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_pixel";
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iommus = <&apps_smmu 0x2903 0x0400>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
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buffer-types = <0x106>;
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virtual-addr-pool = <0x00500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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};
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};
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