mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
719cc9aa79
Add devicetree bindings snapshot to the devicetree project Change-Id: I20b46d194bd3b107ddcb3e35283e6dafa27adec1
25 lines
660 B
Plaintext
25 lines
660 B
Plaintext
NVIDIA Tegra20 timer
|
|
|
|
The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
|
|
running counter. The first two channels may also trigger a watchdog reset.
|
|
|
|
Required properties:
|
|
|
|
- compatible : should be "nvidia,tegra20-timer".
|
|
- reg : Specifies base physical address and size of the registers.
|
|
- interrupts : A list of 4 interrupts; one per timer channel.
|
|
- clocks : Must contain one entry, for the module clock.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
|
|
Example:
|
|
|
|
timer {
|
|
compatible = "nvidia,tegra20-timer";
|
|
reg = <0x60005000 0x60>;
|
|
interrupts = <0 0 0x04
|
|
0 1 0x04
|
|
0 41 0x04
|
|
0 42 0x04>;
|
|
clocks = <&tegra_car 132>;
|
|
};
|