mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
b0e5152a74
Add devicetree bindings snapshot to the devicetree project.
This snapshot is taken as of the
'commit 5fba1b18cfc72e264e5f3ce49020ed322aa6ac9f ("Merge 5.6-rc3
into android-mainline")' of the kernel project.
Change-Id: Ia087ab2b7d4a2616ea446a69683a8b5b821d0448
87 lines
2.8 KiB
Plaintext
87 lines
2.8 KiB
Plaintext
* Samsung Exynos4 Clock Controller
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The Exynos4 clock controller generates and supplies clock to various controllers
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within the Exynos4 SoC. The clock binding described here is applicable to all
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SoC's in the Exynos4 family.
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Required Properties:
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- compatible: should be one of the following.
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- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
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- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos4.h header and can be used in device
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tree sources.
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Example 1: An example of a clock controller node is listed below.
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clock: clock-controller@10030000 {
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compatible = "samsung,exynos4210-clock";
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reg = <0x10030000 0x20000>;
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#clock-cells = <1>;
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};
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Example 2: UART controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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serial@13820000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13820000 0x100>;
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interrupts = <0 54 0>;
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clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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};
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Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
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subsystem. Registers for those clocks are located in the ISP power domain.
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Because those registers are also located in a different memory region than
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the main clock controller, a separate clock controller has to be defined for
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handling them.
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Required Properties:
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- compatible: should be "samsung,exynos4412-isp-clock".
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- reg: physical base address of the ISP clock controller and length of memory
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mapped region.
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- #clock-cells: should be 1.
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- clocks: list of the clock controller input clock identifiers,
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from common clock bindings, should point to CLK_ACLK200 and
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CLK_ACLK400_MCUISP clocks from the main clock controller.
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- clock-names: list of the clock controller input clock names,
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as described in clock-bindings.txt, should be "aclk200" and
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"aclk400_mcuisp".
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- power-domains: a phandle to ISP power domain node as described by
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generic PM domain bindings.
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Example 3: The clock controllers bindings for Exynos4412 SoCs.
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clock: clock-controller@10030000 {
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compatible = "samsung,exynos4412-clock";
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reg = <0x10030000 0x18000>;
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#clock-cells = <1>;
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};
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isp_clock: clock-controller@10048000 {
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compatible = "samsung,exynos4412-isp-clock";
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reg = <0x10048000 0x1000>;
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#clock-cells = <1>;
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power-domains = <&pd_isp>;
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clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
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clock-names = "aclk200", "aclk400_mcuisp";
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};
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