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https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
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d67fba66f8
Update the devfreq_icc documentation to add support for L3 BW voting devices which require an additional bus width property to be defined. Change-Id: Iec16c5f666b2643971d45cb48c97015407372853
90 lines
3.0 KiB
Plaintext
90 lines
3.0 KiB
Plaintext
MSM devfreq icc device
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devfreq icc is a device that represents a MSM device's BW requirements from its
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master port(s) to a different device's slave port(s) in a MSM SoC. This
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device is typically used to vote for BW requirements from a device's (Eg:
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CPU, GPU) master port(s) to the slave (Eg: DDR) port(s).
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Required properties:
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- compatible: Must be "qcom,devfreq-icc" or "qcom,devfreq-icc-ddr"
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or "qcom,devfreq-icc-llcc" or "qcom,devfreq-icc-l3"
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or "qcom,devfreq-icc-l3bw"
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- interconnects: Pairs of phandles and interconnect provider specificers
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to denote the edge source and destination ports of the
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desired interconnect path.
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- operating-points-v2: A phandle to the OPP v2 table that holds meaningful
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instantaneous bandwidth values (in MB/s) that can be
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requested from the device master port to the slave port.
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The list of values depend on the supported bus/slave
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frequencies and the bus width. Required for all devices
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except those compatible with "qcom,devfreq-icc-l3" or
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"qcom,devfreq-icc-l3bw".
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- reg: Physical base address and region size of the memory
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mapped registers containing the device's frequency
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table. Required for "qcom,devfreq-icc-l3" and
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"qcom,devfreq-icc-l3bw" devices.
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- reg-names: Name used for the above registers. Expected name is
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"ftbl-base". Required for "qcom,devfreq-icc-l3"
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and "qcom,devfreq-icc-l3bw" devices.
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- qcom,bus-width: Bus width of the interconnect path. Only required for
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"qcom,devfreq-icc-l3bw" devices.
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Optional properties:
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- qcom,active-only: Indicates that the bandwidth votes need to be
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enforced only when the CPU subsystem is active.
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- governor: Initial governor to use for the device.
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Default: "performance"
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- opp-supported-hw: For the devices that are compatible with "qcom,devfreq-icc-ddr",
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the OPP node can have opp-supported-hw property. This is a
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single 32 bit bitmap value, representing compatible DDR-Type in HW.
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Example:
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Value:
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0x80: Frequency Compatible for LPDDR4X only
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0x100: Frequency Compatible for LPDDR5 only
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0x180: Frequency Compatible for both LPDDR4X and LPDDR5
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Example:
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bw_opp_table: bw-opp-table {
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compatible = "operating-points-v2";
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opp-75 {
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opp-hz = /bits/ 64 < 572 >; /* 75 MHz */
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opp-supported-hw = <0x80>;
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};
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opp-150 {
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opp-hz = /bits/ 64 < 1144 >; /* 150 MHz */
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opp-supported-hw = <0x80>;
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};
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opp-200 {
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opp-hz = /bits/ 64 < 1525 >; /* 200 MHz */
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opp-supported-hw = <0x180>;
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};
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opp-307 {
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opp-hz = /bits/ 64 < 2342 >; /* 307 MHz */
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opp-supported-hw = <0x80>;
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};
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opp-460 {
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opp-hz = /bits/ 64 < 3509 >; /* 460 MHz */
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opp-supported-hw = <0x80>;
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};
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opp-614 {
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opp-hz = /bits/ 64 < 4684 >; /* 614 MHz */
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opp-supported-hw = <0x80>;
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};
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opp-800 {
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opp-hz = /bits/ 64 < 6103 >; /* 800 MHz */
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opp-supported-hw = <0x80>;
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};
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opp-931 {
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opp-hz = /bits/ 64 < 7102 >; /* 931 MHz */
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opp-supported-hw = <0x80>;
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};
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};
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qcom,cpubw {
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compatible = "qcom,devfreq-icc-ddr";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&bw_opp_table>;
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};
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