mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
b0e5152a74
Add devicetree bindings snapshot to the devicetree project.
This snapshot is taken as of the
'commit 5fba1b18cfc72e264e5f3ce49020ed322aa6ac9f ("Merge 5.6-rc3
into android-mainline")' of the kernel project.
Change-Id: Ia087ab2b7d4a2616ea446a69683a8b5b821d0448
60 lines
1.6 KiB
Plaintext
60 lines
1.6 KiB
Plaintext
* Microsemi MIPS CPUs
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Boards with a SoC of the Microsemi MIPS family shall have the following
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properties:
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Required properties:
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- compatible: "mscc,ocelot"
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* Other peripherals:
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o CPU chip regs:
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The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
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functionalities: chip ID, general purpose register for software use, reset
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controller, hardware status and configuration, efuses.
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Required properties:
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- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
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- reg : Should contain registers location and length
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Example:
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syscon@71070000 {
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compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
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reg = <0x71070000 0x1c>;
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};
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o CPU system control:
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The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
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the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
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endianness, CPU bus control, CPU status.
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Required properties:
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- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
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- reg : Should contain registers location and length
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Example:
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syscon@70000000 {
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compatible = "mscc,ocelot-cpu-syscon", "syscon";
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reg = <0x70000000 0x2c>;
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};
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o HSIO regs:
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The SoC has a few registers (HSIO) handling miscellaneous functionalities:
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configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
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status, SerDes muxing and a thermal sensor.
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Required properties:
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- compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
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- reg : Should contain registers location and length
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Example:
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syscon@10d0000 {
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compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
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reg = <0x10d0000 0x10000>;
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};
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