mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
b0e5152a74
Add devicetree bindings snapshot to the devicetree project.
This snapshot is taken as of the
'commit 5fba1b18cfc72e264e5f3ce49020ed322aa6ac9f ("Merge 5.6-rc3
into android-mainline")' of the kernel project.
Change-Id: Ia087ab2b7d4a2616ea446a69683a8b5b821d0448
37 lines
1.4 KiB
Plaintext
37 lines
1.4 KiB
Plaintext
NVIDIA Tegra210 timer
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The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
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timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
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from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
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(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
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or watchdog interrupts.
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Required properties:
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- compatible : "nvidia,tegra210-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 14 interrupts; one per each timer channels 0 through
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13.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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timer@60005000 {
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compatible = "nvidia,tegra210-timer";
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reg = <0x0 0x60005000 0x0 0x400>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_TIMER>;
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clock-names = "timer";
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};
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