mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 04:59:05 +00:00
7a4ab80643
Add CNSS2 device tree entry for WLAN KIWI device parameters. Change-Id: Ic2464917d2017e0d26e04745c7398610c5f108cd
140 lines
3.4 KiB
Plaintext
140 lines
3.4 KiB
Plaintext
#include <dt-bindings/interconnect/qcom,waipio.h>
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&wlan {
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status = "disabled";
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};
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&cnss_pins {
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cnss_host_sol_default: cnss_host_sol_default {
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mux {
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pins = "gpio48";
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function = "gpio";
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};
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config {
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pins = "gpio48";
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drive-strength = <4>;
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bias-pull-down;
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};
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};
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cnss_dev_sol_default: cnss_dev_sol_default {
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mux {
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pins = "gpio50";
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function = "gpio";
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};
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config {
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pins = "gpio50";
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drive-strength = <4>;
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bias-pull-down;
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};
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};
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};
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&soc {
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wlan_wcn7850: qcom,cnss-wcn7850@b0000000 {
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compatible = "qcom,cnss-wcn7850";
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reg = <0xb0000000 0x10000>;
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reg-names = "smmu_iova_ipa";
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wlan-en-gpio = <&tlmm 80 0>;
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wlan-host-sol-gpio = <&tlmm 48 0>;
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wlan-dev-sol-gpio = <&tlmm 50 0>;
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pinctrl-names = "wlan_en_active", "wlan_en_sleep",
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"sol_default";
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pinctrl-0 = <&cnss_wlan_en_active>;
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pinctrl-1 = <&cnss_wlan_en_sleep>;
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pinctrl-2 = <&cnss_host_sol_default &cnss_dev_sol_default>;
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qcom,wlan;
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qcom,wlan-rc-num = <1>;
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qcom,wlan-ramdump-dynamic = <0x780000>;
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use-pm-domain;
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qcom,same-dt-multi-dev;
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mboxes = <&qmp_aop 0>;
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vdd-wlan-io-supply = <&S10B>;
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qcom,vdd-wlan-io-config = <1800000 1800000 0 0 0>;
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vdd-wlan-supply = <&S3E>;
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qcom,vdd-wlan-config = <1000000 1000000 0 0 0>;
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vdd-wlan-aon-supply = <&S2E>;
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qcom,vdd-wlan-aon-config = <980000 1040000 0 0 0>;
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vdd-wlan-dig-supply = <&S11B>;
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qcom,vdd-wlan-dig-config = <950000 1170000 0 0 0>;
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vdd-wlan-rfa1-supply = <&S1C>;
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qcom,vdd-wlan-rfa1-config = <1900000 2024000 0 0 0>;
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vdd-wlan-rfa2-supply = <&S12B>;
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qcom,vdd-wlan-rfa2-config = <1350000 2040000 0 0 0>;
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interconnects =
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<&pcie_noc MASTER_PCIE_1 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
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<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
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interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
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qcom,icc-path-count = <2>;
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qcom,bus-bw-cfg-count = <9>;
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qcom,bus-bw-cfg =
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/** ICC Path 1 **/
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<0 0>, /* no vote */
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/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
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<2250 1600000>,
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/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
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<7500 1600000>,
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/* medium: 60-240 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
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<30000 1600000>,
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/* high: 240-1080 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
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<100000 6448000>,
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/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 1555 MHz */
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<175000 6448000>,
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/* ultra high: DBS mode snoc/anoc: 403 Mhz ddr: 2092 MHz */
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<175000 6448000>,
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/* super high: DBS mode snoc/anoc: 533 Mhz ddr: 3.2GHz */
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<175000 8528000>,
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/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
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* ddr: 547.2 MHz
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*/
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<7500 3200000>,
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/** ICC Path 2 **/
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<0 0>,
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/* ddr: 451.2 MHz */
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<2250 1804800>,
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/* ddr: 451.2 MHz */
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<7500 1804800>,
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/* ddr: 451.2 MHz */
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<30000 1804800>,
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/* ddr: 451.2 MHz */
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<100000 1804800>,
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/* ddr: 1555 MHz */
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<175000 6220800>,
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/* ddr: 2092 MHz */
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<175000 8368000>,
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/* ddr: 3.2 GHz */
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<175000 12800000>,
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/* ddr: 547.2 MHz */
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<7500 2188800>;
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};
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};
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&pcie1_rp {
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#address-cells = <5>;
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#size-cells = <0>;
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cnss_pci1: cnss_pci1 {
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reg = <0 0 0 0 0>;
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qcom,iommu-group = <&cnss_pci_iommu_group1>;
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memory-region = <&cnss_wlan_mem>;
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#address-cells = <1>;
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#size-cells = <1>;
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cnss_pci_iommu_group1: cnss_pci_iommu_group1 {
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qcom,iommu-msi-size = <0x1000>;
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qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-pagetable = "coherent";
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qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
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"non-fatal";
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};
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};
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};
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