mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 04:59:05 +00:00
6afacf98eb
Add USB GDSC supplies which will get enabled prior to turning on the USB clocks. Change-Id: I0d30d386c3b576af08a0ac458edd3db3e9cc4625
94 lines
2.4 KiB
Plaintext
94 lines
2.4 KiB
Plaintext
&soc {
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usb0: ssusb@a6f8800 {
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compatible = "qcom,dwc3";
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reg = <0xa6f8800 0x400>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x0 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma-ranges;
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk";
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resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0xa600000 0xcd00>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,ssp-u3-u0-quirk;
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snps,usb3-u1u2-disable;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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usb-core-id = <0>;
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tx-fifo-resize;
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maximum-speed = "super-speed-plus";
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dr_mode = "drd";
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};
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};
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usb1: ssusb@a8f8800 {
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compatible = "qcom,dwc3";
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reg = <0xa8f8800 0x400>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x20 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma-ranges;
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USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>;
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clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>,
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<&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
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<&clock_gcc GCC_USB30_SEC_SLEEP_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk";
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resets = <&clock_gcc GCC_USB30_SEC_BCR>;
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reset-names = "core_reset";
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dwc3@a800000 {
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compatible = "snps,dwc3";
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reg = <0xa800000 0xcd00>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,ssp-u3-u0-quirk;
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snps,usb3-u1u2-disable;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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usb-core-id = <0>;
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tx-fifo-resize;
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maximum-speed = "super-speed-plus";
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dr_mode = "drd";
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};
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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};
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