mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 04:59:05 +00:00
9f853f5b6d
Add PDC irq chip, apps_rsc and disp_rsc devices to enable RPMH communication. Change-Id: I1d36d5b0ab0ce643b7946e85da0be113fc5f290a
891 lines
19 KiB
Plaintext
891 lines
19 KiB
Plaintext
#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,parrot.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,camcc-parrot.h>
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#include <dt-bindings/clock/qcom,dispcc-parrot.h>
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#include <dt-bindings/clock/qcom,gcc-parrot.h>
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#include <dt-bindings/clock/qcom,gpucc-parrot.h>
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#include <dt-bindings/clock/qcom,videocc-parrot.h>
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/ {
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model = "Qualcomm Technologies, Inc. Parrot";
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compatible = "qcom,parrot";
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qcom,msm-id = <537 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen: chosen { };
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_memory: reserved-memory { };
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aliases {
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mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
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mmc1 = &sdhc_2; /* SDC2 SD card slot */
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};
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firmware: firmware {};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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soc: soc { };
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};
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&firmware {
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android {
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compatible = "android,firmware";
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fstab {
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compatible = "android,fstab";
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vendor {
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compatible = "android,vendor";
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dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
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type = "ext4";
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mnt_flags = "ro,barrier=1,discard";
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fsmgr_flags = "wait,slotselect";
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status = "ok";
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};
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};
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};
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};
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#include "parrot-stub-regulator.dtsi"
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#include "parrot-usb.dtsi"
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#include "parrot-reserved-memory.dtsi"
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* global autoconfigured region for contiguous allocations */
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system_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17200000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17200000 0x10000>, /* GICD */
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<0x17260000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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wdog: qcom,wdt@17410000 {
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compatible = "qcom,msm-watchdog";
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reg = <0x17410000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <9360>;
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qcom,ipi-ping;
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qcom,wakeup-enable;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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apps_rsc: rsc@17a00000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x17a00000 0x10000>,
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<0x17a10000 0x10000>,
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<0x17a20000 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 3>,
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<SLEEP_TCS 2>,
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<WAKE_TCS 2>,
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<CONTROL_TCS 0>, /* PDC wakeup values will be written from TZ */
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<FAST_PATH_TCS 1>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,pdc";
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reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
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reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg";
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qcom,pdc-ranges = <0 480 94>, <94 609 31>,
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<125 63 1>, <126 716 12>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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disp_rsc: rsc@af20000 {
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label = "disp_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0xaf20000 0x10000>;
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reg-names = "drv-0";
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
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qcom,tcs-offset = <0x1c00>;
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qcom,drv-id = <0>;
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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memtimer: timer@17420000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17420000 0x1000>;
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clock-frequency = <19200000>;
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frame@17421000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17421000 0x1000>,
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<0x17422000 0x1000>;
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};
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frame@17423000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17423000 0x1000>;
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status = "disabled";
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};
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frame@17425000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17425000 0x1000>;
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status = "disabled";
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};
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frame@17427000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17427000 0x1000>;
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status = "disabled";
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};
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frame@17429000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17429000 0x1000>;
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status = "disabled";
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};
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frame@1742b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742b000 0x1000>;
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status = "disabled";
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};
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frame@1742d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742d000 0x1000>;
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status = "disabled";
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};
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};
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ipcc_mproc: qcom,ipcc@ed18000 {
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compatible = "qcom,ipcc";
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reg = <0xed18000 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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tcsr_mutex_block: syscon@1f40000 {
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compatible = "syscon";
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reg = <0x1f40000 0x20000>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_block 0 0x1000>;
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#hwlock-cells = <1>;
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};
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smem: qcom,smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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qcom,smp2p-modem {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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modem_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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modem_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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adsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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adsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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sleepstate_smp2p_out: sleepstate-out {
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qcom,entry-name = "sleepstate";
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#qcom,smem-state-cells = <1>;
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};
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sleepstate_smp2p_in: qcom,sleepstate-in {
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qcom,entry-name = "sleepstate_see";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p_sleepstate {
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compatible = "qcom,smp2p-sleepstate";
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qcom,smem-states = <&sleepstate_smp2p_out 0>;
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interrupt-parent = <&sleepstate_smp2p_in>;
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interrupts = <0 0>;
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interrupt-names = "smp2p-sleepstate-in";
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};
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qcom,smp2p-cdsp {
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compatible = "qcom,smp2p";
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qcom,smem = <94>, <432>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <5>;
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cdsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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cdsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-wpss {
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compatible = "qcom,smp2p";
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qcom,smem = <617>, <616>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <13>;
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wpss_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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wpss_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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aoss_qmp: power-controller@c300000 {
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|
compatible = "qcom,diwali-aoss-qmp";
|
|
reg = <0xc300000 0x400>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
#power-domain-cells = <1>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,qmp = <&aoss_qmp>;
|
|
label = "aop";
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qmp_tme: qcom,qmp-tme {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,remote-pid = <14>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_TME
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "tme_qmp";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_TME
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "tme";
|
|
qcom,early-boot;
|
|
priority = <0>;
|
|
mbox-desc-offset = <0x0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo-board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <38400000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_0_pipe_clk: pcie_0_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_1_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_tx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
bi_tcxo: bi_tcxo {
|
|
compatible = "fixed-factor-clock";
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
clocks = <&xo_board>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
bi_tcxo_ao: bi_tcxo_ao {
|
|
compatible = "fixed-factor-clock";
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
clocks = <&xo_board>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
rpmhcc: qcom,rpmhcc {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "rpmhcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ade0000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "camcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "dispcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gpucc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@1002000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "videocc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
sdhc_1: sdhci@7C4000 {
|
|
status = "disabled";
|
|
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>;
|
|
reg-names = "hc", "cqhci";
|
|
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
bus-width = <8>;
|
|
non-removable;
|
|
supports-cqe;
|
|
|
|
no-sd;
|
|
no-sdio;
|
|
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
mmc-hs400-enhanced-strobe;
|
|
|
|
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
|
<&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
|
|
clock-names = "iface", "core", "ice_core";
|
|
|
|
qcom,ice-clk-rates = <300000000 100000000>;
|
|
|
|
qos0 {
|
|
mask = <0xf0>;
|
|
vote = <44>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x0f>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
sdhc_2: sdhci@8804000 {
|
|
status = "disabled";
|
|
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x08804000 0x1000>;
|
|
reg-names = "hc";
|
|
|
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
bus-width = <4>;
|
|
no-sdio;
|
|
no-mmc;
|
|
qcom,restore-after-cx-collapse;
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
|
|
qos0 {
|
|
mask = <0xf0>;
|
|
vote = <44>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x0f>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x0 0x280000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x00000001>;
|
|
};
|
|
|
|
clk_virt: interconnect@0 {
|
|
compatible = "qcom,parrot-clk_virt";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
mc_virt: interconnect@1 {
|
|
compatible = "qcom,parrot-mc_virt";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
cnoc2: interconnect@1500000 {
|
|
compatible = "qcom,parrot-cnoc2";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
cnoc3: interconnect@1502000 {
|
|
compatible = "qcom,parrot-cnoc3";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
system_noc: interconnect@1680000 {
|
|
compatible = "qcom,parrot-system_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
pcie_noc: interconnect@16c0000 {
|
|
compatible = "qcom,parrot-pcie_anoc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
compatible = "qcom,parrot-aggre1_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
compatible = "qcom,parrot-aggre2_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1740000 {
|
|
compatible = "qcom,parrot-mmss_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
gem_noc: interconnect@19100000 {
|
|
compatible = "qcom,parrot-gem_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
nsp_noc: interconnect@320C0000 {
|
|
compatible = "qcom,parrot-nsp_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
lpass_ag_noc: interconnect@3c40000 {
|
|
compatible = "qcom,parrot-lpass_ag_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
qcom_tzlog: tz-log@146AA720 {
|
|
compatible = "qcom,tz-log";
|
|
reg = <0x146AA720 0x3000>;
|
|
qcom,hyplog-enabled;
|
|
hyplog-address-offset = <0x410>;
|
|
hyplog-size-offset = <0x414>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
#include "diwali-gdsc.dtsi"
|
|
|
|
&gcc_pcie_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
/delete-property/ qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_ufs_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb30_prim_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_camss_top_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&disp_cc_mdss_core_gdsc {
|
|
compatible = "regulator-fixed";
|
|
/delete-property/ qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&disp_cc_mdss_core_int2_gdsc {
|
|
compatible = "regulator-fixed";
|
|
/delete-property/ qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cc_cx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cc_gx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&video_cc_mvs0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
reg = <0xaaf6004 0x4>;
|
|
status = "ok";
|
|
/delete-property/ qcom,support-hw-trigger;
|
|
};
|
|
|
|
&video_cc_mvsc_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
#include "parrot-pinctrl.dtsi"
|
|
#include "parrot-dma-heaps.dtsi"
|