mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
caf4fb3839
Add QUPv3 common driver, I2C and GSI DT nodes in trustedvm dtsi. Change-Id: Ide390774db3b93ceaaa89661440cdf3bf5971939
154 lines
3.4 KiB
Plaintext
154 lines
3.4 KiB
Plaintext
#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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interrupt-parent = <&vgic>;
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chosen {
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bootargs = "root=/dev/ram rw init=/init console=hvc0 loglevel=8";
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linux,initrd-start = <0x2a900000>;
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linux,initrd-end = <0x2b100000>; /* 8 MB */
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kaslr-seed = <0xfeedbeef 0xc0def00d>;
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <0x2>;
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};
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};
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vgic: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
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<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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memory@28000000 {
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device_type = "memory";
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reg = <0x0 0x28000000 0x0 0x8000000>; /* Temp S2 mapping */
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};
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qcom,vm-config {
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compatible = "qcom,vm-1.0";
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vm-type = "aarch64-guest";
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boot-config = "fdt,unified";
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os-type = "linux";
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kernel-entry-segment = "kernel";
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kernel-entry-offset = <0x0 0x0>;
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vendor = "Qualcomm";
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image-name = "qcom,trustedvm";
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qcom,pasid = <0x0 0x1c>;
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memory {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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base-address = <0x0 0xD0800000>;
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size-min = <0x0 0x8000000>; /* 128 MB */
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};
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segments {
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/* offset and size */
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kernel = <0x0 0x8000 0x0 0x2000000>; /* 32 MB */
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dt = <0x0 0x7000000 0x0 0x4000>; /* 16 KB */
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};
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vcpus {
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config = "/cpus";
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affinity = "static";
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affinity-map = <0x0>; /* VCPU -> CPU */
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};
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interrupts {
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config = &vgic;
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};
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vdevices {
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peer-default;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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always-on;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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/*
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* QUPv3 Instances
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* North 4 : SE 4
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*/
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/* QUPv3_0 wrapper instance: North QUP */
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qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x9c0000 0x2000>;
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};
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/* GPI */
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gpi_dma0: qcom,gpi-dma@900000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x900000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <12>;
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qcom,gpii-mask = <0x80>;
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qcom,ev-factor = <2>;
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qcom,gpi-ee-offset = <0x10000>;
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status = "ok";
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};
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/* I2C SE */
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qupv3_se4_i2c: i2c@990000 {
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compatible = "qcom,i2c-geni";
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reg = <0x990000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma0 0 4 3 64 0>,
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<&gpi_dma0 1 4 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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qcom,le-vm;
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status = "ok";
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};
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};
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#include "trustedvm-ion.dtsi"
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