mirror of
https://github.com/Evolution-X-Devices/device_xiaomi_sdm710-common
synced 2026-02-01 04:20:55 +00:00
Revert "sdm710-common: Split RF configs from the main NFC config"
We are using AOSP stack so libnfc-nxp_RF.conf is inappropriate.
This reverts commit b5affc765c.
Signed-off-by: Ivan Vecera <ivan@cera.cz>
Change-Id: Id71571d1a2ab2fa9668b0c49773d02f1ee00a999
This commit is contained in:
Ivan Vecera
committed by
Sebastiano Barezzi
Sebastiano Barezzi
parent
782dfdd1a7
commit
48943bc614
@@ -118,6 +118,55 @@ NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, BA, 1E, 15,
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# DCDCWaitTime=4.2ms
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NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 40, 0A}
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NXP_RF_CONF_BLK_1={
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20, 02, E7, 1B,
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A0, 0D, 06, 06, 37, 08, 76, 00, 00,
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A0, 0D, 03, 24, 03, 7D,
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A0, 0D, 06, 02, 35, 00, 3E, 00, 00,
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A0, 0D, 06, 04, 35, F4, 05, 70, 02,
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A0, 0D, 06, C2, 35, 00, 3E, 00, 03,
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A0, 0D, 06, 04, 42, F8, 40, FF, FF,
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A0, 0D, 04, 32, 42, F8, 40,
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A0, 0D, 04, 46, 42, 68, 40,
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A0, 0D, 04, 56, 42, 78, 40,
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A0, 0D, 04, 5C, 42, 80, 40,
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A0, 0D, 04, CA, 42, 68, 40,
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A0, 0D, 06, 06, 42, 00, 02, F6, F6,
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A0, 0D, 06, 32, 4A, 53, 07, 00, 1B,
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A0, 0D, 06, 46, 4A, 33, 07, 00, 07,
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A0, 0D, 06, 56, 4A, 43, 07, 00, 07,
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A0, 0D, 06, 5C, 4A, 11, 07, 01, 07,
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A0, 0D, 06, 34, 44, 66, 08, 00, 00,
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A0, 0D, 06, 48, 44, 65, 0A, 00, 00,
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A0, 0D, 06, 58, 44, 55, 08, 00, 00,
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A0, 0D, 06, 5E, 44, 55, 08, 00, 00,
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A0, 0D, 06, CA, 44, 65, 0A, 00, 00,
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A0, 0D, 06, 06, 44, 04, 04, C4, 00,
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A0, 0D, 06, 34, 2D, DC, 20, 04, 00,
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A0, 0D, 06, 48, 2D, 15, 34, 1F, 01,
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A0, 0D, 06, 58, 2D, 0D, 48, 0C, 01,
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A0, 0D, 06, 5E, 2D, 0D, 5A, 0C, 01,
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A0, 0D, 06, CA, 2D, 15, 34, 1F, 01
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}
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# Enable DLMA
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NXP_RF_CONF_BLK_2={
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20, 02, D6, 01, A0, 34, D2, 23, 04, 18, 47, 40, 00, 00, 40, 01, 32, 00, 40, 01, 47, 00, 40, 01, 73, 00, 40, 01, A7, 00, 40, 01, F5, 00, 08, 01, 5C, 01, 48, 00, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 48, 01, 00, 00, 08, 03, 00, 00, 08, 01, 00, 00, C8, 02, 00, 00, C8, 00, 00, 00, 88, 02, 00, 00, 48, 02, 00, 00, B8, 00, 00, 00, 68, 00, 00, 00, 18, 00, 00, 00, 08, 02, 00, 00, 00, 00, 00, 00, 00, 00, 47, 00, 00, 40, 01, 32, 00, 40, 01, 47, 00, 40, 01, 73, 00, 40, 01, A7, 00, 40, 01, F5, 00, 08, 01, 5C, 01, 48, 00, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 48, 01, 00, 00, 08, 03, 00, 00, 08, 01, 00, 00, C8, 02, 00, 00, C8, 00, 00, 00, 88, 02, 00, 00, 48, 02, 00, 00, B8, 00, 00, 00, 68, 00, 00, 00, 18, 00, 00, 00, 08, 02, 00, 00, 00, 00
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}
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# Disable DPC
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NXP_RF_CONF_BLK_3={
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20, 02, 5B, 01, A0, 0B, 57, 11, 11, 90, 78, 0F, 4E, 00, 3D, 95, 00, 00, 3D, 9F, 00, 00, 50, 9F, 00, 00, 59, 9F, 00, 00, 5A, 9F, 00, 00, 64, 9F, 00, 00, 65, 9F, 00, 00, 6E, 9F, 00, 00, 72, 9F, 00, 00, 79, 9F, 00, 00, 7B, 9F, 00, 00, 84, 9F, 00, 00, 86, 9F, 00, 00, 8F, 9F, 00, 00, 91, 9F, 00, 00, 9A, 9F, 00, 00, A1, 9F, 00, 00, A7, 9F, 00, 00, B0, 1F, 00, 00, B9, 1F, 00, 00
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}
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# CE detector/phase
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NXP_RF_CONF_BLK_4={
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20, 02, 21, 04,
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A0, 38, 04, 08, 08, 08, 00,
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A0, 3A, 08, E1, 00, E1, 00, E1, 00, E1, 00,
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A0, 0D, 06, 06, 16, 0E, 00, 1F, 00,
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A0, B1, 02, A8, 02
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}
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###############################################################################
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# Set configuration optimization decision setting
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# Enable = 0x01
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@@ -130,6 +179,46 @@ NXP_SET_CONFIG_ALWAYS=0x01
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# Disable = 0x00
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NXP_RF_UPDATE_REQ=0x01
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###############################################################################
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# Core configuration extensions
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# A009 - Time-out before standby
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# A0EC - Disable/Enable SWP1 interface
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# A0ED - Disable/Enable SWP2 interface
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# A05E - Send RID automatically in Jewel Reader mode
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# A012 - NFCEE interface 2 configuration
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# A040 - Low Power Card Detector Enable
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# A041 - Low Power Card Detector Threshold
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# A042 - Low Power Card Detector Sampling
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# A043 - Low Power Card Detector Hybrid
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# A0D5 - SWP/DWP desired baudrate
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# A0D8 - Configure the number of Sliding Windows used on DWP
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# A0DD - Retry on SWP2 interface
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# A0F2 - SVDD_PWR_REQ enable
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# A09F - Add ON/OFF guard time for SVDD power management(Step value ~1mSec)
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# A096 - Notify all AIDs
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# A037 - SE DWP system configuration
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NXP_CORE_CONF_EXTN={20, 02, 6B, 14,
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A0, 09, 02, 90, 01,
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A0, EC, 01, 01,
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A0, ED, 01, 03,
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A0, 5E, 01, 01,
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A0, 12, 01, 02,
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A0, 40, 01, 01,
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A0, 41, 01, 05,
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A0, 43, 01, 04,
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A0, 46, 02, BA, 27,
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A0, 47, 02, BA, 27,
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A0, 81, 01, 01,
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A0, D5, 01, 0A,
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A0, D8, 01, 02,
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A0, DD, 01, 2D,
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A0, F2, 01, 01,
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A0, 9F, 02, 08, 08,
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A0, 96, 01, 01,
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A0, 37, 01, 35,
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A0, 3F, 01, 01,
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A0, 29, 17, 1A, 07, 00, 1D, 00, 02, 00, 1D, 00, 02, 00, 40, F6, F6, 00, 43, F6, F6, 38, 70, 00, 00, 00
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}
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###############################################################################
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# Core configuration rf field filter settings to enable set to 01 to disable set to 00 last bit
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# NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 01}
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@@ -138,6 +227,25 @@ NXP_RF_UPDATE_REQ=0x01
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# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set to 0x00
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NXP_I2C_FRAGMENTATION_ENABLED=0x00
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###############################################################################
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# Core configuration settings
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NXP_CORE_CONF={ 20, 02, 2E, 0E,
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28, 01, 00,
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21, 01, 00,
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30, 01, 08,
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31, 01, 03,
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32, 01, 60,
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38, 01, 01,
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33, 04, 01, 02, 03, 04,
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54, 01, 06,
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50, 01, 02,
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5B, 01, 00,
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80, 01, 01,
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81, 01, 01,
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82, 01, 0E,
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18, 01, 01
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}
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###############################################################################
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# Mifare Classic Key settings
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# NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
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@@ -1,109 +0,0 @@
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NXP_RF_CONF_BLK_1={
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20, 02, E7, 1B,
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A0, 0D, 06, 06, 37, 08, 76, 00, 00,
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A0, 0D, 03, 24, 03, 7D,
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A0, 0D, 06, 02, 35, 00, 3E, 00, 00,
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A0, 0D, 06, 04, 35, F4, 05, 70, 02,
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A0, 0D, 06, C2, 35, 00, 3E, 00, 03,
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A0, 0D, 06, 04, 42, F8, 40, FF, FF,
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A0, 0D, 04, 32, 42, F8, 40,
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A0, 0D, 04, 46, 42, 68, 40,
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A0, 0D, 04, 56, 42, 78, 40,
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A0, 0D, 04, 5C, 42, 80, 40,
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A0, 0D, 04, CA, 42, 68, 40,
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A0, 0D, 06, 06, 42, 00, 02, F6, F6,
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A0, 0D, 06, 32, 4A, 53, 07, 00, 1B,
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A0, 0D, 06, 46, 4A, 33, 07, 00, 07,
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A0, 0D, 06, 56, 4A, 43, 07, 00, 07,
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A0, 0D, 06, 5C, 4A, 11, 07, 01, 07,
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A0, 0D, 06, 34, 44, 66, 08, 00, 00,
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A0, 0D, 06, 48, 44, 65, 0A, 00, 00,
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A0, 0D, 06, 58, 44, 55, 08, 00, 00,
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A0, 0D, 06, 5E, 44, 55, 08, 00, 00,
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A0, 0D, 06, CA, 44, 65, 0A, 00, 00,
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A0, 0D, 06, 06, 44, 04, 04, C4, 00,
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A0, 0D, 06, 34, 2D, DC, 20, 04, 00,
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A0, 0D, 06, 48, 2D, 15, 34, 1F, 01,
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A0, 0D, 06, 58, 2D, 0D, 48, 0C, 01,
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A0, 0D, 06, 5E, 2D, 0D, 5A, 0C, 01,
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A0, 0D, 06, CA, 2D, 15, 34, 1F, 01
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}
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# Enable DLMA
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NXP_RF_CONF_BLK_2={
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20, 02, D6, 01, A0, 34, D2, 23, 04, 18, 47, 40, 00, 00, 40, 01, 32, 00, 40, 01, 47, 00, 40, 01, 73, 00, 40, 01, A7, 00, 40, 01, F5, 00, 08, 01, 5C, 01, 48, 00, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 48, 01, 00, 00, 08, 03, 00, 00, 08, 01, 00, 00, C8, 02, 00, 00, C8, 00, 00, 00, 88, 02, 00, 00, 48, 02, 00, 00, B8, 00, 00, 00, 68, 00, 00, 00, 18, 00, 00, 00, 08, 02, 00, 00, 00, 00, 00, 00, 00, 00, 47, 00, 00, 40, 01, 32, 00, 40, 01, 47, 00, 40, 01, 73, 00, 40, 01, A7, 00, 40, 01, F5, 00, 08, 01, 5C, 01, 48, 00, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 48, 01, 00, 00, 08, 03, 00, 00, 08, 01, 00, 00, C8, 02, 00, 00, C8, 00, 00, 00, 88, 02, 00, 00, 48, 02, 00, 00, B8, 00, 00, 00, 68, 00, 00, 00, 18, 00, 00, 00, 08, 02, 00, 00, 00, 00
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}
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# Disable DPC
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NXP_RF_CONF_BLK_3={
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20, 02, 5B, 01, A0, 0B, 57, 11, 11, 90, 78, 0F, 4E, 00, 3D, 95, 00, 00, 3D, 9F, 00, 00, 50, 9F, 00, 00, 59, 9F, 00, 00, 5A, 9F, 00, 00, 64, 9F, 00, 00, 65, 9F, 00, 00, 6E, 9F, 00, 00, 72, 9F, 00, 00, 79, 9F, 00, 00, 7B, 9F, 00, 00, 84, 9F, 00, 00, 86, 9F, 00, 00, 8F, 9F, 00, 00, 91, 9F, 00, 00, 9A, 9F, 00, 00, A1, 9F, 00, 00, A7, 9F, 00, 00, B0, 1F, 00, 00, B9, 1F, 00, 00
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}
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# CE detector/phase
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NXP_RF_CONF_BLK_4={
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20, 02, 21, 04,
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A0, 38, 04, 08, 08, 08, 00,
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A0, 3A, 08, E1, 00, E1, 00, E1, 00, E1, 00,
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A0, 0D, 06, 06, 16, 0E, 00, 1F, 00,
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A0, B1, 02, A8, 02
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}
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###############################################################################
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# Core configuration extensions
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# A009 - Time-out before standby
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# A0EC - Disable/Enable SWP1 interface
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# A0ED - Disable/Enable SWP2 interface
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# A05E - Send RID automatically in Jewel Reader mode
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# A012 - NFCEE interface 2 configuration
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# A040 - Low Power Card Detector Enable
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# A041 - Low Power Card Detector Threshold
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# A042 - Low Power Card Detector Sampling
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# A043 - Low Power Card Detector Hybrid
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# A0D5 - SWP/DWP desired baudrate
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# A0D8 - Configure the number of Sliding Windows used on DWP
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# A0DD - Retry on SWP2 interface
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# A0F2 - SVDD_PWR_REQ enable
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# A09F - Add ON/OFF guard time for SVDD power management(Step value ~1mSec)
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# A096 - Notify all AIDs
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# A037 - SE DWP system configuration
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NXP_CORE_CONF_EXTN={20, 02, 6B, 14,
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A0, 09, 02, 90, 01,
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A0, EC, 01, 01,
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A0, ED, 01, 03,
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A0, 5E, 01, 01,
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A0, 12, 01, 02,
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A0, 40, 01, 01,
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A0, 41, 01, 05,
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A0, 43, 01, 04,
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A0, 46, 02, BA, 27,
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A0, 47, 02, BA, 27,
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A0, 81, 01, 01,
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A0, D5, 01, 0A,
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A0, D8, 01, 02,
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A0, DD, 01, 2D,
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A0, F2, 01, 01,
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A0, 9F, 02, 08, 08,
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A0, 96, 01, 01,
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A0, 37, 01, 35,
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A0, 3F, 01, 01,
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A0, 29, 17, 1A, 07, 00, 1D, 00, 02, 00, 1D, 00, 02, 00, 40, F6, F6, 00, 43, F6, F6, 38, 70, 00, 00, 00
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}
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###############################################################################
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# Core configuration settings
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NXP_CORE_CONF={ 20, 02, 2E, 0E,
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28, 01, 00,
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21, 01, 00,
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30, 01, 08,
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31, 01, 03,
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32, 01, 60,
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38, 01, 01,
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33, 04, 01, 02, 03, 04,
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54, 01, 06,
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50, 01, 02,
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5B, 01, 00,
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80, 01, 01,
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81, 01, 01,
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82, 01, 0E,
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18, 01, 01
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}
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