Merge "ARM: dts: msm: Enable HMP for SA8155 VM"

This commit is contained in:
qctecmdr
2022-08-02 05:49:04 -07:00
committed by Gerrit - the friendly Code Review server

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@@ -4,4 +4,103 @@
model = "Qualcomm Technologies, Inc. SA8155 Guest Virtual Machine";
qcom,msm-name = "SA8155 v2";
qcom,msm-id = <362 0x20000>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
capacity-dmips-mhz = <1024>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
capacity-dmips-mhz = <1024>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
capacity-dmips-mhz = <1024>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
capacity-dmips-mhz = <1024>;
};
CPU4: cpu@4 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x4>;
capacity-dmips-mhz = <414>;
};
CPU5: cpu@5 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x5>;
capacity-dmips-mhz = <414>;
};
CPU6: cpu@6 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x6>;
capacity-dmips-mhz = <414>;
};
CPU7: cpu@7 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x7>;
capacity-dmips-mhz = <414>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
};
};