Merge "dt-bindings: Add missing dt-bindings"

bindings/arm/msm/jtag-mm.txt

@@ -0,0 +1,32 @@
+* JTAG-MM
+
+The jtag-mm entry specifies the memory mapped addresses for the debug and ETM
+registers. The jtag-mm driver uses these to save and restore the registers
+using memory mapped access during power collapse so as to retain their state
+across power collapse. This is necessary in case cp14 access to the registers
+is not permitted.
+
+Required Properties:
+compatible: component name used for driver matching, should be:
+	"qcom,jtag-mm"		- for jtag-mm device
+	"qcom,jtagv8-mm"	- for jtagv8-mm device supporting ARMv8 targets
+
+	reg: physical base address and length of the register set
+	reg-names: should be "etm-base" for etm register set and "debug-base"
+		   for debug register set.
+	qcom,coresight-jtagmm-cpu: specifies phandle for the cpu associated
+				   with the jtag-mm device
+	qcom,si-enable : boolean, indicating etm save and restore is
+			 supported via system instructions
+	qcom,save-restore-disable : boolean, to disable etm save and restore
+				    functionality
+
+Example:
+jtag_mm: jtagmm@fc332000 {
+	compatible = "qcom,jtag-mm";
+	reg = <0xfc332000 0x1000>,
+		<0xfc333000 0x1000>;
+	reg-names = "etm-base","debug-base";
+
+	qcom,coresight-jtagmm-cpu = <&CPU0>;
+};

bindings/arm/msm/msm.txt

@@ -287,4 +287,6 @@ compatible = "qcom,sa6155-adp-air"
 compatible = "qcom,sa6155-adp-star"
 compatible = "qcom,sa6155p-adp-air"
 compatible = "qcom,sa6155p-adp-star"
-
+compatible = "qcom,khaje-idp"
+compatible = "qcom,khaje-qrd"
+compatible = "qcom,khaje-atp"

bindings/arm/msm/msm_gladiator_erp.txt

@@ -0,0 +1,21 @@
+* MSM Gladiator error reporting driver
+
+Required properties:
+- compatible: Should be "qcom,msm-gladiator" or "qcom,msm-gladiator-v2" or
+"qcom,msm-gladiator-v3"
+- reg: I/O address Gladiator H/W block
+- reg-names: Should be "gladiator_base"
+- interrupts: Should contain the gladiator error interrupt number
+- clock-names: Should be "atb_clk"
+- clocks: Handles to clocks specified in "clock-names" property.
+
+Example:
+
+qcom,msm-gladiator-v2@b1c0000 {
+	compatible = "qcom,msm-gladiator";
+	reg = <0xb1c0000 0xe000>;
+	reg-names = "gladiator_base";
+	interrupts = <0 34 0>;
+	clock-names = "atb_clk";
+	clocks = <&clock_gcc clk_qdss_clk>;
+}

bindings/arm/msm/msm_gladiator_hang_detect.txt

@@ -0,0 +1,41 @@
+Gladiator Hang Detection provides sysfs entries for configuring
+thresholds and enable on ACE_port, IO_port, M1_port, M2_port,
+and PCIO_port
+
+If gladiator is hung for threshold time (value * 5ns) and no
+heart beat event from gladiator port to gladiator hang monitor
+detection, gladiator hang interrupt would be generated to reset
+the SOC to collect all cores context.
+
+Gladiator hang detection can be enabled on different ports.
+
+Writing 1 into ace_enabled sysfs entry, enables gladiator hang
+detection on ACE port
+Writing 1 into io_enabled sysfs entry, enables gladiator hang
+detection on IO port
+Writing 1 into ace_enabled sysfs entry, enables gladiator hang
+detection on M1 port
+Writing 1 into ace_enabled sysfs entry, enables gladiator hang
+detection on M2 port
+Writing 1 into pcio_enabled sysfs entry, enables gladiator hang
+detection on PCIO port
+
+Required properties:
+- compatible : "qcom,gladiator-hang-detect" or "qcom,gladiator-hang-detect-v2"
+				or "qcom,gladiator-hang-detect-v3"
+- qcom, threshold-arr:
+		Array of APCS_COMMON_GLADIATOR_HANG_THRESHOLD_n register
+		address
+- qcom, config-reg:
+		APCS_COMMON_GLADIATOR_HANG_CONFIG register address
+
+Optional properties:
+
+Example:
+	For msmcobalt:
+		qcom,ghd {
+				compatible = "qcom,gladiator-hang-detect";
+				qcom,threshold-arr = <0x179d141c 0x179d1420
+					0x179d1424 0x179d1428 0x179d1420 0x179d1430>;
+				qcom,config-reg = <0x179d1434>;
+		};

bindings/edac/arm64_cache_erp.txt

@@ -0,0 +1,34 @@
+* ARM Cortex A53 / A57 cache error reporting driver
+
+Required properties:
+- compatible: Should be "arm,arm64-cpu-erp"
+- interrupts: List of hardware interrupts that may indicate an error condition
+  in the CPU subsystem, or in the L1 / L2 caches. At least one interrupt entry
+  is required.
+- interrupt-names: Must contain one or more of the following IRQ types:
+	"pri-dbe-irq" - double-bit error interrupt for primary cluster
+	"sec-dbe-irq" - double-bit error interrupt for secondary cluster
+	"pri-ext-irq" - external bus error interrupt for primary cluster
+	"sec-ext-irq" - external bus error interrupt for secondary cluster
+	"cci-irq"     - CCI error interrupt. If this property is present, having
+			the 'cci' reg-base defined using the 'reg' property is
+			recommended.
+	At least one irq entry is required.
+
+Optional properties:
+- reg: Should contain physical address of the CCI register space
+- reg-names: Should contain 'cci'. Must be present if 'reg' property is present
+- poll-delay-msec: Indicates how often the edac check callback should be called. Time in msec.
+
+Example:
+	cpu_cache_erp {
+		compatible = "arm,arm64-cpu-erp";
+		interrupt-names = "pri-dbe-irq",
+				  "sec-dbe-irq",
+				  "pri-ext-irq",
+				  "sec-ext-irq";
+		interrupts = <0 92 0>,
+			     <0 91 0>,
+			     <0 96 0>,
+			     <0 95 0>;
+	};

bindings/platform/msm/msm_demux.txt

@@ -0,0 +1,13 @@
+* Demux
+
+Demux is responsible for demuxing the transport stream contents
+to respective elementary streams
+
+Required properties:
+- compatible : Should be "qcom,demux"
+
+Example:
+
+        demux {
+                compatible = "qcom,demux";
+        };