Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add L3 interconnect device for Cinder"

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qctecmdr
2022-06-10 07:24:50 -07:00
committed by Gerrit - the friendly Code Review server
parent fda1a2c67d ad843264bb
commit 06e9f7079b
2 changed files with 10 additions and 10 deletions
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11
bindings/interconnect/qcom,epss-l3.txt
View File

@@ -6,7 +6,7 @@ performance states of the CPU subsystem.
Required properties :
- compatible : shall contain only one of the following:
"qcom,lahaina-epss-l3-shared",
"qcom,cinder-epss-l3-cpu",
"qcom,lahaina-epss-l3-cpu";
- reg : Address and length of the register set for the device
- clock-names: should contain "xo", "alternate"
@@ -16,15 +16,6 @@ Required properties :
Examples:
epss_l3_shared: l3_shared@18590000 {
reg = <0x18590000 0x1000>;
compatible = "qcom,lahaina-epss-l3-shared";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_GPLL0>;
};
epss_l3_cpu: l3_cpu@18590000{
reg = <0x18590000 0x4000>;
compatible = "qcom,lahaina-epss-l3-cpu";

9
qcom/cinder.dtsi
View File

@@ -1195,6 +1195,15 @@
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
epss_l3_cpu: l3_cpu@17d90000 {
reg = <0x17d90000 0x2000>;
compatible = "qcom,cinder-epss-l3-cpu";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
status = "disabled";
};
};
&firmware {