mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 05:00:27 +00:00
display-devicetree: Update from OnePlus 11 14.0.0.201(EX01)
Change-Id: Ic1ef794e0a7eb9d0935352664adc92e06ce33276 Signed-off-by: chandu078 <chandudyavanapelli03@gmail.com>
This commit is contained in:
chandu078
Bruno Martins
@@ -18,6 +18,9 @@ endif
|
||||
dtbo-$(CONFIG_WUKONG_DTB) += oplus/wukong-21131-display-kalama-overlay.dtbo
|
||||
dtbo-$(CONFIG_SALAMI_DTB) += oplus/salami-22811-display-kalama-overlay.dtbo
|
||||
dtbo-$(CONFIG_XUEYING_DTB) += oplus/xueying-22003-display-kalama-overlay.dtbo
|
||||
dtbo-$(CONFIG_ZONDA_DTB) += oplus/zonda-22635-display-kalama-overlay.dtbo
|
||||
dtbo-$(CONFIG_XIGUA_DTB) += oplus/xigua-22851-display-kalama-overlay.dtbo
|
||||
dtbo-$(CONFIG_ASTON_DTB) += oplus/aston-23801-display-kalama-overlay.dtbo
|
||||
#OPLUS_DTS_OVERLAY end
|
||||
else
|
||||
dtbo-$(CONFIG_ARCH_KALAMA) += display/trustedvm-kalama-sde-display-mtp-overlay.dtbo \
|
||||
|
||||
@@ -168,8 +168,8 @@
|
||||
qcom,sde-has-dest-scaler;
|
||||
qcom,sde-max-trusted-vm-displays = <1>;
|
||||
|
||||
qcom,sde-max-bw-low-kbps = <13600000>;
|
||||
qcom,sde-max-bw-high-kbps = <18200000>;
|
||||
qcom,sde-max-bw-low-kbps = <17300000>;
|
||||
qcom,sde-max-bw-high-kbps = <25000000>;
|
||||
qcom,sde-min-core-ib-kbps = <2500000>;
|
||||
qcom,sde-min-llcc-ib-kbps = <0>;
|
||||
qcom,sde-min-dram-ib-kbps = <800000>;
|
||||
|
||||
@@ -200,29 +200,10 @@
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
|
||||
};
|
||||
|
||||
&qupv3_se4_spi {
|
||||
/* goodix-berlin@0 {
|
||||
panel = <&dsi_vtdr6130_amoled_cmd
|
||||
&dsi_vtdr6130_amoled_video>;
|
||||
}; */
|
||||
goodix_gt9966@0{
|
||||
panel = <&dsi_panel_boe_nt37900_2440_2268_dsc_cmd>;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se10_i2c {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&qupv3_se10_spi {
|
||||
goodix_gt9916@0{
|
||||
panel = <&dsi_panel_boe_nt37705_1116_2484_dsc_cmd>;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se8_spi {
|
||||
/*
|
||||
goodix-berlin@0 {
|
||||
panel = <&dsi_vtdr6130_amoled_cmd
|
||||
&dsi_vtdr6130_amoled_video>;
|
||||
};
|
||||
}; */
|
||||
};
|
||||
|
||||
17
qcom/display/oplus/aston-23801-display-kalama-overlay.dts
Normal file
17
qcom/display/oplus/aston-23801-display-kalama-overlay.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
#include <dt-bindings/oplus/hw-id.h>
|
||||
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h>
|
||||
#include "../display/kalama-sde-display-mtp-overlay.dts"
|
||||
#include "kalama-display-overlay-common.dtsi"
|
||||
#include "aston-23801-display-kalama-overlay.dtsi"
|
||||
/* #if defined(CONFIG_PXLW_IRIS) */
|
||||
#include "pxlw-iris7p-kalama-common.dtsi"
|
||||
#include "pxlw-aston/dsi-panel-pxlw-iris7p.dtsi"
|
||||
/* #endif */
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama MTP,aston";
|
||||
|
||||
oplus,project-id = <23861 23801>;
|
||||
};
|
||||
91
qcom/display/oplus/aston-23801-display-kalama-overlay.dtsi
Normal file
91
qcom/display/oplus/aston-23801-display-kalama-overlay.dtsi
Normal file
@@ -0,0 +1,91 @@
|
||||
/* add for custom clk by gpio5 */
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include "panel/dsi-panel-AA551-P-3-A0004-dsc-cmd.dtsi"
|
||||
|
||||
&soc {
|
||||
oplus_display_dev: oplus,dsi-display-dev {
|
||||
oplus,dsi-panel-primary = <
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_panel_AA551_P_3_A0004_dsc_cmd
|
||||
>;
|
||||
oplus,dsi-panel-secondary = <
|
||||
>;
|
||||
oplus,dsi-panel-extended = <>;
|
||||
};
|
||||
|
||||
oplus_aston_dsi_panel_pwr_supply: oplus_aston_dsi_panel_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <200000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <2>;
|
||||
qcom,supply-pre-off-sleep = <8>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "vci";
|
||||
qcom,supply-min-voltage = <3000000>;
|
||||
qcom,supply-max-voltage = <3000000>;
|
||||
qcom,supply-enable-load = <10000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
qcom,supply-post-on-sleep = <10>;
|
||||
qcom,supply-pre-on-sleep = <2>;
|
||||
qcom,supply-pre-off-sleep = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,platform-te-gpio-1 = <&tlmm 87 0>;
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend",
|
||||
"te1_active", "te1_suspend";
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
|
||||
pinctrl-2 = <&sde_te1_active>;
|
||||
pinctrl-3 = <&sde_te1_suspend>;
|
||||
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 2>,
|
||||
<&mdss_dsi_phy1 3>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
/* add for custom clk by gpio5 */
|
||||
<&rpmhcc RPMH_DIV_CLK1>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1",
|
||||
"mdp_core_clk",
|
||||
/* add for custom clk by gpio5 */
|
||||
"div_clk";
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_te1_active>;
|
||||
pinctrl-1 = <&sde_te1_suspend>;
|
||||
|
||||
/delete-property/ vddio-supply;
|
||||
/delete-property/ vci-supply;
|
||||
/delete-property/ vdd-supply;
|
||||
};
|
||||
&mdss_dsi_phy0 {
|
||||
/delete-property/ qcom,dsi-pll-ssc-en;
|
||||
/delete-property/ qcom,dsi-pll-ssc-mode;
|
||||
};
|
||||
|
||||
&mdss_dsi_phy1 {
|
||||
/delete-property/ qcom,dsi-pll-ssc-en;
|
||||
/delete-property/ qcom,dsi-pll-ssc-mode;
|
||||
};
|
||||
|
||||
&L13B {
|
||||
regulator-max-microvolt = <3200000>;
|
||||
qcom,init-voltage = <3000000>;
|
||||
};
|
||||
@@ -4,4 +4,4 @@
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
/delete-property/ qcom,esd-check-enabled;
|
||||
};
|
||||
};
|
||||
2078
qcom/display/oplus/panel/dsi-panel-AA536-P-3-A0001-dsc-cmd.dtsi
Normal file
2078
qcom/display/oplus/panel/dsi-panel-AA536-P-3-A0001-dsc-cmd.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,384 @@
|
||||
qcom,mdss-dsi-on-evt-command = [
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
15 00 00 40 00 00 02 35 00
|
||||
15 00 00 40 00 00 02 53 20
|
||||
//1-BIT ESD
|
||||
39 00 00 40 00 00 04 FF 08 38 06
|
||||
15 00 00 40 00 00 02 C6 01
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 09 ED FF FF FF F7 FF FF BF FF
|
||||
39 00 00 40 00 00 09 EE FE EF C1 E0 00 C0 01 00
|
||||
15 00 00 40 00 00 02 D2 03
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 F8 01 //FUNCSTION SLECT
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 B3 50 //TE TEST MODE
|
||||
15 00 00 40 00 00 02 B5 03
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62 //OTP DON'T RELOAD
|
||||
39 00 00 40 00 00 04 FF 08 38 31
|
||||
15 00 00 40 00 00 02 D0 81
|
||||
15 00 00 40 00 00 02 A0 F3
|
||||
39 00 00 40 00 00 0B 90 02 03 04 06 07 02 03 04 06 07 //LUT_DBV
|
||||
39 00 00 40 00 00 07 91 04 44 55 03 09 0F //RATIO_Y_R
|
||||
39 00 00 40 00 00 07 92 04 44 55 03 09 0F //RATIO_Y_G
|
||||
39 00 00 40 00 00 07 93 04 44 55 03 09 0F //RATIO_Y_B
|
||||
//CTB DATA VALUE
|
||||
39 00 00 40 00 00 13 80 F0 8B 68 45 21 DF BB 98 75 B0 30 23 28 07 FD FC 02 A9
|
||||
39 00 00 40 00 00 13 81 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 EE F0 AC
|
||||
39 00 00 40 00 00 13 82 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 83 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 84 F0 69 4E 34 19 E7 CC B2 97 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 85 F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 86 F0 8B 68 45 21 DF BB 98 75 F0 22 21 18 00 FE EF F4 AC
|
||||
39 00 00 40 00 00 13 87 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 88 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 89 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8A F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8B F0 5E 46 2F 16 EA D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
//1 LINE AVERAGE
|
||||
39 00 00 40 00 00 09 8F 40 40 40 40 40 40 40 40
|
||||
39 00 00 40 00 00 09 8C 08 0D 0D 0C 09 05 03 00
|
||||
39 00 00 40 00 00 09 8D 0D 0F 0B 08 06 04 03 00
|
||||
39 00 00 40 00 00 07 8E 02 10 08 00 0F 70
|
||||
15 00 00 40 00 00 02 D0 80
|
||||
39 00 00 40 00 00 04 FF 08 38 05
|
||||
15 00 00 40 00 00 02 80 19
|
||||
39 00 00 40 00 00 0A D0 FF AF 56 3D 2D 2D 2D 2D FF //AOD EL INTERAL
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
//DSC 1.2 CONFIG
|
||||
39 00 00 40 00 00 04 FF 08 38 07
|
||||
39 00 00 40 00 00 02 8A 01
|
||||
39 00 00 40 00 00 03 8B 11 E0 //CHANGE PPS TABLE
|
||||
39 00 00 40 00 00 64 81 00 00 00 00 00 12 00 00 AB 30 80 0A DC 04 F0 00 14 02 78
|
||||
02 78 02 00 02 57 00 20 01 F8 00 08 00 0D 05 7A 04 4F 18 00
|
||||
10 E0 07 10 20 00 06 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 77
|
||||
79 7B 7D 7E 02 02 22 00 2A 40 2A BE 3A FC 3A FA 3A F8 3B 38
|
||||
3B 78 3B B6 4B B6 4B F4 4B F4 6C 34 84 74 74 00 00 00 00 00
|
||||
//OSC 138.6MHZ
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 F5 33
|
||||
15 00 00 40 00 00 02 F6 B7
|
||||
15 00 00 40 00 00 02 F7 98
|
||||
//MIPI=556.8MHz_1113.6Mbps OSC
|
||||
39 00 00 40 00 00 04 FF 08 38 22
|
||||
39 00 00 40 00 00 08 D0 00 D6 11 10 32 14 14
|
||||
39 00 00 40 00 00 08 D3 00 D6 11 10 32 14 14
|
||||
39 00 00 40 00 00 08 D6 00 D6 11 10 32 14 14
|
||||
39 00 00 40 00 00 08 D9 00 D6 11 10 32 14 14
|
||||
39 00 00 40 00 00 0A DC 84 94 BB 00 20 C4 A1 CC 10
|
||||
15 00 00 40 00 00 02 DD 01 //TRIM_CMD enable
|
||||
15 00 00 40 00 00 02 DE F1
|
||||
15 00 00 40 00 00 02 DF 80
|
||||
39 00 00 40 00 00 09 E0 02 00 5F 21 00 3C 28 00 //P6_cmd key=3C
|
||||
//DCDC Setting
|
||||
39 00 00 40 00 00 04 FF 08 38 1F
|
||||
39 00 00 40 00 00 03 83 DB 7F
|
||||
39 00 00 40 00 00 03 84 2D 7F
|
||||
39 00 00 40 00 00 04 85 5F 79 07
|
||||
//ESD fixed H linse
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 02 D2 05
|
||||
39 00 00 40 00 00 02 D3 01
|
||||
//Fixed 4095 BL issue
|
||||
39 00 00 40 00 00 04 FF 08 38 49
|
||||
39 00 00 40 00 00 05 97 FE 0F FF 0F
|
||||
|
||||
//EM_DUTY 84
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 01
|
||||
39 00 00 40 00 00 04 FF 08 38 64
|
||||
39 00 00 40 00 00 05 80 00 00 78 05
|
||||
39 00 00 40 00 00 05 81 00 00 78 05
|
||||
39 00 00 40 00 00 05 82 00 00 A7 05
|
||||
39 00 00 40 00 00 05 83 00 00 CB 05
|
||||
39 00 00 40 00 00 05 84 00 00 CB 05
|
||||
39 00 00 40 00 00 05 85 00 00 CB 05
|
||||
39 00 00 40 00 00 05 86 00 00 CB 05
|
||||
39 00 00 40 00 00 05 87 00 02 D7 1E
|
||||
39 00 00 40 00 00 05 88 00 03 31 1E
|
||||
39 00 00 40 00 00 05 89 00 03 B8 1E
|
||||
39 00 00 40 00 00 05 8A 00 04 03 1E
|
||||
39 00 00 40 00 00 05 8B 00 04 36 1E
|
||||
39 00 00 40 00 00 05 8C 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8D 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8E 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8F 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 90 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 91 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 92 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 93 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 94 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 95 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 96 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 97 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 98 00 04 B0 1E
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 00
|
||||
39 00 00 40 00 00 04 FF 08 38 4E
|
||||
|
||||
//HRST
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62
|
||||
39 00 00 40 00 00 04 FF 08 38 01
|
||||
39 00 00 40 00 00 0F 82 00 00 40 0A 00 15 08 08 00 0F 00 00 3E FC
|
||||
39 00 00 40 00 00 0F 83 00 00 C0 00 10 28 08 18 00 00 00 00 3E FC
|
||||
15 00 00 40 00 00 02 94 09
|
||||
15 00 00 40 00 00 02 98 08
|
||||
39 00 00 40 00 00 04 FF 08 38 09
|
||||
39 00 00 40 00 00 03 8E 08 10
|
||||
15 00 00 40 00 00 02 B4 04
|
||||
15 00 00 40 00 00 02 EE 40
|
||||
39 00 00 40 00 00 04 FF 08 38 0A
|
||||
39 00 00 40 00 00 05 82 08 08 00 40
|
||||
39 00 00 40 00 00 05 83 08 18 00 C0
|
||||
39 00 00 40 00 00 05 90 08 08 00 40
|
||||
39 00 00 40 00 00 05 91 08 18 00 C0
|
||||
39 00 00 40 00 00 05 9E 20 20 00 C0
|
||||
39 00 00 40 00 00 05 9F 20 20 00 C0
|
||||
39 00 00 40 00 00 04 FF 08 38 0B
|
||||
39 00 00 40 00 00 09 80 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 82 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 84 00 00 00 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 86 00
|
||||
15 00 00 40 00 00 02 87 00
|
||||
15 00 00 40 00 00 02 88 00
|
||||
39 00 00 40 00 00 09 89 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8A 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8B 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 81 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 83 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 85 20 20 20 20 20 20 20 20
|
||||
39 00 00 40 00 00 02 8C 10
|
||||
39 00 00 40 00 00 02 8D 03
|
||||
39 00 00 40 00 00 02 8E BF
|
||||
39 00 00 40 00 00 09 8F 33 BF BF 33 BF BF 03 BF
|
||||
39 00 00 40 00 00 09 90 00 05 05 00 05 05 00 05
|
||||
39 00 00 40 00 00 09 91 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 06 93 08 00 00 00 10
|
||||
39 00 00 40 00 00 04 FF 08 38 0D
|
||||
15 00 00 40 00 00 02 CF 84
|
||||
15 00 00 40 00 00 02 D0 40
|
||||
15 00 00 40 00 00 02 D1 00
|
||||
15 00 00 40 00 00 02 D2 00
|
||||
15 00 00 40 00 00 02 D3 00
|
||||
15 00 00 40 00 00 02 D4 00
|
||||
15 00 00 40 00 00 02 D5 17
|
||||
15 00 00 40 00 00 02 D6 17
|
||||
15 00 00 40 00 00 02 D7 00
|
||||
15 00 00 40 00 00 02 D8 00
|
||||
|
||||
39 00 00 00 00 00 04 FF 08 38 00
|
||||
05 00 00 00 78 00 01 11
|
||||
//120HZ
|
||||
39 00 00 40 00 00 04 FF 08 38 2D
|
||||
15 00 00 40 00 00 02 80 00
|
||||
15 00 00 40 00 00 02 D0 01 //120HZ
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 A6 00
|
||||
15 00 00 40 00 00 02 A7 00
|
||||
39 00 00 40 00 00 08 B0 00 00 80 00 00 00 00
|
||||
39 00 00 40 00 00 09 B1 FF FF FF 00 00 00 00 00
|
||||
39 00 00 40 00 00 08 C0 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 06 C1 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 B6 B0
|
||||
15 00 00 40 00 00 02 B8 00
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 BC 52
|
||||
15 00 00 40 00 00 02 BD 34
|
||||
15 00 00 40 00 00 02 BE 56
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-on-dvt-command = [
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
15 00 00 40 00 00 02 35 00
|
||||
15 00 00 40 00 00 02 53 20
|
||||
//1-BIT ESD
|
||||
39 00 00 40 00 00 04 FF 08 38 06
|
||||
15 00 00 40 00 00 02 C6 01
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 09 ED FF FF FF F7 FF FF BF FF
|
||||
39 00 00 40 00 00 09 EE FE EF C1 E0 00 C0 01 00
|
||||
15 00 00 40 00 00 02 D2 03
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 F8 01 //FUNCSTION SLECT
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 B3 50 //TE TEST MODE
|
||||
15 00 00 40 00 00 02 B5 03
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62 //OTP DON'T RELOAD
|
||||
39 00 00 40 00 00 04 FF 08 38 31
|
||||
15 00 00 40 00 00 02 D0 81
|
||||
15 00 00 40 00 00 02 A0 F3
|
||||
39 00 00 40 00 00 0B 90 02 03 04 06 07 02 03 04 06 07 //LUT_DBV
|
||||
39 00 00 40 00 00 07 91 04 44 55 03 09 0F //RATIO_Y_R
|
||||
39 00 00 40 00 00 07 92 04 44 55 03 09 0F //RATIO_Y_G
|
||||
39 00 00 40 00 00 07 93 04 44 55 03 09 0F //RATIO_Y_B
|
||||
//CTB DATA VALUE
|
||||
39 00 00 40 00 00 13 80 F0 8B 68 45 21 DF BB 98 75 B0 30 23 28 07 FD FC 02 A9
|
||||
39 00 00 40 00 00 13 81 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 EE F0 AC
|
||||
39 00 00 40 00 00 13 82 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 83 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 84 F0 69 4E 34 19 E7 CC B2 97 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 85 F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 86 F0 8B 68 45 21 DF BB 98 75 F0 22 21 18 00 FE EF F4 AC
|
||||
39 00 00 40 00 00 13 87 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 88 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 89 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8A F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8B F0 5E 46 2F 16 EA D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
//1 LINE AVERAGE
|
||||
39 00 00 40 00 00 09 8F 40 40 40 40 40 40 40 40
|
||||
39 00 00 40 00 00 09 8C 08 0D 0D 0C 09 05 03 00
|
||||
39 00 00 40 00 00 09 8D 0D 0F 0B 08 06 04 03 00
|
||||
39 00 00 40 00 00 07 8E 02 10 08 00 0F 70
|
||||
15 00 00 40 00 00 02 D0 80
|
||||
39 00 00 40 00 00 04 FF 08 38 05
|
||||
15 00 00 40 00 00 02 80 19
|
||||
39 00 00 40 00 00 0A D0 FF AF 56 3D 2D 2D 2D 2D FF //AOD EL INTERAL
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
//DSC 1.2 CONFIG
|
||||
39 00 00 40 00 00 04 FF 08 38 07
|
||||
39 00 00 40 00 00 02 8A 01
|
||||
39 00 00 40 00 00 03 8B 11 E0 //CHANGE PPS TABLE
|
||||
39 00 00 40 00 00 64 81 00 00 00 00 00 12 00 00 AB 30 80 0A DC 04 F0 00 14 02 78
|
||||
02 78 02 00 02 57 00 20 01 F8 00 08 00 0D 05 7A 04 4F 18 00
|
||||
10 E0 07 10 20 00 06 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 77
|
||||
79 7B 7D 7E 02 02 22 00 2A 40 2A BE 3A FC 3A FA 3A F8 3B 38
|
||||
3B 78 3B B6 4B B6 4B F4 4B F4 6C 34 84 74 74 00 00 00 00 00
|
||||
//OSC 138.6MHZ
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 F5 33
|
||||
15 00 00 40 00 00 02 F6 B7
|
||||
15 00 00 40 00 00 02 F7 98
|
||||
//MIPI=556.8MHz_1113.6Mbps OSC
|
||||
39 00 00 40 00 00 04 FF 08 38 22
|
||||
39 00 00 40 00 00 08 D0 00 D6 11 10 32 14 14
|
||||
39 00 00 40 00 00 08 D3 00 D6 11 10 32 14 14
|
||||
39 00 00 40 00 00 08 D6 00 D6 11 10 32 14 14
|
||||
39 00 00 40 00 00 08 D9 00 D6 11 10 32 14 14
|
||||
39 00 00 40 00 00 0A DC 84 94 BB 00 20 C4 A1 CC 10
|
||||
15 00 00 40 00 00 02 DD 01 //TRIM_CMD enable
|
||||
15 00 00 40 00 00 02 DE F1
|
||||
15 00 00 40 00 00 02 DF 80
|
||||
39 00 00 40 00 00 09 E0 02 00 5F 21 00 3C 28 00 //P6_cmd key=3C
|
||||
//DCDC Setting
|
||||
39 00 00 40 00 00 04 FF 08 38 1F
|
||||
39 00 00 40 00 00 03 83 DB 7F
|
||||
39 00 00 40 00 00 03 84 2D 7F
|
||||
39 00 00 40 00 00 04 85 5F 79 07
|
||||
//ESD fixed H linse
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 02 D2 05
|
||||
39 00 00 40 00 00 02 D3 01
|
||||
//Fixed 4095 BL issue
|
||||
39 00 00 40 00 00 04 FF 08 38 49
|
||||
39 00 00 40 00 00 05 97 FE 0F FF 0F
|
||||
//EM_DUTY 92.5
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 01
|
||||
39 00 00 40 00 00 04 FF 08 38 64
|
||||
39 00 00 40 00 00 05 80 00 00 57 05
|
||||
39 00 00 40 00 00 05 81 00 00 57 05
|
||||
39 00 00 40 00 00 05 82 00 00 57 05
|
||||
39 00 00 40 00 00 05 83 00 00 57 05
|
||||
39 00 00 40 00 00 05 84 00 00 57 05
|
||||
39 00 00 40 00 00 05 85 00 00 57 05
|
||||
39 00 00 40 00 00 05 86 00 00 CB 05
|
||||
39 00 00 40 00 00 05 87 00 02 D7 1E
|
||||
39 00 00 40 00 00 05 88 00 03 31 1E
|
||||
39 00 00 40 00 00 05 89 00 03 B8 1E
|
||||
39 00 00 40 00 00 05 8A 00 04 03 1E
|
||||
39 00 00 40 00 00 05 8B 00 04 36 1E
|
||||
39 00 00 40 00 00 05 8C 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8D 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8E 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8F 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 90 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 91 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 92 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 93 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 94 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 95 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 96 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 97 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 98 00 04 B0 1E
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 00
|
||||
39 00 00 40 00 00 04 FF 08 38 4E
|
||||
//HRST
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62
|
||||
39 00 00 40 00 00 04 FF 08 38 01
|
||||
39 00 00 40 00 00 0F 82 00 00 40 0A 00 15 08 08 00 0F 00 00 3E FC
|
||||
39 00 00 40 00 00 0F 83 00 00 C0 00 10 1C 08 18 00 00 00 00 3E FC
|
||||
15 00 00 40 00 00 02 94 09
|
||||
15 00 00 40 00 00 02 98 08
|
||||
39 00 00 40 00 00 04 FF 08 38 09
|
||||
39 00 00 40 00 00 03 8E 08 10
|
||||
15 00 00 40 00 00 02 B4 04
|
||||
15 00 00 40 00 00 02 EE 40
|
||||
39 00 00 40 00 00 04 FF 08 38 0A
|
||||
39 00 00 40 00 00 05 82 08 08 00 40
|
||||
39 00 00 40 00 00 05 83 08 18 00 C0
|
||||
39 00 00 40 00 00 05 90 08 08 00 40
|
||||
39 00 00 40 00 00 05 91 08 18 00 C0
|
||||
39 00 00 40 00 00 05 9E 20 20 00 C0
|
||||
39 00 00 40 00 00 05 9F 20 20 00 C0
|
||||
39 00 00 40 00 00 04 FF 08 38 0B
|
||||
39 00 00 40 00 00 09 80 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 82 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 84 00 00 00 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 86 00
|
||||
15 00 00 40 00 00 02 87 00
|
||||
15 00 00 40 00 00 02 88 00
|
||||
39 00 00 40 00 00 09 89 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8A 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8B 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 81 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 83 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 85 20 20 20 20 20 20 20 20
|
||||
39 00 00 40 00 00 02 8C 10
|
||||
39 00 00 40 00 00 02 8D 03
|
||||
39 00 00 40 00 00 02 8E BF
|
||||
39 00 00 40 00 00 09 8F 33 BF BF 33 BF BF 03 BF
|
||||
39 00 00 40 00 00 09 90 00 05 05 00 05 05 00 05
|
||||
39 00 00 40 00 00 09 91 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 06 93 08 00 00 00 10
|
||||
39 00 00 40 00 00 04 FF 08 38 0D
|
||||
15 00 00 40 00 00 02 CF 84
|
||||
15 00 00 40 00 00 02 D0 40
|
||||
15 00 00 40 00 00 02 D1 00
|
||||
15 00 00 40 00 00 02 D2 00
|
||||
15 00 00 40 00 00 02 D3 00
|
||||
15 00 00 40 00 00 02 D4 00
|
||||
15 00 00 40 00 00 02 D5 17
|
||||
15 00 00 40 00 00 02 D6 17
|
||||
15 00 00 40 00 00 02 D7 00
|
||||
15 00 00 40 00 00 02 D8 00
|
||||
|
||||
39 00 00 00 00 00 04 FF 08 38 00
|
||||
05 00 00 00 78 00 01 11
|
||||
//120HZ
|
||||
39 00 00 40 00 00 04 FF 08 38 2D
|
||||
15 00 00 40 00 00 02 80 00
|
||||
15 00 00 40 00 00 02 D0 01 //120HZ
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 A6 00
|
||||
15 00 00 40 00 00 02 A7 00
|
||||
39 00 00 40 00 00 08 B0 00 00 80 00 00 00 00
|
||||
39 00 00 40 00 00 09 B1 FF FF FF 00 00 00 00 00
|
||||
39 00 00 40 00 00 08 C0 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 06 C1 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 B6 B0
|
||||
15 00 00 40 00 00 02 B8 00
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 BC 52
|
||||
15 00 00 40 00 00 02 BD 34
|
||||
15 00 00 40 00 00 02 BE 56
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-on-evt-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-dvt-command-state = "dsi_lp_mode";
|
||||
@@ -0,0 +1,378 @@
|
||||
qcom,mdss-dsi-on-evt-command = [
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
15 00 00 40 00 00 02 35 00
|
||||
15 00 00 40 00 00 02 53 20
|
||||
//1-BIT ESD
|
||||
39 00 00 40 00 00 04 FF 08 38 06
|
||||
15 00 00 40 00 00 02 C6 01
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 09 ED FF FF FF F7 FF FF BF FF
|
||||
39 00 00 40 00 00 09 EE FE EF C1 E0 00 C0 01 00
|
||||
15 00 00 40 00 00 02 D2 03
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 F8 01 //FUNCSTION SLECT
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 B3 50 //TE TEST MODE
|
||||
15 00 00 40 00 00 02 B5 03
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62 //OTP DON'T RELOAD
|
||||
39 00 00 40 00 00 04 FF 08 38 31
|
||||
15 00 00 40 00 00 02 D0 81
|
||||
15 00 00 40 00 00 02 A0 F3
|
||||
39 00 00 40 00 00 0B 90 02 03 04 06 07 02 03 04 06 07 //LUT_DBV
|
||||
39 00 00 40 00 00 07 91 04 44 55 03 09 0F //RATIO_Y_R
|
||||
39 00 00 40 00 00 07 92 04 44 55 03 09 0F //RATIO_Y_G
|
||||
39 00 00 40 00 00 07 93 04 44 55 03 09 0F //RATIO_Y_B
|
||||
//CTB DATA VALUE
|
||||
39 00 00 40 00 00 13 80 F0 8B 68 45 21 DF BB 98 75 B0 30 23 28 07 FD FC 02 A9
|
||||
39 00 00 40 00 00 13 81 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 EE F0 AC
|
||||
39 00 00 40 00 00 13 82 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 83 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 84 F0 69 4E 34 19 E7 CC B2 97 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 85 F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 86 F0 8B 68 45 21 DF BB 98 75 F0 22 21 18 00 FE EF F4 AC
|
||||
39 00 00 40 00 00 13 87 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 88 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 89 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8A F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8B F0 5E 46 2F 16 EA D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
//1 LINE AVERAGE
|
||||
39 00 00 40 00 00 09 8F 40 40 40 40 40 40 40 40
|
||||
39 00 00 40 00 00 09 8C 08 0D 0D 0C 09 05 03 00
|
||||
39 00 00 40 00 00 09 8D 0D 0F 0B 08 06 04 03 00
|
||||
39 00 00 40 00 00 07 8E 02 10 08 00 0F 70
|
||||
15 00 00 40 00 00 02 D0 80
|
||||
39 00 00 40 00 00 04 FF 08 38 05
|
||||
15 00 00 40 00 00 02 80 19
|
||||
39 00 00 40 00 00 0A D0 FF AF 56 3D 2D 2D 2D 2D FF //AOD EL INTERAL
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
//DSC 1.2 CONFIG
|
||||
39 00 00 40 00 00 04 FF 08 38 07
|
||||
39 00 00 40 00 00 02 8A 01
|
||||
39 00 00 40 00 00 03 8B 11 E0 //CHANGE PPS TABLE
|
||||
39 00 00 40 00 00 64 81 00 00 00 00 00 12 00 00 AB 30 80 0A DC 04 F0 00 14 02 78
|
||||
02 78 02 00 02 57 00 20 01 F8 00 08 00 0D 05 7A 04 4F 18 00
|
||||
10 E0 07 10 20 00 06 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 77
|
||||
79 7B 7D 7E 02 02 22 00 2A 40 2A BE 3A FC 3A FA 3A F8 3B 38
|
||||
3B 78 3B B6 4B B6 4B F4 4B F4 6C 34 84 74 74 00 00 00 00 00
|
||||
//OSC 138.6MHZ
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 F5 33
|
||||
15 00 00 40 00 00 02 F6 B7
|
||||
15 00 00 40 00 00 02 F7 98
|
||||
//MIPI=556.8MHz_1113.6Mbps OSC
|
||||
39 00 00 40 00 00 04 FF 08 38 22
|
||||
39 00 00 40 00 00 08 D0 00 DA 11 10 32 14 14
|
||||
39 00 00 40 00 00 0A DC 84 94 BB 00 20 C4 A1 CC 10
|
||||
15 00 00 40 00 00 02 DD 01 //TRIM_CMD enable
|
||||
15 00 00 40 00 00 02 DE F1
|
||||
15 00 00 40 00 00 02 DF 80
|
||||
39 00 00 40 00 00 09 E0 02 00 5F 21 00 3C 28 00 //P6_cmd key=3C
|
||||
//DCDC Setting
|
||||
39 00 00 40 00 00 04 FF 08 38 1F
|
||||
39 00 00 40 00 00 03 83 DB 7F
|
||||
39 00 00 40 00 00 03 84 2D 7F
|
||||
39 00 00 40 00 00 04 85 5F 79 07
|
||||
//ESD fixed H linse
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 02 D2 05
|
||||
39 00 00 40 00 00 02 D3 01
|
||||
//Fixed 4095 BL issue
|
||||
39 00 00 40 00 00 04 FF 08 38 49
|
||||
39 00 00 40 00 00 05 97 FE 0F FF 0F
|
||||
|
||||
//EM_DUTY 84
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 01
|
||||
39 00 00 40 00 00 04 FF 08 38 64
|
||||
39 00 00 40 00 00 05 80 00 00 78 05
|
||||
39 00 00 40 00 00 05 81 00 00 78 05
|
||||
39 00 00 40 00 00 05 82 00 00 A7 05
|
||||
39 00 00 40 00 00 05 83 00 00 CB 05
|
||||
39 00 00 40 00 00 05 84 00 00 CB 05
|
||||
39 00 00 40 00 00 05 85 00 00 CB 05
|
||||
39 00 00 40 00 00 05 86 00 00 CB 05
|
||||
39 00 00 40 00 00 05 87 00 02 D7 1E
|
||||
39 00 00 40 00 00 05 88 00 03 31 1E
|
||||
39 00 00 40 00 00 05 89 00 03 B8 1E
|
||||
39 00 00 40 00 00 05 8A 00 04 03 1E
|
||||
39 00 00 40 00 00 05 8B 00 04 36 1E
|
||||
39 00 00 40 00 00 05 8C 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8D 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8E 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8F 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 90 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 91 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 92 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 93 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 94 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 95 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 96 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 97 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 98 00 04 B0 1E
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 00
|
||||
39 00 00 40 00 00 04 FF 08 38 4E
|
||||
|
||||
//HRST
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62
|
||||
39 00 00 40 00 00 04 FF 08 38 01
|
||||
39 00 00 40 00 00 0F 82 00 00 40 0A 00 15 08 08 00 0F 00 00 3E FC
|
||||
39 00 00 40 00 00 0F 83 00 00 C0 00 10 28 08 18 00 00 00 00 3E FC
|
||||
15 00 00 40 00 00 02 94 09
|
||||
15 00 00 40 00 00 02 98 08
|
||||
39 00 00 40 00 00 04 FF 08 38 09
|
||||
39 00 00 40 00 00 03 8E 08 10
|
||||
15 00 00 40 00 00 02 B4 04
|
||||
15 00 00 40 00 00 02 EE 40
|
||||
39 00 00 40 00 00 04 FF 08 38 0A
|
||||
39 00 00 40 00 00 05 82 08 08 00 40
|
||||
39 00 00 40 00 00 05 83 08 18 00 C0
|
||||
39 00 00 40 00 00 05 90 08 08 00 40
|
||||
39 00 00 40 00 00 05 91 08 18 00 C0
|
||||
39 00 00 40 00 00 05 9E 20 20 00 C0
|
||||
39 00 00 40 00 00 05 9F 20 20 00 C0
|
||||
39 00 00 40 00 00 04 FF 08 38 0B
|
||||
39 00 00 40 00 00 09 80 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 82 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 84 00 00 00 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 86 00
|
||||
15 00 00 40 00 00 02 87 00
|
||||
15 00 00 40 00 00 02 88 00
|
||||
39 00 00 40 00 00 09 89 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8A 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8B 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 81 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 83 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 85 20 20 20 20 20 20 20 20
|
||||
39 00 00 40 00 00 02 8C 10
|
||||
39 00 00 40 00 00 02 8D 03
|
||||
39 00 00 40 00 00 02 8E BF
|
||||
39 00 00 40 00 00 09 8F 33 BF BF 33 BF BF 03 BF
|
||||
39 00 00 40 00 00 09 90 00 05 05 00 05 05 00 05
|
||||
39 00 00 40 00 00 09 91 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 06 93 08 00 00 00 10
|
||||
39 00 00 40 00 00 04 FF 08 38 0D
|
||||
15 00 00 40 00 00 02 CF 84
|
||||
15 00 00 40 00 00 02 D0 40
|
||||
15 00 00 40 00 00 02 D1 00
|
||||
15 00 00 40 00 00 02 D2 00
|
||||
15 00 00 40 00 00 02 D3 00
|
||||
15 00 00 40 00 00 02 D4 00
|
||||
15 00 00 40 00 00 02 D5 17
|
||||
15 00 00 40 00 00 02 D6 17
|
||||
15 00 00 40 00 00 02 D7 00
|
||||
15 00 00 40 00 00 02 D8 00
|
||||
|
||||
39 00 00 00 00 00 04 FF 08 38 00
|
||||
05 00 00 00 78 00 01 11
|
||||
//60HZ
|
||||
39 00 00 40 00 00 04 FF 08 38 2D
|
||||
15 00 00 40 00 00 02 80 00
|
||||
15 00 00 40 00 00 02 D0 06
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 A6 00
|
||||
15 00 00 40 00 00 02 A7 00
|
||||
39 00 00 40 00 00 08 B0 00 00 80 00 00 00 00 //60HZ
|
||||
39 00 00 40 00 00 09 B1 FF FF FF 00 00 00 00 00
|
||||
39 00 00 40 00 00 08 C0 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 06 C1 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 B6 B0
|
||||
15 00 00 40 00 00 02 B8 00
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 04 00 02 BC 52
|
||||
15 00 00 40 04 00 02 BD 34
|
||||
15 00 00 40 00 00 02 BE 56
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-on-dvt-command = [
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
15 00 00 40 00 00 02 35 00
|
||||
15 00 00 40 00 00 02 53 20
|
||||
//1-BIT ESD
|
||||
39 00 00 40 00 00 04 FF 08 38 06
|
||||
15 00 00 40 00 00 02 C6 01
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 09 ED FF FF FF F7 FF FF BF FF
|
||||
39 00 00 40 00 00 09 EE FE EF C1 E0 00 C0 01 00
|
||||
15 00 00 40 00 00 02 D2 03
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 F8 01 //FUNCSTION SLECT
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 B3 50 //TE TEST MODE
|
||||
15 00 00 40 00 00 02 B5 03
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62 //OTP DON'T RELOAD
|
||||
39 00 00 40 00 00 04 FF 08 38 31
|
||||
15 00 00 40 00 00 02 D0 81
|
||||
15 00 00 40 00 00 02 A0 F3
|
||||
39 00 00 40 00 00 0B 90 02 03 04 06 07 02 03 04 06 07 //LUT_DBV
|
||||
39 00 00 40 00 00 07 91 04 44 55 03 09 0F //RATIO_Y_R
|
||||
39 00 00 40 00 00 07 92 04 44 55 03 09 0F //RATIO_Y_G
|
||||
39 00 00 40 00 00 07 93 04 44 55 03 09 0F //RATIO_Y_B
|
||||
//CTB DATA VALUE
|
||||
39 00 00 40 00 00 13 80 F0 8B 68 45 21 DF BB 98 75 B0 30 23 28 07 FD FC 02 A9
|
||||
39 00 00 40 00 00 13 81 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 EE F0 AC
|
||||
39 00 00 40 00 00 13 82 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 83 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 84 F0 69 4E 34 19 E7 CC B2 97 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 85 F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 86 F0 8B 68 45 21 DF BB 98 75 F0 22 21 18 00 FE EF F4 AC
|
||||
39 00 00 40 00 00 13 87 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 88 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 89 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8A F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8B F0 5E 46 2F 16 EA D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
//1 LINE AVERAGE
|
||||
39 00 00 40 00 00 09 8F 40 40 40 40 40 40 40 40
|
||||
39 00 00 40 00 00 09 8C 08 0D 0D 0C 09 05 03 00
|
||||
39 00 00 40 00 00 09 8D 0D 0F 0B 08 06 04 03 00
|
||||
39 00 00 40 00 00 07 8E 02 10 08 00 0F 70
|
||||
15 00 00 40 00 00 02 D0 80
|
||||
39 00 00 40 00 00 04 FF 08 38 05
|
||||
15 00 00 40 00 00 02 80 19
|
||||
39 00 00 40 00 00 0A D0 FF AF 56 3D 2D 2D 2D 2D FF //AOD EL INTERAL
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
//DSC 1.2 CONFIG
|
||||
39 00 00 40 00 00 04 FF 08 38 07
|
||||
39 00 00 40 00 00 02 8A 01
|
||||
39 00 00 40 00 00 03 8B 11 E0 //CHANGE PPS TABLE
|
||||
39 00 00 40 00 00 64 81 00 00 00 00 00 12 00 00 AB 30 80 0A DC 04 F0 00 14 02 78
|
||||
02 78 02 00 02 57 00 20 01 F8 00 08 00 0D 05 7A 04 4F 18 00
|
||||
10 E0 07 10 20 00 06 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 77
|
||||
79 7B 7D 7E 02 02 22 00 2A 40 2A BE 3A FC 3A FA 3A F8 3B 38
|
||||
3B 78 3B B6 4B B6 4B F4 4B F4 6C 34 84 74 74 00 00 00 00 00
|
||||
//OSC 138.6MHZ
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 F5 33
|
||||
15 00 00 40 00 00 02 F6 B7
|
||||
15 00 00 40 00 00 02 F7 98
|
||||
//MIPI=556.8MHz_1113.6Mbps OSC
|
||||
39 00 00 40 00 00 04 FF 08 38 22
|
||||
39 00 00 40 00 00 08 D0 00 DA 11 10 32 14 14
|
||||
39 00 00 40 00 00 0A DC 84 94 BB 00 20 C4 A1 CC 10
|
||||
15 00 00 40 00 00 02 DD 01 //TRIM_CMD enable
|
||||
15 00 00 40 00 00 02 DE F1
|
||||
15 00 00 40 00 00 02 DF 80
|
||||
39 00 00 40 00 00 09 E0 02 00 5F 21 00 3C 28 00 //P6_cmd key=3C
|
||||
//DCDC Setting
|
||||
39 00 00 40 00 00 04 FF 08 38 1F
|
||||
39 00 00 40 00 00 03 83 DB 7F
|
||||
39 00 00 40 00 00 03 84 2D 7F
|
||||
39 00 00 40 00 00 04 85 5F 79 07
|
||||
//ESD fixed H linse
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 02 D2 05
|
||||
39 00 00 40 00 00 02 D3 01
|
||||
//Fixed 4095 BL issue
|
||||
39 00 00 40 00 00 04 FF 08 38 49
|
||||
39 00 00 40 00 00 05 97 FE 0F FF 0F
|
||||
//EM_DUTY 92.5
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 01
|
||||
39 00 00 40 00 00 04 FF 08 38 64
|
||||
39 00 00 40 00 00 05 80 00 00 57 05
|
||||
39 00 00 40 00 00 05 81 00 00 57 05
|
||||
39 00 00 40 00 00 05 82 00 00 57 05
|
||||
39 00 00 40 00 00 05 83 00 00 57 05
|
||||
39 00 00 40 00 00 05 84 00 00 57 05
|
||||
39 00 00 40 00 00 05 85 00 00 57 05
|
||||
39 00 00 40 00 00 05 86 00 00 CB 05
|
||||
39 00 00 40 00 00 05 87 00 02 D7 1E
|
||||
39 00 00 40 00 00 05 88 00 03 31 1E
|
||||
39 00 00 40 00 00 05 89 00 03 B8 1E
|
||||
39 00 00 40 00 00 05 8A 00 04 03 1E
|
||||
39 00 00 40 00 00 05 8B 00 04 36 1E
|
||||
39 00 00 40 00 00 05 8C 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8D 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8E 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8F 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 90 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 91 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 92 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 93 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 94 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 95 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 96 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 97 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 98 00 04 B0 1E
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 00
|
||||
39 00 00 40 00 00 04 FF 08 38 4E
|
||||
//HRST
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62
|
||||
39 00 00 40 00 00 04 FF 08 38 01
|
||||
39 00 00 40 00 00 0F 82 00 00 40 0A 00 15 08 08 00 0F 00 00 3E FC
|
||||
39 00 00 40 00 00 0F 83 00 00 C0 00 10 1C 08 18 00 00 00 00 3E FC
|
||||
15 00 00 40 00 00 02 94 09
|
||||
15 00 00 40 00 00 02 98 08
|
||||
39 00 00 40 00 00 04 FF 08 38 09
|
||||
39 00 00 40 00 00 03 8E 08 10
|
||||
15 00 00 40 00 00 02 B4 04
|
||||
15 00 00 40 00 00 02 EE 40
|
||||
39 00 00 40 00 00 04 FF 08 38 0A
|
||||
39 00 00 40 00 00 05 82 08 08 00 40
|
||||
39 00 00 40 00 00 05 83 08 18 00 C0
|
||||
39 00 00 40 00 00 05 90 08 08 00 40
|
||||
39 00 00 40 00 00 05 91 08 18 00 C0
|
||||
39 00 00 40 00 00 05 9E 20 20 00 C0
|
||||
39 00 00 40 00 00 05 9F 20 20 00 C0
|
||||
39 00 00 40 00 00 04 FF 08 38 0B
|
||||
39 00 00 40 00 00 09 80 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 82 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 84 00 00 00 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 86 00
|
||||
15 00 00 40 00 00 02 87 00
|
||||
15 00 00 40 00 00 02 88 00
|
||||
39 00 00 40 00 00 09 89 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8A 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8B 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 81 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 83 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 85 20 20 20 20 20 20 20 20
|
||||
39 00 00 40 00 00 02 8C 10
|
||||
39 00 00 40 00 00 02 8D 03
|
||||
39 00 00 40 00 00 02 8E BF
|
||||
39 00 00 40 00 00 09 8F 33 BF BF 33 BF BF 03 BF
|
||||
39 00 00 40 00 00 09 90 00 05 05 00 05 05 00 05
|
||||
39 00 00 40 00 00 09 91 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 06 93 08 00 00 00 10
|
||||
39 00 00 40 00 00 04 FF 08 38 0D
|
||||
15 00 00 40 00 00 02 CF 84
|
||||
15 00 00 40 00 00 02 D0 40
|
||||
15 00 00 40 00 00 02 D1 00
|
||||
15 00 00 40 00 00 02 D2 00
|
||||
15 00 00 40 00 00 02 D3 00
|
||||
15 00 00 40 00 00 02 D4 00
|
||||
15 00 00 40 00 00 02 D5 17
|
||||
15 00 00 40 00 00 02 D6 17
|
||||
15 00 00 40 00 00 02 D7 00
|
||||
15 00 00 40 00 00 02 D8 00
|
||||
|
||||
39 00 00 00 00 00 04 FF 08 38 00
|
||||
05 00 00 00 78 00 01 11
|
||||
//60HZ
|
||||
39 00 00 40 00 00 04 FF 08 38 2D
|
||||
15 00 00 40 00 00 02 80 00
|
||||
15 00 00 40 00 00 02 D0 06
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 A6 00
|
||||
15 00 00 40 00 00 02 A7 00
|
||||
39 00 00 40 00 00 08 B0 00 00 80 00 00 00 00 //60HZ
|
||||
39 00 00 40 00 00 09 B1 FF FF FF 00 00 00 00 00
|
||||
39 00 00 40 00 00 08 C0 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 06 C1 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 B6 B0
|
||||
15 00 00 40 00 00 02 B8 00
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 04 00 02 BC 52
|
||||
15 00 00 40 04 00 02 BD 34
|
||||
15 00 00 40 00 00 02 BE 56
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-on-evt-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-dvt-command-state = "dsi_lp_mode";
|
||||
@@ -0,0 +1,378 @@
|
||||
qcom,mdss-dsi-on-evt-command = [
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
15 00 00 40 00 00 02 35 00
|
||||
15 00 00 40 00 00 02 53 20
|
||||
//1-BIT ESD
|
||||
39 00 00 40 00 00 04 FF 08 38 06
|
||||
15 00 00 40 00 00 02 C6 01
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 09 ED FF FF FF F7 FF FF BF FF
|
||||
39 00 00 40 00 00 09 EE FE EF C1 E0 00 C0 01 00
|
||||
15 00 00 40 00 00 02 D2 03
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 F8 01 //FUNCSTION SLECT
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 B3 50 //TE TEST MODE
|
||||
15 00 00 40 00 00 02 B5 03
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62 //OTP DON'T RELOAD
|
||||
39 00 00 40 00 00 04 FF 08 38 31
|
||||
15 00 00 40 00 00 02 D0 81
|
||||
15 00 00 40 00 00 02 A0 F3
|
||||
39 00 00 40 00 00 0B 90 02 03 04 06 07 02 03 04 06 07 //LUT_DBV
|
||||
39 00 00 40 00 00 07 91 04 44 55 03 09 0F //RATIO_Y_R
|
||||
39 00 00 40 00 00 07 92 04 44 55 03 09 0F //RATIO_Y_G
|
||||
39 00 00 40 00 00 07 93 04 44 55 03 09 0F //RATIO_Y_B
|
||||
//CTB DATA VALUE
|
||||
39 00 00 40 00 00 13 80 F0 8B 68 45 21 DF BB 98 75 B0 30 23 28 07 FD FC 02 A9
|
||||
39 00 00 40 00 00 13 81 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 EE F0 AC
|
||||
39 00 00 40 00 00 13 82 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 83 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 84 F0 69 4E 34 19 E7 CC B2 97 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 85 F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 86 F0 8B 68 45 21 DF BB 98 75 F0 22 21 18 00 FE EF F4 AC
|
||||
39 00 00 40 00 00 13 87 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 88 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 89 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8A F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8B F0 5E 46 2F 16 EA D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
//1 LINE AVERAGE
|
||||
39 00 00 40 00 00 09 8F 40 40 40 40 40 40 40 40
|
||||
39 00 00 40 00 00 09 8C 08 0D 0D 0C 09 05 03 00
|
||||
39 00 00 40 00 00 09 8D 0D 0F 0B 08 06 04 03 00
|
||||
39 00 00 40 00 00 07 8E 02 10 08 00 0F 70
|
||||
15 00 00 40 00 00 02 D0 80
|
||||
39 00 00 40 00 00 04 FF 08 38 05
|
||||
15 00 00 40 00 00 02 80 19
|
||||
39 00 00 40 00 00 0A D0 FF AF 56 3D 2D 2D 2D 2D FF //AOD EL INTERAL
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
//DSC 1.2 CONFIG
|
||||
39 00 00 40 00 00 04 FF 08 38 07
|
||||
39 00 00 40 00 00 02 8A 01
|
||||
39 00 00 40 00 00 03 8B 11 E0 //CHANGE PPS TABLE
|
||||
39 00 00 40 00 00 64 81 00 00 00 00 00 12 00 00 AB 30 80 0A DC 04 F0 00 14 02 78
|
||||
02 78 02 00 02 57 00 20 01 F8 00 08 00 0D 05 7A 04 4F 18 00
|
||||
10 E0 07 10 20 00 06 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 77
|
||||
79 7B 7D 7E 02 02 22 00 2A 40 2A BE 3A FC 3A FA 3A F8 3B 38
|
||||
3B 78 3B B6 4B B6 4B F4 4B F4 6C 34 84 74 74 00 00 00 00 00
|
||||
//OSC 138.6MHZ
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 F5 33
|
||||
15 00 00 40 00 00 02 F6 B7
|
||||
15 00 00 40 00 00 02 F7 98
|
||||
//MIPI=556.8MHz_1113.6Mbps OSC
|
||||
39 00 00 40 00 00 04 FF 08 38 22
|
||||
39 00 00 40 00 00 08 D0 00 DA 11 10 32 14 14
|
||||
39 00 00 40 00 00 0A DC 84 94 BB 00 20 C4 A1 CC 10
|
||||
15 00 00 40 00 00 02 DD 01 //TRIM_CMD enable
|
||||
15 00 00 40 00 00 02 DE F1
|
||||
15 00 00 40 00 00 02 DF 80
|
||||
39 00 00 40 00 00 09 E0 02 00 5F 21 00 3C 28 00 //P6_cmd key=3C
|
||||
//DCDC Setting
|
||||
39 00 00 40 00 00 04 FF 08 38 1F
|
||||
39 00 00 40 00 00 03 83 DB 7F
|
||||
39 00 00 40 00 00 03 84 2D 7F
|
||||
39 00 00 40 00 00 04 85 5F 79 07
|
||||
//ESD fixed H linse
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 02 D2 05
|
||||
39 00 00 40 00 00 02 D3 01
|
||||
//Fixed 4095 BL issue
|
||||
39 00 00 40 00 00 04 FF 08 38 49
|
||||
39 00 00 40 00 00 05 97 FE 0F FF 0F
|
||||
|
||||
//EM_DUTY 84
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 01
|
||||
39 00 00 40 00 00 04 FF 08 38 64
|
||||
39 00 00 40 00 00 05 80 00 00 78 05
|
||||
39 00 00 40 00 00 05 81 00 00 78 05
|
||||
39 00 00 40 00 00 05 82 00 00 A7 05
|
||||
39 00 00 40 00 00 05 83 00 00 CB 05
|
||||
39 00 00 40 00 00 05 84 00 00 CB 05
|
||||
39 00 00 40 00 00 05 85 00 00 CB 05
|
||||
39 00 00 40 00 00 05 86 00 00 CB 05
|
||||
39 00 00 40 00 00 05 87 00 02 D7 1E
|
||||
39 00 00 40 00 00 05 88 00 03 31 1E
|
||||
39 00 00 40 00 00 05 89 00 03 B8 1E
|
||||
39 00 00 40 00 00 05 8A 00 04 03 1E
|
||||
39 00 00 40 00 00 05 8B 00 04 36 1E
|
||||
39 00 00 40 00 00 05 8C 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8D 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8E 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8F 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 90 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 91 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 92 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 93 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 94 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 95 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 96 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 97 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 98 00 04 B0 1E
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 00
|
||||
39 00 00 40 00 00 04 FF 08 38 4E
|
||||
|
||||
//HRST
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62
|
||||
39 00 00 40 00 00 04 FF 08 38 01
|
||||
39 00 00 40 00 00 0F 82 00 00 40 0A 00 15 08 08 00 0F 00 00 3E FC
|
||||
39 00 00 40 00 00 0F 83 00 00 C0 00 10 28 08 18 00 00 00 00 3E FC
|
||||
15 00 00 40 00 00 02 94 09
|
||||
15 00 00 40 00 00 02 98 08
|
||||
39 00 00 40 00 00 04 FF 08 38 09
|
||||
39 00 00 40 00 00 03 8E 08 10
|
||||
15 00 00 40 00 00 02 B4 04
|
||||
15 00 00 40 00 00 02 EE 40
|
||||
39 00 00 40 00 00 04 FF 08 38 0A
|
||||
39 00 00 40 00 00 05 82 08 08 00 40
|
||||
39 00 00 40 00 00 05 83 08 18 00 C0
|
||||
39 00 00 40 00 00 05 90 08 08 00 40
|
||||
39 00 00 40 00 00 05 91 08 18 00 C0
|
||||
39 00 00 40 00 00 05 9E 20 20 00 C0
|
||||
39 00 00 40 00 00 05 9F 20 20 00 C0
|
||||
39 00 00 40 00 00 04 FF 08 38 0B
|
||||
39 00 00 40 00 00 09 80 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 82 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 84 00 00 00 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 86 00
|
||||
15 00 00 40 00 00 02 87 00
|
||||
15 00 00 40 00 00 02 88 00
|
||||
39 00 00 40 00 00 09 89 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8A 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8B 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 81 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 83 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 85 20 20 20 20 20 20 20 20
|
||||
39 00 00 40 00 00 02 8C 10
|
||||
39 00 00 40 00 00 02 8D 03
|
||||
39 00 00 40 00 00 02 8E BF
|
||||
39 00 00 40 00 00 09 8F 33 BF BF 33 BF BF 03 BF
|
||||
39 00 00 40 00 00 09 90 00 05 05 00 05 05 00 05
|
||||
39 00 00 40 00 00 09 91 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 06 93 08 00 00 00 10
|
||||
39 00 00 40 00 00 04 FF 08 38 0D
|
||||
15 00 00 40 00 00 02 CF 84
|
||||
15 00 00 40 00 00 02 D0 40
|
||||
15 00 00 40 00 00 02 D1 00
|
||||
15 00 00 40 00 00 02 D2 00
|
||||
15 00 00 40 00 00 02 D3 00
|
||||
15 00 00 40 00 00 02 D4 00
|
||||
15 00 00 40 00 00 02 D5 17
|
||||
15 00 00 40 00 00 02 D6 17
|
||||
15 00 00 40 00 00 02 D7 00
|
||||
15 00 00 40 00 00 02 D8 00
|
||||
|
||||
39 00 00 00 00 00 04 FF 08 38 00
|
||||
05 00 00 00 78 00 01 11
|
||||
//90HZ
|
||||
39 00 00 40 00 00 04 FF 08 38 2D
|
||||
15 00 00 40 00 00 02 80 00
|
||||
15 00 00 40 00 00 02 D0 04 //90HZ
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 A6 00
|
||||
15 00 00 40 00 00 02 A7 00
|
||||
39 00 00 40 00 00 08 B0 00 00 80 00 00 00 00
|
||||
39 00 00 40 00 00 09 B1 FF FF FF 00 00 00 00 00
|
||||
39 00 00 40 00 00 08 C0 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 06 C1 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 B6 B0
|
||||
15 00 00 40 00 00 02 B8 00
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 04 00 02 BC 52
|
||||
15 00 00 40 04 00 02 BD 34
|
||||
15 00 00 40 00 00 02 BE 56
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-on-dvt-command = [
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
15 00 00 40 00 00 02 35 00
|
||||
15 00 00 40 00 00 02 53 20
|
||||
//1-BIT ESD
|
||||
39 00 00 40 00 00 04 FF 08 38 06
|
||||
15 00 00 40 00 00 02 C6 01
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 09 ED FF FF FF F7 FF FF BF FF
|
||||
39 00 00 40 00 00 09 EE FE EF C1 E0 00 C0 01 00
|
||||
15 00 00 40 00 00 02 D2 03
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 F8 01 //FUNCSTION SLECT
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 B3 50 //TE TEST MODE
|
||||
15 00 00 40 00 00 02 B5 03
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62 //OTP DON'T RELOAD
|
||||
39 00 00 40 00 00 04 FF 08 38 31
|
||||
15 00 00 40 00 00 02 D0 81
|
||||
15 00 00 40 00 00 02 A0 F3
|
||||
39 00 00 40 00 00 0B 90 02 03 04 06 07 02 03 04 06 07 //LUT_DBV
|
||||
39 00 00 40 00 00 07 91 04 44 55 03 09 0F //RATIO_Y_R
|
||||
39 00 00 40 00 00 07 92 04 44 55 03 09 0F //RATIO_Y_G
|
||||
39 00 00 40 00 00 07 93 04 44 55 03 09 0F //RATIO_Y_B
|
||||
//CTB DATA VALUE
|
||||
39 00 00 40 00 00 13 80 F0 8B 68 45 21 DF BB 98 75 B0 30 23 28 07 FD FC 02 A9
|
||||
39 00 00 40 00 00 13 81 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 EE F0 AC
|
||||
39 00 00 40 00 00 13 82 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 83 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 84 F0 69 4E 34 19 E7 CC B2 97 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 85 F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 86 F0 8B 68 45 21 DF BB 98 75 F0 22 21 18 00 FE EF F4 AC
|
||||
39 00 00 40 00 00 13 87 F0 7D 5E 3E 1E E2 C2 A2 83 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 88 F0 6A 4F 35 19 E7 CB B1 96 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 89 F0 5E 46 2F 17 E9 D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8A F0 66 4C 33 18 E8 CD B4 9A E0 22 21 20 00 00 F1 F0 AC
|
||||
39 00 00 40 00 00 13 8B F0 5E 46 2F 16 EA D1 BA A2 E0 22 21 20 00 00 F1 F0 AC
|
||||
//1 LINE AVERAGE
|
||||
39 00 00 40 00 00 09 8F 40 40 40 40 40 40 40 40
|
||||
39 00 00 40 00 00 09 8C 08 0D 0D 0C 09 05 03 00
|
||||
39 00 00 40 00 00 09 8D 0D 0F 0B 08 06 04 03 00
|
||||
39 00 00 40 00 00 07 8E 02 10 08 00 0F 70
|
||||
15 00 00 40 00 00 02 D0 80
|
||||
39 00 00 40 00 00 04 FF 08 38 05
|
||||
15 00 00 40 00 00 02 80 19
|
||||
39 00 00 40 00 00 0A D0 FF AF 56 3D 2D 2D 2D 2D FF //AOD EL INTERAL
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
//DSC 1.2 CONFIG
|
||||
39 00 00 40 00 00 04 FF 08 38 07
|
||||
39 00 00 40 00 00 02 8A 01
|
||||
39 00 00 40 00 00 03 8B 11 E0 //CHANGE PPS TABLE
|
||||
39 00 00 40 00 00 64 81 00 00 00 00 00 12 00 00 AB 30 80 0A DC 04 F0 00 14 02 78
|
||||
02 78 02 00 02 57 00 20 01 F8 00 08 00 0D 05 7A 04 4F 18 00
|
||||
10 E0 07 10 20 00 06 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 77
|
||||
79 7B 7D 7E 02 02 22 00 2A 40 2A BE 3A FC 3A FA 3A F8 3B 38
|
||||
3B 78 3B B6 4B B6 4B F4 4B F4 6C 34 84 74 74 00 00 00 00 00
|
||||
//OSC 138.6MHZ
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 00 00 02 F5 33
|
||||
15 00 00 40 00 00 02 F6 B7
|
||||
15 00 00 40 00 00 02 F7 98
|
||||
//MIPI=556.8MHz_1113.6Mbps OSC
|
||||
39 00 00 40 00 00 04 FF 08 38 22
|
||||
39 00 00 40 00 00 08 D0 00 DA 11 10 32 14 14
|
||||
39 00 00 40 00 00 0A DC 84 94 BB 00 20 C4 A1 CC 10
|
||||
15 00 00 40 00 00 02 DD 01 //TRIM_CMD enable
|
||||
15 00 00 40 00 00 02 DE F1
|
||||
15 00 00 40 00 00 02 DF 80
|
||||
39 00 00 40 00 00 09 E0 02 00 5F 21 00 3C 28 00 //P6_cmd key=3C
|
||||
//DCDC Setting
|
||||
39 00 00 40 00 00 04 FF 08 38 1F
|
||||
39 00 00 40 00 00 03 83 DB 7F
|
||||
39 00 00 40 00 00 03 84 2D 7F
|
||||
39 00 00 40 00 00 04 85 5F 79 07
|
||||
//ESD fixed H linse
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
39 00 00 40 00 00 02 D2 05
|
||||
39 00 00 40 00 00 02 D3 01
|
||||
//Fixed 4095 BL issue
|
||||
39 00 00 40 00 00 04 FF 08 38 49
|
||||
39 00 00 40 00 00 05 97 FE 0F FF 0F
|
||||
//EM_DUTY 92.5
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 01
|
||||
39 00 00 40 00 00 04 FF 08 38 64
|
||||
39 00 00 40 00 00 05 80 00 00 57 05
|
||||
39 00 00 40 00 00 05 81 00 00 57 05
|
||||
39 00 00 40 00 00 05 82 00 00 57 05
|
||||
39 00 00 40 00 00 05 83 00 00 57 05
|
||||
39 00 00 40 00 00 05 84 00 00 57 05
|
||||
39 00 00 40 00 00 05 85 00 00 57 05
|
||||
39 00 00 40 00 00 05 86 00 00 CB 05
|
||||
39 00 00 40 00 00 05 87 00 02 D7 1E
|
||||
39 00 00 40 00 00 05 88 00 03 31 1E
|
||||
39 00 00 40 00 00 05 89 00 03 B8 1E
|
||||
39 00 00 40 00 00 05 8A 00 04 03 1E
|
||||
39 00 00 40 00 00 05 8B 00 04 36 1E
|
||||
39 00 00 40 00 00 05 8C 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8D 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8E 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 8F 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 90 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 91 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 92 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 93 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 94 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 95 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 96 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 97 00 04 B0 1E
|
||||
39 00 00 40 00 00 05 98 00 04 B0 1E
|
||||
39 00 00 40 00 00 04 FF 08 38 23
|
||||
39 00 00 40 00 00 02 CB 00
|
||||
39 00 00 40 00 00 04 FF 08 38 4E
|
||||
//HRST
|
||||
39 00 00 40 00 00 04 FF 08 38 08
|
||||
15 00 00 40 00 00 02 C8 62
|
||||
39 00 00 40 00 00 04 FF 08 38 01
|
||||
39 00 00 40 00 00 0F 82 00 00 40 0A 00 15 08 08 00 0F 00 00 3E FC
|
||||
39 00 00 40 00 00 0F 83 00 00 C0 00 10 1C 08 18 00 00 00 00 3E FC
|
||||
15 00 00 40 00 00 02 94 09
|
||||
15 00 00 40 00 00 02 98 08
|
||||
39 00 00 40 00 00 04 FF 08 38 09
|
||||
39 00 00 40 00 00 03 8E 08 10
|
||||
15 00 00 40 00 00 02 B4 04
|
||||
15 00 00 40 00 00 02 EE 40
|
||||
39 00 00 40 00 00 04 FF 08 38 0A
|
||||
39 00 00 40 00 00 05 82 08 08 00 40
|
||||
39 00 00 40 00 00 05 83 08 18 00 C0
|
||||
39 00 00 40 00 00 05 90 08 08 00 40
|
||||
39 00 00 40 00 00 05 91 08 18 00 C0
|
||||
39 00 00 40 00 00 05 9E 20 20 00 C0
|
||||
39 00 00 40 00 00 05 9F 20 20 00 C0
|
||||
39 00 00 40 00 00 04 FF 08 38 0B
|
||||
39 00 00 40 00 00 09 80 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 82 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 84 00 00 00 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 86 00
|
||||
15 00 00 40 00 00 02 87 00
|
||||
15 00 00 40 00 00 02 88 00
|
||||
39 00 00 40 00 00 09 89 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8A 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 8B 00 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 09 81 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 83 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 09 85 20 20 20 20 20 20 20 20
|
||||
39 00 00 40 00 00 02 8C 10
|
||||
39 00 00 40 00 00 02 8D 03
|
||||
39 00 00 40 00 00 02 8E BF
|
||||
39 00 00 40 00 00 09 8F 33 BF BF 33 BF BF 03 BF
|
||||
39 00 00 40 00 00 09 90 00 05 05 00 05 05 00 05
|
||||
39 00 00 40 00 00 09 91 08 08 08 08 18 18 18 18
|
||||
39 00 00 40 00 00 06 93 08 00 00 00 10
|
||||
39 00 00 40 00 00 04 FF 08 38 0D
|
||||
15 00 00 40 00 00 02 CF 84
|
||||
15 00 00 40 00 00 02 D0 40
|
||||
15 00 00 40 00 00 02 D1 00
|
||||
15 00 00 40 00 00 02 D2 00
|
||||
15 00 00 40 00 00 02 D3 00
|
||||
15 00 00 40 00 00 02 D4 00
|
||||
15 00 00 40 00 00 02 D5 17
|
||||
15 00 00 40 00 00 02 D6 17
|
||||
15 00 00 40 00 00 02 D7 00
|
||||
15 00 00 40 00 00 02 D8 00
|
||||
|
||||
39 00 00 00 00 00 04 FF 08 38 00
|
||||
05 00 00 00 78 00 01 11
|
||||
//90HZ
|
||||
39 00 00 40 00 00 04 FF 08 38 2D
|
||||
15 00 00 40 00 00 02 80 00
|
||||
15 00 00 40 00 00 02 D0 04 //90HZ
|
||||
39 00 00 40 00 00 04 FF 08 38 02
|
||||
15 00 00 40 00 00 02 A6 00
|
||||
15 00 00 40 00 00 02 A7 00
|
||||
39 00 00 40 00 00 08 B0 00 00 80 00 00 00 00
|
||||
39 00 00 40 00 00 09 B1 FF FF FF 00 00 00 00 00
|
||||
39 00 00 40 00 00 08 C0 00 00 00 00 00 00 00
|
||||
39 00 00 40 00 00 06 C1 00 00 00 00 00
|
||||
15 00 00 40 00 00 02 B6 B0
|
||||
15 00 00 40 00 00 02 B8 00
|
||||
39 00 00 40 00 00 04 FF 08 38 20
|
||||
15 00 00 40 04 00 02 BC 52
|
||||
15 00 00 40 04 00 02 BD 34
|
||||
15 00 00 40 00 00 02 BE 56
|
||||
39 00 00 40 00 00 04 FF 08 38 00
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-on-evt-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-dvt-command-state = "dsi_lp_mode";
|
||||
2736
qcom/display/oplus/panel/dsi-panel-AA551-P-3-A0004-dsc-cmd.dtsi
Normal file
2736
qcom/display/oplus/panel/dsi-panel-AA551-P-3-A0004-dsc-cmd.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
1220
qcom/display/oplus/panel/dsi-panel-AC052-P-1-A0002-dsc-cmd.dtsi
Normal file
1220
qcom/display/oplus/panel/dsi-panel-AC052-P-1-A0002-dsc-cmd.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
1304
qcom/display/oplus/panel/dsi-panel-AC052-P-3-A0003-dsc-cmd-pvt.dtsi
Normal file
1304
qcom/display/oplus/panel/dsi-panel-AC052-P-3-A0003-dsc-cmd-pvt.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
1279
qcom/display/oplus/panel/dsi-panel-AC052-P-3-A0003-dsc-cmd.dtsi
Normal file
1279
qcom/display/oplus/panel/dsi-panel-AC052-P-3-A0003-dsc-cmd.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
1353
qcom/display/oplus/panel/dsi-panel-AC052-S-3-A0001-dsc-cmd.dtsi
Normal file
1353
qcom/display/oplus/panel/dsi-panel-AC052-S-3-A0001-dsc-cmd.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -53,8 +53,8 @@
|
||||
oplus,mdss-dsi-panel-status-match-modes = <0x00000000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@fhd_sa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-iris-copy-SA-FHD-120fps-timing-switch.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
@@ -69,20 +69,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -270,7 +261,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-on-command = [
|
||||
/* SDC Auto On */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -281,7 +272,7 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -292,28 +283,63 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 17
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -322,8 +348,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
timing@fhd_sa_90 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-iris-copy-SA-FHD-90fps-timing-switch.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
@@ -338,21 +364,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 04 37
|
||||
@@ -529,20 +540,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -551,8 +553,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
timing@fhd_sa_60 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-iris-copy-SM-FHD-60fps-timing-switch.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-timing-default;
|
||||
@@ -568,11 +570,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC MFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 04 37
|
||||
@@ -757,30 +754,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -789,8 +767,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@fhd_oa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-iris-copy-OA-FHD-120fps-timing-switch.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
@@ -805,18 +783,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -1011,89 +980,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 13
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 09
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 07
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 04
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 03
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1102,8 +1013,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
timing@wqhd_sa_60 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-iris-copy-SM-QHD-60fps-timing-switch.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
@@ -1118,11 +1029,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC MFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 05 9F
|
||||
@@ -1292,30 +1198,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1324,8 +1211,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
timing@wqhd_sa_90 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-iris-copy-SA-QHD-90fps-timing-switch.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
@@ -1340,21 +1227,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 05 9F
|
||||
@@ -1516,20 +1388,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1538,8 +1401,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@wqhd_sa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-iris-copy-SA-QHD-120fps-timing-switch.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
@@ -1554,20 +1417,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -1738,7 +1592,7 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-on-command = [
|
||||
/* SDC Auto On */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -1749,7 +1603,7 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -1760,28 +1614,63 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 17
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1790,8 +1679,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@wqhd_oa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-iris-copy-OA-QHD-120fps-timing-switch.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
@@ -1806,18 +1695,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -1997,89 +1877,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 13
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 09
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 07
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 04
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 03
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2095,8 +1917,6 @@
|
||||
/* hardware config */
|
||||
qcom,panel-supply-entries = <&oplus_salami_dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,dynamic-te-gpio = <&tlmm 177 0>;
|
||||
qcom,vsync-switch-gpio = <&tlmm 57 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
qcom,platform-panel-vout-gpio = <&tlmm 90 0>;
|
||||
//qcom,platform-panel-vddr-aod-en-gpio = <&tlmm 180 0>;
|
||||
@@ -2145,17 +1965,12 @@
|
||||
oplus,enhance_mipi_strength;
|
||||
|
||||
/* adfr config */
|
||||
/* just for qsync enable*/
|
||||
oplus,adfr-config = <0xDF>;
|
||||
oplus,adfr-mux-vsync-switch-gpio = <&tlmm 57 0>;
|
||||
oplus,adfr-test-te-gpio = <&tlmm 177 0>;
|
||||
/* just for qsync enable */
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <24>;
|
||||
/*
|
||||
** 0st bit: adfr global on/off
|
||||
** 1st bit: fakeframe on/off
|
||||
** 2st bit: switch on/off
|
||||
** 3rd bit: 0:double-TE switch 1:external TE/TP switch
|
||||
** 4rd bit: idle mode on/off
|
||||
*/
|
||||
oplus,adfr-config = <31>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
@@ -2168,48 +1983,46 @@
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
/delete-node/ timing@fhd_oplus_120;
|
||||
/delete-node/ timing@wqhd_oplus_120;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -53,8 +53,8 @@
|
||||
oplus,mdss-dsi-panel-status-match-modes = <0x00000000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@fhd_sa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
@@ -68,20 +68,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -269,7 +260,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-on-command = [
|
||||
/* SDC Auto On */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -280,7 +271,7 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -291,28 +282,63 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 17
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -321,8 +347,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
timing@fhd_sa_90 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
@@ -336,21 +362,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 04 37
|
||||
@@ -527,20 +538,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -549,8 +551,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
timing@fhd_sa_60 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-timing-default;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
@@ -565,11 +567,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC MFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 04 37
|
||||
@@ -754,30 +751,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -786,8 +764,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@fhd_oa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
@@ -801,18 +779,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -1007,89 +976,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 13
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 09
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 07
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 04
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 03
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1098,8 +1009,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
timing@wqhd_sa_60 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
@@ -1113,11 +1024,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC MFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 05 9F
|
||||
@@ -1287,30 +1193,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1319,8 +1206,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
timing@wqhd_sa_90 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
@@ -1334,21 +1221,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 05 9F
|
||||
@@ -1510,20 +1382,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1532,8 +1395,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@wqhd_sa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
@@ -1547,20 +1410,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -1731,7 +1585,7 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-on-command = [
|
||||
/* SDC Auto On */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -1742,7 +1596,7 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -1753,28 +1607,63 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 17
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1783,8 +1672,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
#include "dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@wqhd_oa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
@@ -1798,18 +1687,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -1989,89 +1869,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 13
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 09
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 07
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 04
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 03
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2087,7 +1909,6 @@
|
||||
/* hardware config */
|
||||
qcom,panel-supply-entries = <&oplus_salami_dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,dynamic-te-gpio = <&tlmm 177 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
qcom,platform-panel-vout-gpio = <&tlmm 90 0>;
|
||||
//qcom,platform-panel-vddr-aod-en-gpio = <&tlmm 180 0>;
|
||||
@@ -2136,17 +1957,11 @@
|
||||
oplus,enhance_mipi_strength;
|
||||
|
||||
/* adfr config */
|
||||
/* just for qsync enable*/
|
||||
oplus,adfr-config = <0xD7>;
|
||||
oplus,adfr-test-te-gpio = <&tlmm 177 0>;
|
||||
/* just for qsync enable */
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <24>;
|
||||
/*
|
||||
** 0st bit: adfr global on/off
|
||||
** 1st bit: fakeframe on/off
|
||||
** 2st bit: switch on/off
|
||||
** 3rd bit: 0:double-TE switch 1:external TE/TP switch
|
||||
** 4rd bit: idle mode on/off
|
||||
*/
|
||||
oplus,adfr-config = <23>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
@@ -2159,48 +1974,46 @@
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
/delete-node/ timing@fhd_oplus_120;
|
||||
/delete-node/ timing@wqhd_oplus_120;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -53,8 +53,8 @@
|
||||
oplus,mdss-dsi-panel-status-match-modes = <0x00000000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@fhd_sa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-iris-copy-SA-FHD-120fps-timing-switch.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
@@ -69,20 +69,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -307,7 +298,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-on-command = [
|
||||
/* SDC Auto On */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -318,7 +309,7 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -329,28 +320,63 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 17
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -359,8 +385,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
timing@fhd_sa_90 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-iris-copy-SA-FHD-90fps-timing-switch.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
@@ -375,21 +401,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 04 37
|
||||
@@ -597,20 +608,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -619,8 +621,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
timing@fhd_sa_60 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-iris-copy-SM-FHD-60fps-timing-switch.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-timing-default;
|
||||
@@ -636,11 +638,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC MFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 04 37
|
||||
@@ -862,30 +859,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -894,8 +872,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@fhd_oa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-iris-copy-OA-FHD-120fps-timing-switch.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
@@ -910,18 +888,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -1153,89 +1122,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 13
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 09
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 07
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 04
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 03
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1244,8 +1155,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
timing@wqhd_sa_60 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-iris-copy-SM-QHD-60fps-timing-switch.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
@@ -1260,11 +1171,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC MFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 05 9F
|
||||
@@ -1470,30 +1376,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1502,8 +1389,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
timing@wqhd_sa_90 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-iris-copy-SA-QHD-90fps-timing-switch.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
@@ -1518,21 +1405,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 05 9F
|
||||
@@ -1724,20 +1596,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1746,8 +1609,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@wqhd_sa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-iris-copy-SA-QHD-120fps-timing-switch.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
@@ -1762,20 +1625,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -1982,7 +1836,7 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-on-command = [
|
||||
/* SDC Auto On */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -1993,7 +1847,7 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -2004,28 +1858,63 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 17
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2034,8 +1923,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@wqhd_oa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
#include "../pxlw-salami/dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-iris-copy-OA-QHD-120fps-timing-switch.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
@@ -2050,18 +1939,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -2277,89 +2157,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 13
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 09
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 07
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 04
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 03
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2375,8 +2197,6 @@
|
||||
/* hardware config */
|
||||
qcom,panel-supply-entries = <&oplus_salami_dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,dynamic-te-gpio = <&tlmm 177 0>;
|
||||
qcom,vsync-switch-gpio = <&tlmm 57 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
qcom,platform-panel-vout-gpio = <&tlmm 90 0>;
|
||||
//qcom,platform-panel-vddr-aod-en-gpio = <&tlmm 180 0>;
|
||||
@@ -2425,17 +2245,12 @@
|
||||
oplus,enhance_mipi_strength;
|
||||
|
||||
/* adfr config */
|
||||
/* just for qsync enable*/
|
||||
oplus,adfr-config = <0xDF>;
|
||||
oplus,adfr-mux-vsync-switch-gpio = <&tlmm 57 0>;
|
||||
oplus,adfr-test-te-gpio = <&tlmm 177 0>;
|
||||
/* just for qsync enable */
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <24>;
|
||||
/*
|
||||
** 0st bit: adfr global on/off
|
||||
** 1st bit: fakeframe on/off
|
||||
** 2st bit: switch on/off
|
||||
** 3rd bit: 0:double-TE switch 1:external TE/TP switch
|
||||
** 4rd bit: idle mode on/off
|
||||
*/
|
||||
oplus,adfr-config = <31>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
@@ -2448,48 +2263,46 @@
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
/delete-node/ timing@fhd_oplus_120;
|
||||
/delete-node/ timing@wqhd_oplus_120;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -53,8 +53,8 @@
|
||||
oplus,mdss-dsi-panel-status-match-modes = <0x00000000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@fhd_sa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
@@ -68,20 +68,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -306,7 +297,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-on-command = [
|
||||
/* SDC Auto On */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -317,7 +308,7 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -328,28 +319,63 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 17
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -358,8 +384,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
timing@fhd_sa_90 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
@@ -373,21 +399,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 04 37
|
||||
@@ -595,20 +606,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -617,8 +619,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
timing@fhd_sa_60 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-timing-default;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
@@ -633,11 +635,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC MFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 04 37
|
||||
@@ -859,30 +856,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -891,8 +869,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@fhd_oa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
@@ -906,18 +884,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -1149,89 +1118,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 13
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 09
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 07
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 04
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 03
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
|
||||
//qcom,panel-roi-alignment=<1080 36 1080 36 1080 36>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1240,8 +1151,8 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
timing@wqhd_sa_60 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
@@ -1255,11 +1166,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC MFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 05 9F
|
||||
@@ -1465,30 +1371,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1497,8 +1384,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
timing@wqhd_sa_90 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
@@ -1512,21 +1399,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
39 00 00 40 00 00 05 2A 00 00 05 9F
|
||||
@@ -1718,20 +1590,11 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1740,8 +1603,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@wqhd_sa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
@@ -1755,20 +1618,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-panel-vsync-source = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
qcom,mdss-dsi-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -1975,7 +1829,7 @@
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-on-command = [
|
||||
/* SDC Auto On */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -1986,7 +1840,7 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
@@ -1997,28 +1851,63 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 17
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2027,8 +1916,8 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
#include "dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
timing@wqhd_oa_120 {
|
||||
#include "dsi-panel-samsung-amb670yf0x-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
@@ -2042,18 +1931,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* CASET/PASET Setting */
|
||||
@@ -2269,89 +2149,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 13
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 09
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 07
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 04
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 03
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
05 00 00 00 11 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
|
||||
//qcom,panel-roi-alignment=<1440 24 1440 24 1440 24>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2367,7 +2189,6 @@
|
||||
/* hardware config */
|
||||
qcom,panel-supply-entries = <&oplus_salami_dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,dynamic-te-gpio = <&tlmm 177 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
qcom,platform-panel-vout-gpio = <&tlmm 90 0>;
|
||||
//qcom,platform-panel-vddr-aod-en-gpio = <&tlmm 180 0>;
|
||||
@@ -2416,17 +2237,11 @@
|
||||
oplus,enhance_mipi_strength;
|
||||
|
||||
/* adfr config */
|
||||
/* just for qsync enable*/
|
||||
oplus,adfr-config = <0xD7>;
|
||||
oplus,adfr-test-te-gpio = <&tlmm 177 0>;
|
||||
/* just for qsync enable */
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <24>;
|
||||
/*
|
||||
** 0st bit: adfr global on/off
|
||||
** 1st bit: fakeframe on/off
|
||||
** 2st bit: switch on/off
|
||||
** 3rd bit: 0:double-TE switch 1:external TE/TP switch
|
||||
** 4rd bit: idle mode on/off
|
||||
*/
|
||||
oplus,adfr-config = <23>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
@@ -2439,48 +2254,46 @@
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
/delete-node/ timing@fhd_oplus_120;
|
||||
/delete-node/ timing@wqhd_oplus_120;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -0,0 +1,235 @@
|
||||
/***************************************************************
|
||||
** Copyright (C), 2022, OPLUS Mobile Comm Corp., Ltd
|
||||
**
|
||||
** Description : 120fps common config
|
||||
** Version : NA
|
||||
** Date : 2022/04/08
|
||||
** Author : Oplus Display
|
||||
******************************************************************/
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-need-to-separate-backlight;
|
||||
oplus,ofp-hbm-on-period = <2>;
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
/* Display Off */
|
||||
05 00 00 00 15 00 02 28 00
|
||||
/* Sleep In */
|
||||
05 00 00 00 65 00 02 10 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-hbm-enter-switch-command = [
|
||||
/* HBM Mode ON */
|
||||
15 00 00 40 00 00 02 53 E0
|
||||
39 00 00 00 00 00 03 51 0D D2
|
||||
];
|
||||
qcom,mdss-dsi-hbm-exit-switch-command = [
|
||||
/* HBM Mode OFF */
|
||||
15 00 00 40 00 00 02 53 20
|
||||
39 00 00 00 00 00 03 51 07 FF
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-pre-switch-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A /* Level2 key Access Enable */
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00 /* SDC auto mode min == max */
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-hbm-on-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 00 08 00 03 F0 A5 A5
|
||||
/* HBM Mode ON */
|
||||
15 00 00 40 00 00 02 53 E0
|
||||
39 00 00 00 08 00 03 51 0E FF
|
||||
/* AID Cycle + AOR Change Setting */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
39 00 00 40 00 00 04 B0 02 B9 65
|
||||
39 00 00 40 00 00 07 65 00 AC 00 AC 00 AC
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hbm-off-command = [
|
||||
/* HBM Mode OFF */
|
||||
15 00 00 40 00 00 02 53 28
|
||||
39 00 00 00 08 00 03 51 06 9F
|
||||
/* AID Cycle + AOR Change Setting */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
39 00 00 40 00 00 04 B0 02 B9 65
|
||||
39 00 00 40 00 00 07 65 01 5E 01 5E 01 5E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-lp1-command = [
|
||||
05 00 00 00 09 00 01 28
|
||||
/* AOD Mode ON */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 24
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-nolp-command = [
|
||||
05 00 00 00 09 00 01 28
|
||||
/* AOD Mode OFF */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 28
|
||||
39 00 00 40 00 00 03 51 00 00
|
||||
39 00 00 00 09 00 03 F0 A5 A5
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-aod-high-mode-command = [
|
||||
/* AOD High Mode, 50nit */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 24
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-aod-low-mode-command = [
|
||||
/* AOD Low Mode 10nit */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 27
|
||||
39 00 00 40 00 00 04 B0 03 55 65
|
||||
39 00 00 40 00 00 03 65 14 40
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-ultra-low-power-aod-on-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 60
|
||||
15 00 00 40 00 00 02 60 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-ultra-low-power-aod-off-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 60
|
||||
15 00 00 40 00 00 02 60 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 24 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-dly-on-command = [
|
||||
];
|
||||
qcom,mdss-dsi-dly-off-command = [
|
||||
];
|
||||
qcom,mdss-dsi-aor-restore-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-loading-effect-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 02 B6 1D
|
||||
15 00 00 40 00 00 02 1D 27
|
||||
39 00 00 40 00 00 04 B0 02 B7 1D
|
||||
39 00 00 40 00 00 04 1D F9 03 6C
|
||||
39 00 00 40 00 00 04 B0 02 C2 1D
|
||||
39 00 00 40 00 00 0A 1D 43 4C 82 0A 0B 09 27 2A 24
|
||||
39 00 00 40 00 00 04 B0 02 CC 1D
|
||||
39 00 00 40 00 00 09 1D 38 30 3E 43 39 41 46 3C
|
||||
39 00 00 40 00 00 04 B0 01 A5 1F
|
||||
39 00 00 40 00 00 09 1F E2 00 00 00 92 2C 6A 80
|
||||
39 00 00 40 00 00 04 B0 01 AD 1F
|
||||
39 00 00 40 00 00 07 1F 00 00 00 00 FF 90
|
||||
39 00 00 40 00 00 04 B0 01 B5 1F
|
||||
39 00 00 40 00 00 04 1F 49 00 10
|
||||
39 00 00 40 00 00 04 B0 01 BA 1F
|
||||
39 00 00 40 00 00 06 1F 05 FF 10 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C1 1F
|
||||
39 00 00 40 00 00 05 1F 00 00 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C5 1F
|
||||
39 00 00 40 00 00 05 1F 03 FF 21 3C
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-loading-effect-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 02 B6 1D
|
||||
15 00 00 40 00 00 02 1D 27
|
||||
39 00 00 40 00 00 04 B0 02 B7 1D
|
||||
39 00 00 40 00 00 04 1D F9 03 6C
|
||||
39 00 00 40 00 00 04 B0 02 C2 1D
|
||||
39 00 00 40 00 00 0A 1D 43 4C 82 0A 0B 09 27 2A 24
|
||||
39 00 00 40 00 00 04 B0 02 CC 1D
|
||||
39 00 00 40 00 00 09 1D 38 30 3E 43 39 41 46 3C
|
||||
39 00 00 40 00 00 04 B0 01 A5 1F
|
||||
39 00 00 40 00 00 09 1F E2 00 00 00 92 2C 6A 80
|
||||
39 00 00 40 00 00 04 B0 01 AD 1F
|
||||
39 00 00 40 00 00 07 1F 7D 64 7E 65 FF 90
|
||||
39 00 00 40 00 00 04 B0 01 B5 1F
|
||||
39 00 00 40 00 00 04 1F 49 00 10
|
||||
39 00 00 40 00 00 04 B0 01 BA 1F
|
||||
39 00 00 40 00 00 06 1F 05 FF 10 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C1 1F
|
||||
39 00 00 40 00 00 05 1F 00 00 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C5 1F
|
||||
39 00 00 40 00 00 05 1F 03 FF 21 3C
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-loading-effect-off-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 02 B6 1D
|
||||
15 00 00 40 00 00 02 1D 07
|
||||
39 00 00 40 00 00 04 B0 02 B7 1D
|
||||
39 00 00 40 00 00 04 1D F9 03 6C
|
||||
39 00 00 40 00 00 04 B0 02 C2 1D
|
||||
39 00 00 40 00 00 0A 1D 43 4C 82 0A 0B 09 27 2A 24
|
||||
39 00 00 40 00 00 04 B0 02 CC 1D
|
||||
39 00 00 40 00 00 09 1D 38 30 3E 43 39 41 46 3C
|
||||
39 00 00 40 00 00 04 B0 01 A5 1F
|
||||
39 00 00 40 00 00 09 1F E2 00 00 00 92 2C 6A 80
|
||||
39 00 00 40 00 00 04 B0 01 AD 1F
|
||||
39 00 00 40 00 00 07 1F 61 1A 64 1D FF 9F
|
||||
39 00 00 40 00 00 04 B0 01 B5 1F
|
||||
39 00 00 40 00 00 04 1F 49 00 10
|
||||
39 00 00 40 00 00 04 B0 01 BA 1F
|
||||
39 00 00 40 00 00 06 1F 05 FF 10 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C1 1F
|
||||
39 00 00 40 00 00 05 1F 00 00 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C5 1F
|
||||
39 00 00 40 00 00 05 1F 03 FF 21 3C
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-panel-read-register-open-command = [
|
||||
39 00 00 00 00 00 03 F0 5A 5A
|
||||
];
|
||||
qcom,mdss-dsi-panel-id1-command = [
|
||||
06 00 00 00 00 00 01 E9
|
||||
];
|
||||
qcom,mdss-dsi-panel-read-register-close-command = [
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-enter-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-exit-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-pre-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-lp1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-nolp-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aod-high-mode-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aod-low-mode-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-ultra-low-power-aod-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-ultra-low-power-aod-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-dly-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-dly-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aor-restore-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-loading-effect-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-loading-effect-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-loading-effect-off-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-scr-version = <1>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
@@ -0,0 +1,301 @@
|
||||
/***************************************************************
|
||||
** Copyright (C), 2022, OPLUS Mobile Comm Corp., Ltd
|
||||
**
|
||||
** Description : 60fps common config
|
||||
** Version : NA
|
||||
** Date : 2022/04/08
|
||||
** Author : Oplus Display
|
||||
******************************************************************/
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-min-fps-mapping-table = <60 30 20 10 5 1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-need-to-separate-backlight;
|
||||
oplus,ofp-hbm-on-period = <2>;
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
/* Display Off */
|
||||
05 00 00 00 15 00 02 28 00
|
||||
/* Sleep In */
|
||||
05 00 00 00 65 00 02 10 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-hbm-enter-switch-command = [
|
||||
/* HBM Mode ON */
|
||||
15 00 00 40 00 00 02 53 E0
|
||||
39 00 00 00 00 00 03 51 0D D2
|
||||
];
|
||||
qcom,mdss-dsi-hbm-exit-switch-command = [
|
||||
/* HBM Mode OFF */
|
||||
15 00 00 40 00 00 02 53 20
|
||||
39 00 00 00 00 00 03 51 07 FF
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 03
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0B
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 17
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-pre-switch-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A /* Level2 key Access Enable */
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00 /* SDC auto mode min == max */
|
||||
15 00 00 40 00 00 02 BD 23 /* 21 : Manual On 23 Auto On */
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-hbm-on-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 00 0A 00 03 F0 A5 A5
|
||||
/* HBM Mode ON */
|
||||
15 00 00 40 00 00 02 53 E0
|
||||
39 00 00 00 00 00 03 51 0E FF
|
||||
/* AID Cycle + AOR Change Setting */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
39 00 00 40 00 00 04 B0 02 B9 65
|
||||
39 00 00 40 00 00 07 65 00 AC 00 AC 00 AC
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hbm-off-command = [
|
||||
15 00 00 00 0F 00 02 53 E0
|
||||
/* HBM Mode OFF */
|
||||
15 00 00 40 00 00 02 53 28
|
||||
39 00 00 00 00 00 03 51 06 9F
|
||||
/* AID Cycle + AOR Change Setting */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
39 00 00 40 00 00 04 B0 02 B9 65
|
||||
39 00 00 40 00 00 07 65 01 5E 01 5E 01 5E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-lp1-command = [
|
||||
05 00 00 00 09 00 01 28
|
||||
/* AOD Mode ON */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 24
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-nolp-command = [
|
||||
05 00 00 00 09 00 01 28
|
||||
/* AOD Mode OFF */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 28
|
||||
39 00 00 40 00 00 03 51 00 00
|
||||
39 00 00 00 09 00 03 F0 A5 A5
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-aod-high-mode-command = [
|
||||
/* AOD High Mode, 50nit */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 24
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-aod-low-mode-command = [
|
||||
/* AOD Low Mode 10nit */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 27
|
||||
39 00 00 40 00 00 04 B0 03 55 65
|
||||
39 00 00 40 00 00 03 65 14 40
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-ultra-low-power-aod-on-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 60
|
||||
15 00 00 40 00 00 02 60 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-ultra-low-power-aod-off-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 60
|
||||
15 00 00 40 00 00 02 60 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 24 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-dly-on-command = [
|
||||
];
|
||||
qcom,mdss-dsi-dly-off-command = [
|
||||
];
|
||||
qcom,mdss-dsi-aor-restore-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-loading-effect-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 02 B6 1D
|
||||
15 00 00 40 00 00 02 1D 27
|
||||
39 00 00 40 00 00 04 B0 02 B7 1D
|
||||
39 00 00 40 00 00 04 1D F9 03 6C
|
||||
39 00 00 40 00 00 04 B0 02 C2 1D
|
||||
39 00 00 40 00 00 0A 1D 43 4C 82 0A 0B 09 27 2A 24
|
||||
39 00 00 40 00 00 04 B0 02 CC 1D
|
||||
39 00 00 40 00 00 09 1D 38 30 3E 43 39 41 46 3C
|
||||
39 00 00 40 00 00 04 B0 01 A5 1F
|
||||
39 00 00 40 00 00 09 1F E2 00 00 00 92 2C 6A 80
|
||||
39 00 00 40 00 00 04 B0 01 AD 1F
|
||||
39 00 00 40 00 00 07 1F 00 00 00 00 FF 90
|
||||
39 00 00 40 00 00 04 B0 01 B5 1F
|
||||
39 00 00 40 00 00 04 1F 49 00 10
|
||||
39 00 00 40 00 00 04 B0 01 BA 1F
|
||||
39 00 00 40 00 00 06 1F 05 FF 10 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C1 1F
|
||||
39 00 00 40 00 00 05 1F 00 00 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C5 1F
|
||||
39 00 00 40 00 00 05 1F 03 FF 21 3C
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-loading-effect-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 02 B6 1D
|
||||
15 00 00 40 00 00 02 1D 27
|
||||
39 00 00 40 00 00 04 B0 02 B7 1D
|
||||
39 00 00 40 00 00 04 1D F9 03 6C
|
||||
39 00 00 40 00 00 04 B0 02 C2 1D
|
||||
39 00 00 40 00 00 0A 1D 43 4C 82 0A 0B 09 27 2A 24
|
||||
39 00 00 40 00 00 04 B0 02 CC 1D
|
||||
39 00 00 40 00 00 09 1D 38 30 3E 43 39 41 46 3C
|
||||
39 00 00 40 00 00 04 B0 01 A5 1F
|
||||
39 00 00 40 00 00 09 1F E2 00 00 00 92 2C 6A 80
|
||||
39 00 00 40 00 00 04 B0 01 AD 1F
|
||||
39 00 00 40 00 00 07 1F 7D 64 7E 65 FF 90
|
||||
39 00 00 40 00 00 04 B0 01 B5 1F
|
||||
39 00 00 40 00 00 04 1F 49 00 10
|
||||
39 00 00 40 00 00 04 B0 01 BA 1F
|
||||
39 00 00 40 00 00 06 1F 05 FF 10 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C1 1F
|
||||
39 00 00 40 00 00 05 1F 00 00 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C5 1F
|
||||
39 00 00 40 00 00 05 1F 03 FF 21 3C
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-loading-effect-off-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 02 B6 1D
|
||||
15 00 00 40 00 00 02 1D 07
|
||||
39 00 00 40 00 00 04 B0 02 B7 1D
|
||||
39 00 00 40 00 00 04 1D F9 03 6C
|
||||
39 00 00 40 00 00 04 B0 02 C2 1D
|
||||
39 00 00 40 00 00 0A 1D 43 4C 82 0A 0B 09 27 2A 24
|
||||
39 00 00 40 00 00 04 B0 02 CC 1D
|
||||
39 00 00 40 00 00 09 1D 38 30 3E 43 39 41 46 3C
|
||||
39 00 00 40 00 00 04 B0 01 A5 1F
|
||||
39 00 00 40 00 00 09 1F E2 00 00 00 92 2C 6A 80
|
||||
39 00 00 40 00 00 04 B0 01 AD 1F
|
||||
39 00 00 40 00 00 07 1F 61 1A 64 1D FF 9F
|
||||
39 00 00 40 00 00 04 B0 01 B5 1F
|
||||
39 00 00 40 00 00 04 1F 49 00 10
|
||||
39 00 00 40 00 00 04 B0 01 BA 1F
|
||||
39 00 00 40 00 00 06 1F 05 FF 10 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C1 1F
|
||||
39 00 00 40 00 00 05 1F 00 00 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C5 1F
|
||||
39 00 00 40 00 00 05 1F 03 FF 21 3C
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-panel-read-register-open-command = [
|
||||
39 00 00 00 00 00 03 F0 5A 5A
|
||||
];
|
||||
qcom,mdss-dsi-panel-id1-command = [
|
||||
06 00 00 00 00 00 01 E9
|
||||
];
|
||||
qcom,mdss-dsi-panel-read-register-close-command = [
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-enter-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-exit-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-pre-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-lp1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-nolp-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aod-high-mode-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aod-low-mode-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-ultra-low-power-aod-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-ultra-low-power-aod-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-dly-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-dly-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aor-restore-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-loading-effect-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-loading-effect-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-loading-effect-off-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-scr-version = <1>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
@@ -0,0 +1,248 @@
|
||||
/***************************************************************
|
||||
** Copyright (C), 2022, OPLUS Mobile Comm Corp., Ltd
|
||||
**
|
||||
** Description : 90fps common config
|
||||
** Version : NA
|
||||
** Date : 2022/04/08
|
||||
** Author : Oplus Display
|
||||
******************************************************************/
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-need-to-separate-backlight;
|
||||
oplus,ofp-hbm-on-period = <2>;
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
/* Display Off */
|
||||
05 00 00 00 15 00 02 28 00
|
||||
/* Sleep In */
|
||||
05 00 00 00 65 00 02 10 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-hbm-enter-switch-command = [
|
||||
/* HBM Mode ON */
|
||||
15 00 00 40 00 00 02 53 E0
|
||||
39 00 00 00 00 00 03 51 0D D2
|
||||
];
|
||||
qcom,mdss-dsi-hbm-exit-switch-command = [
|
||||
/* HBM Mode OFF */
|
||||
15 00 00 40 00 00 02 53 20
|
||||
39 00 00 00 00 00 03 51 07 FF
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
qcom,mdss-dsi-adfr-pre-switch-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A /* Level2 key Access Enable */
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00 /* SDC auto mode min == max */
|
||||
15 00 00 40 00 00 02 BD 23 /* 21 : Manual On 23 Auto On */
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-hbm-on-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 00 0B 00 03 F0 A5 A5
|
||||
/* HBM Mode ON */
|
||||
15 00 00 40 00 00 02 53 E0
|
||||
39 00 00 00 0B 00 03 51 0E FF
|
||||
/* AID Cycle + AOR Change Setting */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
39 00 00 40 00 00 04 B0 02 B9 65
|
||||
39 00 00 40 00 00 07 65 00 AC 00 AC 00 AC
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hbm-off-command = [
|
||||
/* HBM Mode OFF */
|
||||
15 00 00 40 00 00 02 53 28
|
||||
39 00 00 00 0B 00 03 51 06 9F
|
||||
/* AID Cycle + AOR Change Setting */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
39 00 00 40 00 00 04 B0 02 B9 65
|
||||
39 00 00 40 00 00 07 65 01 5E 01 5E 01 5E
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-lp1-command = [
|
||||
05 00 00 00 09 00 01 28
|
||||
/* AOD Mode ON */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 24
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-nolp-command = [
|
||||
05 00 00 00 09 00 01 28
|
||||
/* AOD Mode OFF */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 28
|
||||
39 00 00 40 00 00 03 51 00 00
|
||||
39 00 00 00 09 00 03 F0 A5 A5
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-aod-high-mode-command = [
|
||||
/* AOD High Mode, 50nit */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 24
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-aod-low-mode-command = [
|
||||
/* AOD Low Mode 10nit */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 53 27
|
||||
39 00 00 40 00 00 04 B0 03 55 65
|
||||
39 00 00 40 00 00 03 65 14 40
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-ultra-low-power-aod-on-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 60
|
||||
15 00 00 40 00 00 02 60 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-ultra-low-power-aod-off-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 01 60
|
||||
15 00 00 40 00 00 02 60 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 24 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-dly-on-command = [
|
||||
];
|
||||
qcom,mdss-dsi-dly-off-command = [
|
||||
];
|
||||
qcom,mdss-dsi-aor-restore-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-loading-effect-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 02 B6 1D
|
||||
15 00 00 40 00 00 02 1D 27
|
||||
39 00 00 40 00 00 04 B0 02 B7 1D
|
||||
39 00 00 40 00 00 04 1D F9 03 6C
|
||||
39 00 00 40 00 00 04 B0 02 C2 1D
|
||||
39 00 00 40 00 00 0A 1D 43 4C 82 0A 0B 09 27 2A 24
|
||||
39 00 00 40 00 00 04 B0 02 CC 1D
|
||||
39 00 00 40 00 00 09 1D 38 30 3E 43 39 41 46 3C
|
||||
39 00 00 40 00 00 04 B0 01 A5 1F
|
||||
39 00 00 40 00 00 09 1F E2 00 00 00 92 2C 6A 80
|
||||
39 00 00 40 00 00 04 B0 01 AD 1F
|
||||
39 00 00 40 00 00 07 1F 00 00 00 00 FF 90
|
||||
39 00 00 40 00 00 04 B0 01 B5 1F
|
||||
39 00 00 40 00 00 04 1F 49 00 10
|
||||
39 00 00 40 00 00 04 B0 01 BA 1F
|
||||
39 00 00 40 00 00 06 1F 05 FF 10 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C1 1F
|
||||
39 00 00 40 00 00 05 1F 00 00 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C5 1F
|
||||
39 00 00 40 00 00 05 1F 03 FF 21 3C
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-loading-effect-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 02 B6 1D
|
||||
15 00 00 40 00 00 02 1D 27
|
||||
39 00 00 40 00 00 04 B0 02 B7 1D
|
||||
39 00 00 40 00 00 04 1D F9 03 6C
|
||||
39 00 00 40 00 00 04 B0 02 C2 1D
|
||||
39 00 00 40 00 00 0A 1D 43 4C 82 0A 0B 09 27 2A 24
|
||||
39 00 00 40 00 00 04 B0 02 CC 1D
|
||||
39 00 00 40 00 00 09 1D 38 30 3E 43 39 41 46 3C
|
||||
39 00 00 40 00 00 04 B0 01 A5 1F
|
||||
39 00 00 40 00 00 09 1F E2 00 00 00 92 2C 6A 80
|
||||
39 00 00 40 00 00 04 B0 01 AD 1F
|
||||
39 00 00 40 00 00 07 1F 7D 64 7E 65 FF 90
|
||||
39 00 00 40 00 00 04 B0 01 B5 1F
|
||||
39 00 00 40 00 00 04 1F 49 00 10
|
||||
39 00 00 40 00 00 04 B0 01 BA 1F
|
||||
39 00 00 40 00 00 06 1F 05 FF 10 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C1 1F
|
||||
39 00 00 40 00 00 05 1F 00 00 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C5 1F
|
||||
39 00 00 40 00 00 05 1F 03 FF 21 3C
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-loading-effect-off-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 02 B6 1D
|
||||
15 00 00 40 00 00 02 1D 07
|
||||
39 00 00 40 00 00 04 B0 02 B7 1D
|
||||
39 00 00 40 00 00 04 1D F9 03 6C
|
||||
39 00 00 40 00 00 04 B0 02 C2 1D
|
||||
39 00 00 40 00 00 0A 1D 43 4C 82 0A 0B 09 27 2A 24
|
||||
39 00 00 40 00 00 04 B0 02 CC 1D
|
||||
39 00 00 40 00 00 09 1D 38 30 3E 43 39 41 46 3C
|
||||
39 00 00 40 00 00 04 B0 01 A5 1F
|
||||
39 00 00 40 00 00 09 1F E2 00 00 00 92 2C 6A 80
|
||||
39 00 00 40 00 00 04 B0 01 AD 1F
|
||||
39 00 00 40 00 00 07 1F 61 1A 64 1D FF 9F
|
||||
39 00 00 40 00 00 04 B0 01 B5 1F
|
||||
39 00 00 40 00 00 04 1F 49 00 10
|
||||
39 00 00 40 00 00 04 B0 01 BA 1F
|
||||
39 00 00 40 00 00 06 1F 05 FF 10 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C1 1F
|
||||
39 00 00 40 00 00 05 1F 00 00 00 00
|
||||
39 00 00 40 00 00 04 B0 01 C5 1F
|
||||
39 00 00 40 00 00 05 1F 03 FF 21 3C
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-panel-read-register-open-command = [
|
||||
39 00 00 00 00 00 03 F0 5A 5A
|
||||
];
|
||||
qcom,mdss-dsi-panel-id1-command = [
|
||||
06 00 00 00 00 00 01 E9
|
||||
];
|
||||
qcom,mdss-dsi-panel-read-register-close-command = [
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-enter-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-exit-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-pre-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-lp1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-nolp-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aod-high-mode-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aod-low-mode-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-ultra-low-power-aod-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-ultra-low-power-aod-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-dly-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-dly-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aor-restore-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-loading-effect-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-loading-effect-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-loading-effect-off-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-scr-version = <1>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
@@ -42,7 +42,7 @@
|
||||
qcom,mdss-dsi-panel-blackness-level = <2000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
cell-index = <0>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -59,12 +59,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -411,7 +410,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -420,8 +419,106 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -430,7 +527,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
cell-index = <1>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-90fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -447,13 +544,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -663,7 +753,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
cell-index = <2>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-60fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -680,13 +770,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -1032,17 +1115,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1051,7 +1123,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
cell-index = <3>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -1068,18 +1140,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -1431,7 +1494,7 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1440,10 +1503,40 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 24
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1452,7 +1545,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
cell-index = <4>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -1469,12 +1562,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -1797,7 +1889,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1806,8 +1898,106 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1816,7 +2006,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
cell-index = <5>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-90fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -1833,13 +2023,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -2033,7 +2216,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
cell-index = <6>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-60fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -2050,13 +2233,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -2378,17 +2554,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2397,7 +2562,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
cell-index = <7>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -2414,18 +2579,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -2753,19 +2909,49 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 72
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 24
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2781,42 +2967,42 @@
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
@@ -2827,7 +3013,6 @@
|
||||
&dsi_panel_samsung_amb682cg01_1440_3168_dsc_cmd_dvt {
|
||||
/* HARDWARE CONFIG */
|
||||
qcom,panel-supply-entries = <&oplus_wukong_dsi_panel_pwr_supply>;
|
||||
qcom,dynamic-te-gpio = <&tlmm 87 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
qcom,platform-panel-vout-gpio = <&tlmm 90 0>;
|
||||
//qcom,platform-panel-vddr-aod-en-gpio = <&tlmm 180 0>;
|
||||
@@ -2894,11 +3079,14 @@
|
||||
/*
|
||||
** 0st bit: adfr global on/off
|
||||
** 1st bit: fakeframe on/off
|
||||
** 2st bit: switch on/off
|
||||
** 2nd bit: switch on/off
|
||||
** 3rd bit: 0:double-TE switch 1:external TE/TP switch
|
||||
** 4rd bit: idle mode on/off
|
||||
** 4th bit: idle mode on/off
|
||||
** 5th bit: temperature detection
|
||||
** 6th bit: OA bl mutual exclution
|
||||
*/
|
||||
oplus,adfr-config = <0x11>;
|
||||
oplus,adfr-config = <0x51>;
|
||||
oplus,adfr-test-te-gpio = <&tlmm 87 0>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-fp-type = <0x88>;
|
||||
|
||||
@@ -42,7 +42,7 @@
|
||||
qcom,mdss-dsi-panel-blackness-level = <2000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
cell-index = <0>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt1.dtsi"
|
||||
@@ -59,12 +59,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -335,8 +334,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -345,8 +343,43 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -355,9 +388,61 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -366,7 +451,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
cell-index = <1>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-90fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt1.dtsi"
|
||||
@@ -383,13 +468,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -601,13 +679,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -616,7 +687,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
cell-index = <2>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-60fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt1.dtsi"
|
||||
@@ -633,13 +704,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -909,30 +973,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -941,7 +981,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
cell-index = <3>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt1.dtsi"
|
||||
@@ -958,18 +998,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -1247,70 +1278,16 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 72
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 54
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 36
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 2A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 18
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
@@ -1319,19 +1296,19 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0C
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
15 00 00 40 00 00 02 BD 24
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
@@ -1340,16 +1317,10 @@
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1358,7 +1329,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
cell-index = <4>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt1.dtsi"
|
||||
@@ -1375,12 +1346,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -1635,7 +1605,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1644,7 +1614,43 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1653,9 +1659,61 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1664,7 +1722,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
cell-index = <5>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-90fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt1.dtsi"
|
||||
@@ -1681,13 +1739,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -1883,13 +1934,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1898,7 +1942,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
cell-index = <6>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-60fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt1.dtsi"
|
||||
@@ -1915,13 +1959,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -2175,27 +2212,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2204,7 +2220,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
cell-index = <7>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt1.dtsi"
|
||||
@@ -2221,18 +2237,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -2494,70 +2501,16 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 72
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 54
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 36
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 2A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 18
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
@@ -2566,37 +2519,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0C
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
15 00 00 40 00 00 02 BD 24
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2612,42 +2559,42 @@
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
@@ -2658,7 +2605,6 @@
|
||||
&dsi_panel_samsung_amb682cg01_1440_3168_dsc_cmd_evt1 {
|
||||
/* HARDWARE CONFIG */
|
||||
qcom,panel-supply-entries = <&oplus_wukong_dsi_panel_pwr_supply>;
|
||||
qcom,dynamic-te-gpio = <&tlmm 87 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
qcom,platform-panel-vout-gpio = <&tlmm 90 0>;
|
||||
//qcom,platform-panel-vddr-aod-en-gpio = <&tlmm 180 0>;
|
||||
@@ -2727,7 +2673,8 @@
|
||||
** 3rd bit: 0:double-TE switch 1:external TE/TP switch
|
||||
** 4rd bit: idle mode on/off
|
||||
*/
|
||||
oplus,adfr-config = <0x11>;
|
||||
oplus,adfr-config = <0x51>;
|
||||
oplus,adfr-test-te-gpio = <&tlmm 87 0>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-fp-type = <0x88>;
|
||||
|
||||
@@ -42,7 +42,7 @@
|
||||
qcom,mdss-dsi-panel-blackness-level = <2000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
cell-index = <0>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -59,12 +59,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -335,8 +334,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -345,8 +343,43 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -355,9 +388,61 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -366,7 +451,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
cell-index = <1>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-90fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -383,13 +468,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -601,13 +679,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -616,7 +687,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
cell-index = <2>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-60fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -633,13 +704,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -909,30 +973,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -941,7 +981,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
cell-index = <3>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -958,18 +998,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -1247,70 +1278,16 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 72
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 54
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 36
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 2A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 18
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
@@ -1319,19 +1296,19 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0C
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
15 00 00 40 00 00 02 BD 24
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
@@ -1340,16 +1317,10 @@
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1358,7 +1329,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
cell-index = <4>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -1375,12 +1346,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -1635,7 +1605,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1644,7 +1614,43 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1653,9 +1659,61 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1664,7 +1722,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
cell-index = <5>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-90fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -1681,13 +1739,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -1883,13 +1934,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1898,7 +1942,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
cell-index = <6>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-60fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -1915,13 +1959,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -2175,27 +2212,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2204,7 +2220,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
cell-index = <7>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -2221,18 +2237,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -2494,70 +2501,16 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 72
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 54
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 36
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 2A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 18
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
@@ -2566,37 +2519,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0C
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
15 00 00 40 00 00 02 BD 24
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2612,42 +2559,42 @@
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
@@ -2658,7 +2605,6 @@
|
||||
&dsi_panel_samsung_amb682cg01_1440_3168_dsc_cmd_evt2 {
|
||||
/* HARDWARE CONFIG */
|
||||
qcom,panel-supply-entries = <&oplus_wukong_dsi_panel_pwr_supply>;
|
||||
qcom,dynamic-te-gpio = <&tlmm 87 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
qcom,platform-panel-vout-gpio = <&tlmm 90 0>;
|
||||
//qcom,platform-panel-vddr-aod-en-gpio = <&tlmm 180 0>;
|
||||
@@ -2727,7 +2673,8 @@
|
||||
** 3rd bit: 0:double-TE switch 1:external TE/TP switch
|
||||
** 4rd bit: idle mode on/off
|
||||
*/
|
||||
oplus,adfr-config = <0x11>;
|
||||
oplus,adfr-config = <0x51>;
|
||||
oplus,adfr-test-te-gpio = <&tlmm 87 0>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-fp-type = <0x88>;
|
||||
|
||||
@@ -42,7 +42,7 @@
|
||||
qcom,mdss-dsi-panel-blackness-level = <2000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
cell-index = <0>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -59,12 +59,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -342,8 +341,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -352,8 +350,43 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -362,9 +395,61 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -373,7 +458,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
cell-index = <1>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-90fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -390,13 +475,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -615,13 +693,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -630,7 +701,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
cell-index = <2>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-60fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -647,13 +718,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -930,30 +994,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -962,7 +1002,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
cell-index = <3>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -979,18 +1019,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -1275,70 +1306,16 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 72
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 54
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 36
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 2A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 18
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
@@ -1347,19 +1324,19 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0C
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
15 00 00 40 00 00 02 BD 24
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
@@ -1368,16 +1345,10 @@
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1386,7 +1357,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
cell-index = <4>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -1403,12 +1374,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -1670,7 +1640,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1679,7 +1649,43 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1688,9 +1694,61 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1699,7 +1757,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
cell-index = <5>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-90fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -1716,13 +1774,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -1925,13 +1976,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1940,7 +1984,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
cell-index = <6>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-60fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -1957,13 +2001,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -2224,27 +2261,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2253,7 +2269,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
cell-index = <7>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-old-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect-evt2.dtsi"
|
||||
@@ -2270,18 +2286,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -2550,70 +2557,16 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 72
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 54
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 36
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 2A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 18
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
@@ -2622,37 +2575,31 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0C
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
15 00 00 40 00 00 02 BD 24
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2668,42 +2615,42 @@
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
@@ -2714,7 +2661,6 @@
|
||||
&dsi_panel_samsung_amb682cg01_1440_3168_dsc_cmd_ldo {
|
||||
/* HARDWARE CONFIG */
|
||||
qcom,panel-supply-entries = <&oplus_wukong_dsi_panel_pwr_supply>;
|
||||
qcom,dynamic-te-gpio = <&tlmm 87 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
qcom,platform-panel-vout-gpio = <&tlmm 90 0>;
|
||||
//qcom,platform-panel-vddr-aod-en-gpio = <&tlmm 180 0>;
|
||||
@@ -2783,7 +2729,8 @@
|
||||
** 3rd bit: 0:double-TE switch 1:external TE/TP switch
|
||||
** 4rd bit: idle mode on/off
|
||||
*/
|
||||
oplus,adfr-config = <0x11>;
|
||||
oplus,adfr-config = <0x51>;
|
||||
oplus,adfr-test-te-gpio = <&tlmm 87 0>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-fp-type = <0x88>;
|
||||
|
||||
@@ -59,12 +59,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -335,8 +334,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
/* SDC Auto Off */
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -345,8 +343,43 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
/* SDC Auto On */
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -355,9 +388,61 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -383,13 +468,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -601,13 +679,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -633,13 +704,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -909,30 +973,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -958,18 +998,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -1247,70 +1278,16 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 72
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 54
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 36
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 2A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 18
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
@@ -1319,37 +1296,11 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1375,12 +1326,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -1635,7 +1585,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1644,7 +1594,43 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1653,9 +1639,61 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1681,13 +1719,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -1883,13 +1914,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1915,13 +1939,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -2175,27 +2192,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2221,18 +2217,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -2494,70 +2481,16 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 72
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 54
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 36
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 2A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 18
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
@@ -2566,37 +2499,10 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 0C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-5-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-6-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-7-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-8-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-9-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2612,42 +2518,42 @@
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
@@ -2658,7 +2564,6 @@
|
||||
&dsi_panel_samsung_amb682cg01_1440_3168_dsc_cmd_t0 {
|
||||
/* HARDWARE CONFIG */
|
||||
qcom,panel-supply-entries = <&oplus_wukong_dsi_panel_pwr_supply>;
|
||||
qcom,dynamic-te-gpio = <&tlmm 87 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
qcom,platform-panel-vout-gpio = <&tlmm 90 0>;
|
||||
//qcom,platform-panel-vddr-aod-en-gpio = <&tlmm 180 0>;
|
||||
@@ -2727,7 +2632,8 @@
|
||||
** 3rd bit: 0:double-TE switch 1:external TE/TP switch
|
||||
** 4rd bit: idle mode on/off
|
||||
*/
|
||||
oplus,adfr-config = <0x11>;
|
||||
oplus,adfr-config = <0x51>;
|
||||
oplus,adfr-test-te-gpio = <&tlmm 87 0>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-fp-type = <0x88>;
|
||||
|
||||
@@ -42,7 +42,7 @@
|
||||
qcom,mdss-dsi-panel-blackness-level = <2000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
cell-index = <0>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -59,12 +59,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -411,7 +410,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -420,8 +419,106 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -430,7 +527,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
cell-index = <1>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-90fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -447,13 +544,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <8>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -663,7 +753,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
cell-index = <2>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-60fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -680,13 +770,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -1032,17 +1115,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1051,7 +1123,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
cell-index = <3>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -1068,18 +1140,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 825.6Mbps */
|
||||
@@ -1431,7 +1494,7 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1440,10 +1503,40 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 24
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1080 44 1080 44 1080 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1452,7 +1545,7 @@
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
cell-index = <4>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -1469,12 +1562,11 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 20 10 5 1>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -1797,7 +1889,7 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
@@ -1806,8 +1898,106 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 3C
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 84
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 14
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 94
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 05
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-2-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-3-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-4-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -1816,7 +2006,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
cell-index = <5>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-90fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -1833,13 +2023,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -2033,7 +2216,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
cell-index = <6>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-60fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -2050,13 +2233,6 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* SDC ADFR */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-fakeframe-config = <3>;
|
||||
oplus,adfr-fakeframe-deferred-time = <6>; /* period*0.7 */
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <1314>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <1314>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -2378,17 +2554,6 @@
|
||||
05 00 00 00 00 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2397,7 +2562,7 @@
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
cell-index = <7>;
|
||||
#include "dsi-panel-samsung-amb682cg01-common-120fps.dtsi"
|
||||
#include "dsi-panel-samsung-amb682cg01-common-effect.dtsi"
|
||||
@@ -2414,18 +2579,9 @@
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <8>;
|
||||
|
||||
/* OPLUS ADFR */
|
||||
/* oplus adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <2>;
|
||||
qcom,mdss-dsi-qsync-min-fps-0 = <6>;
|
||||
qcom,mdss-dsi-qsync-min-fps-1 = <8>;
|
||||
qcom,mdss-dsi-qsync-min-fps-2 = <10>;
|
||||
qcom,mdss-dsi-qsync-min-fps-3 = <12>;
|
||||
qcom,mdss-dsi-qsync-min-fps-4 = <15>;
|
||||
qcom,mdss-dsi-qsync-min-fps-5 = <20>;
|
||||
qcom,mdss-dsi-qsync-min-fps-6 = <24>;
|
||||
qcom,mdss-dsi-qsync-min-fps-7 = <30>;
|
||||
qcom,mdss-dsi-qsync-min-fps-8 = <40>;
|
||||
qcom,mdss-dsi-qsync-min-fps-9 = <60>;
|
||||
oplus,adfr-min-fps-mapping-table = <120 30>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
/* FFC Setting: OSC 171.3Mhz, MIPI 1372Mbps */
|
||||
@@ -2753,19 +2909,49 @@
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command = [
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 72
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 12
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 24
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-qsync-on-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-on-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-auto-off-command-state ="dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-0-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-hpwm-adfr-min-fps-1-command-state = "dsi_hs_mode";
|
||||
//qcom,panel-roi-alignment=<1440 44 1440 44 1440 44>;
|
||||
//qcom,partial-update-enabled = "single_roi";
|
||||
|
||||
@@ -2781,42 +2967,42 @@
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 0F 06 07 06 02 04 00 17 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 19 0A 0C 0A 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
@@ -2827,7 +3013,6 @@
|
||||
&dsi_panel_samsung_amb682cg01_1440_3168_dsc_cmd {
|
||||
/* HARDWARE CONFIG */
|
||||
qcom,panel-supply-entries = <&oplus_wukong_dsi_panel_pwr_supply>;
|
||||
qcom,dynamic-te-gpio = <&tlmm 87 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
qcom,platform-panel-vout-gpio = <&tlmm 90 0>;
|
||||
//qcom,platform-panel-vddr-aod-en-gpio = <&tlmm 180 0>;
|
||||
@@ -2894,11 +3079,14 @@
|
||||
/*
|
||||
** 0st bit: adfr global on/off
|
||||
** 1st bit: fakeframe on/off
|
||||
** 2st bit: switch on/off
|
||||
** 2nd bit: switch on/off
|
||||
** 3rd bit: 0:double-TE switch 1:external TE/TP switch
|
||||
** 4rd bit: idle mode on/off
|
||||
** 4th bit: idle mode on/off
|
||||
** 5th bit: temperature detection
|
||||
** 6th bit: OA bl mutual exclution
|
||||
*/
|
||||
oplus,adfr-config = <0x11>;
|
||||
oplus,adfr-config = <0x51>;
|
||||
oplus,adfr-test-te-gpio = <&tlmm 87 0>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-fp-type = <0x88>;
|
||||
|
||||
@@ -13,10 +13,10 @@
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
/* ofp config */
|
||||
oplus,ofp-need-to-separate-backlight;
|
||||
oplus,ofp-hbm-on-period = <2>;
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
@@ -33,6 +33,8 @@
|
||||
39 00 00 40 00 00 03 F0 5A 5A /* Level2 key Access Enable */
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00 /* SDC auto mode min == max */
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 23 /* 21 : Manual On 23 Auto On */
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */
|
||||
|
||||
@@ -13,9 +13,14 @@
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-min-fps-mapping-table = <60 20 10 5 1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-hbm-on-period = <2>;
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
@@ -28,14 +33,73 @@
|
||||
/* Sleep In(10h) */
|
||||
05 00 00 00 64 00 01 10
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-pre-switch-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A /* Level2 key Access Enable */
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00 /* SDC auto mode min == max */
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 23 /* 21 : Manual On 23 Auto On */
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-lp1-command = [
|
||||
/* TSP_SYNC3 Setting: Dynamic Single TE */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
|
||||
@@ -13,10 +13,14 @@
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-need-to-separate-backlight;
|
||||
oplus,ofp-hbm-on-period = <2>;
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
@@ -29,6 +33,13 @@
|
||||
/* Sleep In(10h) */
|
||||
05 00 00 00 64 00 01 10
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
qcom,mdss-dsi-lp1-command = [
|
||||
/* Force Increasing ON */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -182,6 +193,7 @@
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-lp1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-nolp-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aod-high-mode-command-state = "dsi_hs_mode";
|
||||
|
||||
@@ -13,10 +13,10 @@
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
/* ofp config */
|
||||
oplus,ofp-need-to-separate-backlight;
|
||||
oplus,ofp-hbm-on-period = <2>;
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
@@ -33,6 +33,8 @@
|
||||
39 00 00 40 00 00 03 F0 5A 5A /* Level2 key Access Enable */
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00 /* SDC auto mode min == max */
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 23 /* 21 : Manual On 23 Auto On */
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */
|
||||
|
||||
@@ -13,9 +13,14 @@
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
oplus,adfr-min-fps-mapping-table = <60 20 10 5 1>;
|
||||
oplus,adfr-idle-off-min-fps = <20>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-hbm-on-period = <2>;
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
@@ -28,14 +33,73 @@
|
||||
/* Sleep In(10h) */
|
||||
05 00 00 00 64 00 01 10
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-adfr-auto-off-command = [
|
||||
/* SDC Auto Off */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
15 00 00 40 00 00 02 BD 23
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-0-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 06
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-1-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 1E
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-2-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 42
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-3-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 8A
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-min-fps-4-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD CA
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 02
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
qcom,mdss-dsi-adfr-pre-switch-command = [
|
||||
39 00 00 40 00 00 03 F0 5A 5A /* Level2 key Access Enable */
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00 /* SDC auto mode min == max */
|
||||
39 00 00 40 00 00 04 B0 00 13 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 BD 23 /* 21 : Manual On 23 Auto On */
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-lp1-command = [
|
||||
/* TSP_SYNC3 Setting: Dynamic Single TE */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
|
||||
@@ -13,10 +13,14 @@
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
/* standard adfr */
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
oplus,adfr-fakeframe-config = <1>;
|
||||
|
||||
/* ofp config */
|
||||
oplus,ofp-need-to-separate-backlight;
|
||||
oplus,ofp-hbm-on-period = <2>;
|
||||
oplus,ofp-need-to-sync-data-in-aod-unlocking;
|
||||
|
||||
qcom,mdss-dsi-post-on-backlight = [
|
||||
/* Display On */
|
||||
@@ -29,6 +33,13 @@
|
||||
/* Sleep In(10h) */
|
||||
05 00 00 00 64 00 01 10
|
||||
];
|
||||
qcom,mdss-dsi-adfr-fakeframe-command = [
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 40 00 00 01 2C
|
||||
05 00 00 40 00 00 01 3C
|
||||
05 00 00 00 00 00 01 00
|
||||
];
|
||||
qcom,mdss-dsi-lp1-command = [
|
||||
/* Force Increasing ON */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
@@ -182,6 +193,7 @@
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-adfr-fakeframe-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-lp1-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-nolp-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-aod-high-mode-command-state = "dsi_hs_mode";
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
65
qcom/display/oplus/pxlw-aston/dsi-panel-pxlw-iris7p.dtsi
Normal file
65
qcom/display/oplus/pxlw-aston/dsi-panel-pxlw-iris7p.dtsi
Normal file
@@ -0,0 +1,65 @@
|
||||
/* Copyright (c) 2020, Pixelworks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "pxlw-iris7p-cfg-aston-AA551-P-3-A0004-dsc-cmd.dtsi"
|
||||
|
||||
&soc {
|
||||
dsi_iris_pwr_supply: dsi_iris_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "px_v18r";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <62000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* avoid failed to parse power config */
|
||||
dsi_panel_pwr_sec_supply: dsi_panel_pwr_sec_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "dummy";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <60700>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
pxlw,dsi-display-primary-active = "qcom,mdss_dsi_panel_AA551_P_3_A0004_dsc_cmd";
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
pxlw,iris-lightup-config = <&mdss_iris7p_cfg_aston_AA551_P_3_A0004_dsc_cmd>;
|
||||
px_v18r-supply = <&L12B>;
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
px_v18r-supply = <&L12B>;
|
||||
};
|
||||
|
||||
&dsi_panel_AA551_P_3_A0004_dsc_cmd {
|
||||
pxlw,iris-chip-capability = <0x1 0x1 0x7 0x377 0x2>;
|
||||
qcom,iris-supply-entries = <&dsi_iris_pwr_supply>;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,241 @@
|
||||
/*Fullchip
|
||||
|
||||
//dtype, last, wait, ip, opt, dlen
|
||||
//sys*/
|
||||
//commit: 8112c219393a49215c64201f3a4e598da1c2b54d
|
||||
//build : 2023-10-17 17:20:55
|
||||
&soc {
|
||||
pxlw {
|
||||
mdss_iris7p_cfg_aston_AA551_P_3_A0004_dsc_cmd: pxlw,mdss_iris7p_cfg_aston_AA551_P_3_A0004_dsc_cmd {
|
||||
pxlw,platform = <1>;
|
||||
pxlw,panel-type = "PANEL_OLED";
|
||||
/*low power control: dynamic power gating, ulps low power, analog bypass */
|
||||
pxlw,low-power = [01 01 02];
|
||||
/* virtual channel enable: PT, FRC */
|
||||
pxlw,virtual-channel-enable = [00 00];
|
||||
pxlw,virtual-channel-id = [00 02 03];
|
||||
pxlw,chip-ver = <0x6935>;
|
||||
pxlw,pkt-payload-size = <228>;
|
||||
pxlw,min-color-temp = <2500>;
|
||||
pxlw,max-color-temp = <10000>;
|
||||
/*first value represents lightup, second is pq update*/
|
||||
/*0: non-embedded, 1: embedded-no-ma, 2: embedded-ma*/
|
||||
pxlw,dsi-trans-mode = [00 01];
|
||||
/*the 3 groups represent 3 trans modes, non-embedded, embedded-no-ma, embedded-ma*/
|
||||
/*in non-embedded mode, the value must be a multiple of 256*/
|
||||
/*in embedded mode, the value must be a multiple of (pkt-payload-size + 8)*/
|
||||
pxlw,dsi-trans-len = <0x1000 0x400>, <0x0 0x0>, <0x0 0x0>;
|
||||
/* 0: DSI_VIDEO_MODE, 1: DSI_CMD_MODE */
|
||||
pxlw,iris-tx-mode = /bits/ 8 <1>;
|
||||
pxlw,panel-dimming-brightness = <4095>;
|
||||
pxlw,panel-te = <60>;
|
||||
pxlw,ap-te = <60>;
|
||||
pxlw,esd-ctrl = <7>;
|
||||
pxlw,timing-cmd-map = [02 01 00 FF];
|
||||
pxlw,master-timing-cmd-map = [00 00 00 00];
|
||||
pxlw,cmd-param-from-firmware = <1>;
|
||||
pxlw,iris-lightup-sequence-pre0= [
|
||||
00 00 00
|
||||
00 01 00
|
||||
];
|
||||
pxlw,iris-lightup-sequence-pre1= [
|
||||
00 00 00
|
||||
00 01 00
|
||||
];
|
||||
pxlw,iris-lightup-sequence-cont-splash= [
|
||||
00 00 00
|
||||
];
|
||||
pxlw,iris-lightup-sequence= [
|
||||
/* sys */
|
||||
00 16 01
|
||||
00 1a 00
|
||||
/* mipi */
|
||||
01 00 00
|
||||
01 01 00
|
||||
01 02 00
|
||||
01 03 00
|
||||
02 00 00
|
||||
02 01 00
|
||||
02 02 00
|
||||
02 03 00
|
||||
/* dtg */
|
||||
05 00 00
|
||||
05 F0 00
|
||||
/* dport */
|
||||
04 01 00
|
||||
04 E1 00
|
||||
04 80 00
|
||||
/* pwil */
|
||||
03 01 00
|
||||
03 02 00
|
||||
03 03 00
|
||||
03 04 00
|
||||
03 05 00
|
||||
03 06 00
|
||||
03 07 00
|
||||
03 08 00
|
||||
03 09 00
|
||||
03 0a 00
|
||||
03 10 00
|
||||
03 11 00
|
||||
03 12 00
|
||||
03 40 00
|
||||
03 80 00
|
||||
/* blending */
|
||||
2e 00 00
|
||||
2e 40 00
|
||||
2e 80 00
|
||||
/*gamma,65-bin*/
|
||||
86 00 00
|
||||
/*3dlut,17-bin*/
|
||||
81 01 00
|
||||
81 02 00
|
||||
81 03 00
|
||||
81 04 00
|
||||
81 05 00
|
||||
81 06 00
|
||||
/*dpp pre_lut*/
|
||||
92 10 00
|
||||
92 00 00
|
||||
/*dpp dlv_lut*/
|
||||
96 00 00
|
||||
/* dpp */
|
||||
0e f0 01
|
||||
0e 00 00
|
||||
0e 10 00
|
||||
0e 20 00
|
||||
0e 21 00
|
||||
0e 23 00
|
||||
0e 30 00
|
||||
0e 31 00
|
||||
0e 32 00
|
||||
0e 33 00
|
||||
0e 34 00
|
||||
0e 40 00
|
||||
0e 50 00
|
||||
0e 51 00
|
||||
0e 52 00
|
||||
0e 60 00
|
||||
0e 61 00
|
||||
0e 70 00
|
||||
0e 90 00
|
||||
0e a0 00
|
||||
0e c0 00
|
||||
0e d0 00
|
||||
0e e0 00
|
||||
0e 80 00
|
||||
/* scl */
|
||||
0b 00 00
|
||||
83 10 00
|
||||
83 50 00
|
||||
83 90 00
|
||||
83 d0 00
|
||||
8e 10 00
|
||||
8e 50 00
|
||||
8e 90 00
|
||||
8e d0 00
|
||||
/* srcnn */
|
||||
39 00 00
|
||||
39 01 00
|
||||
39 10 00
|
||||
39 20 00
|
||||
39 30 00
|
||||
39 40 00
|
||||
39 80 00
|
||||
8a 10 00
|
||||
8a 50 00
|
||||
8a 90 00
|
||||
8a d0 00
|
||||
94 a0 00
|
||||
94 10 00
|
||||
94 11 00
|
||||
94 12 00
|
||||
94 13 00
|
||||
94 14 00
|
||||
94 20 00
|
||||
94 21 00
|
||||
94 22 00
|
||||
94 23 00
|
||||
94 24 00
|
||||
/* frc dsc */
|
||||
25 00 00
|
||||
25 01 00
|
||||
26 00 00
|
||||
26 01 00
|
||||
24 00 00
|
||||
24 01 00
|
||||
24 80 00
|
||||
/* dsc */
|
||||
08 00 00
|
||||
08 01 00
|
||||
08 02 00
|
||||
07 00 00
|
||||
07 01 00
|
||||
/* psr_mif */
|
||||
2d 00 00
|
||||
/* dma */
|
||||
11 f0 00
|
||||
11 d0 00
|
||||
11 d3 00
|
||||
11 d1 00
|
||||
11 d2 00
|
||||
11 d4 00
|
||||
11 d5 00
|
||||
11 ee 00
|
||||
11 e1 00
|
||||
];
|
||||
pxlw,iris-fps-switch-sequence= [
|
||||
/* sys */
|
||||
00 15 00
|
||||
/* dtg */
|
||||
05 00 01
|
||||
05 f9 00
|
||||
/* dport */
|
||||
04 e1 00
|
||||
/* dma */
|
||||
11 e5 00
|
||||
];
|
||||
pxlw,iris-fps-clk-switch-sequence= [
|
||||
/* sys */
|
||||
00 00 00
|
||||
00 18 00
|
||||
00 15 00
|
||||
/* mipi_tx */
|
||||
02 01 00
|
||||
/* dtg */
|
||||
05 00 01
|
||||
05 f9 00
|
||||
/* dport */
|
||||
04 e1 00
|
||||
/* dma */
|
||||
11 e1 00
|
||||
];
|
||||
pxlw,iris-pq-default-val= [
|
||||
00 00
|
||||
/* dpp */
|
||||
0e 20
|
||||
0e 30
|
||||
0e 50
|
||||
0e 60
|
||||
0e 70
|
||||
0e 90
|
||||
0e a0
|
||||
0e c0
|
||||
0e d0
|
||||
0e e0
|
||||
81 01
|
||||
86 00
|
||||
86 10
|
||||
86 20
|
||||
92 00
|
||||
96 00
|
||||
/* sr2d */
|
||||
39 10
|
||||
39 20
|
||||
39 30
|
||||
39 40
|
||||
];
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
180
qcom/display/oplus/pxlw-iris7p-kalama-common.dtsi
Normal file
180
qcom/display/oplus/pxlw-iris7p-kalama-common.dtsi
Normal file
@@ -0,0 +1,180 @@
|
||||
/* Copyright (c) 2020, Pixelworks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
&tlmm {
|
||||
pxlw_iris_gpio: pxlw_iris_gpio {
|
||||
iris_reset_active: iris_reset_active {
|
||||
mux {
|
||||
pins = "gpio109";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio109";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
iris_reset_suspend: iris_reset_suspend {
|
||||
mux {
|
||||
pins = "gpio109";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio109";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
iris_wakeup_active: iris_wakeup_active {
|
||||
mux {
|
||||
pins = "gpio129";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio129";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
iris_wakeup_suspend: iris_wakeup_suspend {
|
||||
mux {
|
||||
pins = "gpio129";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio129";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
iris_abyp_ready_active: iris_abyp_ready_active {
|
||||
mux {
|
||||
pins = "gpio181";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio181";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
iris_abyp_ready_suspend: iris_abyp_ready_suspend {
|
||||
mux {
|
||||
pins = "gpio181";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio181";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
iris_vdd18_active: iris_vdd18_active {
|
||||
mux {
|
||||
pins = "gpio92";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio92";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
iris_vdd18_suspend: iris_vdd18_suspend {
|
||||
mux {
|
||||
pins = "gpio92";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio92";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
iris_vdd09_active: iris_vdd09_active {
|
||||
mux {
|
||||
pins = "gpio105";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio105";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
iris_vdd09_suspend: iris_vdd09_suspend {
|
||||
mux {
|
||||
pins = "gpio105";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio105";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
pxlw,iris {
|
||||
compatible = "pxlw,iris";
|
||||
index = <0>;
|
||||
|
||||
pinctrl-names = "iris_active", "iris_suspend";
|
||||
pinctrl-0 = <&iris_reset_active &iris_wakeup_active &iris_abyp_ready_active>;
|
||||
pinctrl-1 = <&iris_reset_suspend &iris_wakeup_suspend &iris_abyp_ready_suspend>;
|
||||
|
||||
qcom,iris-reset-gpio = <&tlmm 109 0>;
|
||||
qcom,iris-wakeup-gpio = <&tlmm 129 0>;
|
||||
qcom,iris-abyp-ready-gpio = <&tlmm 181 0>;
|
||||
qcom,iris-vdd-gpio = <&tlmm 92 0>;
|
||||
qcom,iris-vdd-0p9v-gpio = <&tlmm 105 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se10_i2c {
|
||||
status = "ok";
|
||||
qcom,clk-freq-out = <400000>;
|
||||
pixelworks@26 { //i2c: 22, i3c: 26
|
||||
status = "ok";
|
||||
compatible = "pixelworks,iris";
|
||||
reg = <0x26>;
|
||||
};
|
||||
|
||||
pixelworks@22 { //i2c: 22, i3c: 26
|
||||
status = "ok";
|
||||
compatible = "pixelworks,iris-i2c";
|
||||
reg = <0x22>;
|
||||
};
|
||||
};
|
||||
@@ -63,4 +63,4 @@
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -56,4 +56,4 @@
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -63,4 +63,4 @@
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -59,4 +59,4 @@
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -56,4 +56,4 @@
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -52,4 +52,4 @@
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -63,4 +63,4 @@
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -56,4 +56,4 @@
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -53,9 +53,9 @@
|
||||
oplus,mdss-dsi-panel-status-match-modes = <0x00000000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <6200>;
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
@@ -86,9 +86,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <6200>;
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
@@ -119,9 +119,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <6200>;
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-timing-default;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
@@ -153,9 +153,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <6200>;
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
@@ -186,9 +186,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
@@ -219,9 +219,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
@@ -252,9 +252,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7300>;
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
@@ -285,9 +285,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7300>;
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
@@ -353,42 +353,42 @@
|
||||
qcom,mdss-dsi-dc-backlight-level = <520>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
@@ -398,7 +398,7 @@
|
||||
qcom,mdss-mdp-transfer-time-us = <7468>; //same as main panel
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2E 0C 0C 1D 1B 0C 0D 0B 02 04 00 25 11];
|
||||
qcom,display-topology = <1 0 1>,<2 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -59,18 +59,21 @@
|
||||
|
||||
/* 120hz Transition */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 02 BD 21
|
||||
39 00 00 40 00 00 04 B0 00 16 F2
|
||||
39 00 00 40 00 00 03 F2 1B 50
|
||||
39 00 00 40 00 00 04 B0 00 08 CB /* power saving */
|
||||
15 00 00 40 00 00 02 CB 24
|
||||
15 00 00 40 00 00 02 60 00
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 63 CB
|
||||
39 00 00 40 00 00 02 CB 08
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -51,18 +51,21 @@
|
||||
|
||||
/* 120hz Transition */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 02 BD 21
|
||||
39 00 00 40 00 00 04 B0 00 16 F2
|
||||
39 00 00 40 00 00 03 F2 1B 50
|
||||
39 00 00 40 00 00 04 B0 00 08 CB /* power saving */
|
||||
15 00 00 40 00 00 02 CB 24
|
||||
15 00 00 40 00 00 02 60 00
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 63 CB
|
||||
39 00 00 40 00 00 02 CB 08
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -59,18 +59,21 @@
|
||||
|
||||
/* 120hz Transition */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 02 BD 21
|
||||
39 00 00 40 00 00 04 B0 00 16 F2
|
||||
39 00 00 40 00 00 03 F2 1B 50
|
||||
39 00 00 40 00 00 04 B0 00 08 CB /* power saving */
|
||||
15 00 00 40 00 00 02 CB 24
|
||||
15 00 00 40 00 00 02 60 00
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 63 CB
|
||||
39 00 00 40 00 00 02 CB 08
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -69,4 +69,4 @@
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -51,18 +51,21 @@
|
||||
|
||||
/* 120hz Transition */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 02 BD 21
|
||||
39 00 00 40 00 00 04 B0 00 16 F2
|
||||
39 00 00 40 00 00 03 F2 1B 50
|
||||
39 00 00 40 00 00 04 B0 00 08 CB /* power saving */
|
||||
15 00 00 40 00 00 02 CB 24
|
||||
15 00 00 40 00 00 02 60 00
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 63 CB
|
||||
39 00 00 40 00 00 02 CB 08
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -61,4 +61,4 @@
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -59,18 +59,21 @@
|
||||
|
||||
/* 60hz Transition */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 02 BD 21
|
||||
39 00 00 40 00 00 04 B0 00 16 F2
|
||||
39 00 00 40 00 00 03 F2 1B 50
|
||||
39 00 00 40 00 00 04 B0 00 08 CB /* power saving */
|
||||
15 00 00 40 00 00 02 CB 24
|
||||
15 00 00 40 00 00 02 60 01
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
39 00 00 40 00 00 04 B0 00 63 CB
|
||||
39 00 00 40 00 00 02 CB 08
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -51,18 +51,21 @@
|
||||
|
||||
/* 60hz Transition */
|
||||
39 00 00 40 00 00 03 F0 5A 5A
|
||||
39 00 00 40 00 00 02 BD 21
|
||||
39 00 00 40 00 00 04 B0 00 16 F2
|
||||
39 00 00 40 00 00 03 F2 1B 50
|
||||
39 00 00 40 00 00 04 B0 00 08 CB /* power saving */
|
||||
15 00 00 40 00 00 02 CB 24
|
||||
15 00 00 40 00 00 02 60 01
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 40 00 00 04 B0 00 10 BD
|
||||
15 00 00 40 00 00 02 BD 00
|
||||
39 00 00 40 00 00 04 B0 00 16 BD
|
||||
15 00 00 40 00 00 02 BD 77
|
||||
39 00 00 40 00 00 04 B0 00 14 BD
|
||||
15 00 00 40 00 00 02 BD 01
|
||||
39 00 00 40 00 00 04 B0 00 63 CB
|
||||
39 00 00 40 00 00 02 CB 08
|
||||
15 00 00 40 00 00 02 F7 0F
|
||||
39 00 00 40 00 00 03 BD 23 02
|
||||
39 00 00 00 00 00 03 F0 A5 A5
|
||||
];
|
||||
];
|
||||
|
||||
@@ -53,9 +53,9 @@
|
||||
oplus,mdss-dsi-panel-status-match-modes = <0x00000000>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <6200>;
|
||||
timing@fhd_sa_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
@@ -86,9 +86,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_90 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <6200>;
|
||||
timing@fhd_sa_90 {
|
||||
//#include "../dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
@@ -119,9 +119,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@fhd_sdc_60 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <6200>;
|
||||
timing@fhd_sa_60 {
|
||||
//#include "../dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-timing-default;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
@@ -153,9 +153,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@fhd_oplus_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <6200>;
|
||||
timing@fhd_oa_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
//qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <825600000>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
@@ -186,9 +186,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_60 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
timing@wqhd_sa_60 {
|
||||
//#include "../dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-60fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
@@ -219,9 +219,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_90 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
timing@wqhd_sa_90 {
|
||||
//#include "../dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-90fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7700>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
@@ -252,9 +252,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@wqhd_sdc_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7300>;
|
||||
timing@wqhd_sa_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
@@ -285,9 +285,9 @@
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@wqhd_oplus_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf07-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7300>;
|
||||
timing@wqhd_oa_120 {
|
||||
//#include "../dsi-panel-samsung-amb670yf08-1440-3216-dsc-cmd-120fps-common.dtsi"
|
||||
qcom,mdss-mdp-transfer-time-us = <7500>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
@@ -353,42 +353,42 @@
|
||||
qcom,mdss-dsi-dc-backlight-level = <520>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@fhd_sdc_120 {
|
||||
timing@fhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_90 {
|
||||
timing@fhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_sdc_60 {
|
||||
timing@fhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@fhd_oplus_120 {
|
||||
timing@fhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 22 07 07 08 02 04 00 18 0C];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_60 {
|
||||
timing@wqhd_sa_60 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_90 {
|
||||
timing@wqhd_sa_90 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_sdc_120 {
|
||||
timing@wqhd_sa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@wqhd_oplus_120 {
|
||||
timing@wqhd_oa_120 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 26 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
@@ -398,7 +398,7 @@
|
||||
qcom,mdss-mdp-transfer-time-us = <7468>; //same as main panel
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2E 0C 0C 1D 1B 0C 0D 0B 02 04 00 25 11];
|
||||
qcom,display-topology = <1 0 1>,<2 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -2,8 +2,8 @@
|
||||
|
||||
//dtype, last, wait, ip, opt, dlen
|
||||
//sys*/
|
||||
//commit: bf961f687a8d298e3029480804b8308f41862cd6
|
||||
//build : 2022-11-14 14:45:47
|
||||
//commit: 7e7ee2aab79827c5bd326d8c5ea86b9e2fd6e5bb
|
||||
//build : 2023-07-27 11:39:30
|
||||
&soc {
|
||||
pxlw {
|
||||
mdss_iris_cfg_samsung_amb670yf07_1440_3216_dsc_cmd: pxlw,mdss_iris_cfg_samsung_amb670yf07_1440_3216_dsc_cmd {
|
||||
@@ -31,10 +31,11 @@ mdss_iris_cfg_samsung_amb670yf07_1440_3216_dsc_cmd: pxlw,mdss_iris_cfg_samsung_a
|
||||
pxlw,panel-te = <120>;
|
||||
pxlw,ap-te = <120>;
|
||||
pxlw,esd-ctrl = <7>;
|
||||
pxlw,timing-cmd-map = [02 01 00 02 03 04 05 05];
|
||||
pxlw,timing-cmd-map = [02 01 00 FF 03 04 05 FF];
|
||||
pxlw,master-timing-cmd-map = [00 00 00 00 03 03 03 03];
|
||||
pxlw,frc-dsc-init-delay= <4047>;
|
||||
pxlw,cmd-param-from-firmware = <1>;
|
||||
pxlw,ocp_read_by_i2c = <1>;
|
||||
pxlw,iris-lightup-sequence-pre0= [
|
||||
/*sys*/
|
||||
00 a0 00
|
||||
@@ -91,11 +92,11 @@ mdss_iris_cfg_samsung_amb670yf07_1440_3216_dsc_cmd: pxlw,mdss_iris_cfg_samsung_a
|
||||
/*gamma,65-bin*/
|
||||
86 00 01
|
||||
/*3dlut,17-bin*/
|
||||
81 02 01
|
||||
81 03 01
|
||||
81 01 01
|
||||
81 04 01
|
||||
81 05 01
|
||||
81 06 01
|
||||
81 08 01
|
||||
81 09 01
|
||||
81 0a 01
|
||||
81 0b 01
|
||||
|
||||
@@ -0,0 +1,212 @@
|
||||
&mdss_mdp {
|
||||
dsi_panel_AA536_P_3_A0001_dsc_cmd_2nd: qcom,mdss_dsi_panel_AA536_P_3_A0001_dsc_cmd_2nd {
|
||||
qcom,mdss-dsi-panel-name = "AA536 P 3 A0001 dsc cmd mode panel 2nd";
|
||||
oplus,mdss-dsi-vendor-name = "A0001";
|
||||
oplus,mdss-dsi-manufacture = "P3";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <30>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
//qcom,dsi-ctrl-num = <0>;
|
||||
//qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-loading-effect;
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 2>, <0 5>, <1 10>;
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-pan-physical-width-dimension = <70>;
|
||||
qcom,mdss-pan-physical-height-dimension = <155>;
|
||||
qcom,mdss-dsi-init-delay-us = <1000>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-lp11-init;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-bl-high2bit;
|
||||
/* HDR Setting */
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <5400000>;
|
||||
qcom,mdss-dsi-panel-average-brightness = <2000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <4000>;
|
||||
|
||||
qcom,dynamic-mode-switch-enabled;
|
||||
qcom,dynamic-mode-switch-type = "dynamic-resolution-switch-immediate";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@sdc_fhd_120{
|
||||
qcom,mdss-mdp-transfer-time-us = <6290>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsc-scr-version = <0x1>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsi-timing-default;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1094400000>;
|
||||
qcom,mdss-dsi-panel-width = <1240>;
|
||||
qcom,mdss-dsi-panel-height = <2772>;
|
||||
|
||||
qcom,mdss-dsi-h-front-porch = <64>;
|
||||
qcom,mdss-dsi-h-back-porch = <50>;
|
||||
qcom,mdss-dsi-h-pulse-width = <8>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <8>;
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,lm-split = <620 620>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-slice-height = <44>;
|
||||
qcom,mdss-dsc-slice-width = <620>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@sdc_fhd_90{
|
||||
qcom,mdss-mdp-transfer-time-us = <9000>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsc-scr-version = <0x1>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsi-timing-default;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1094400000>;
|
||||
qcom,mdss-dsi-panel-width = <1240>;
|
||||
qcom,mdss-dsi-panel-height = <2772>;
|
||||
|
||||
qcom,mdss-dsi-h-front-porch = <64>;
|
||||
qcom,mdss-dsi-h-back-porch = <80>;
|
||||
qcom,mdss-dsi-h-pulse-width = <8>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <16>;
|
||||
qcom,mdss-dsi-v-front-porch = <10>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,lm-split = <620 620>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-slice-height = <44>;
|
||||
qcom,mdss-dsc-slice-width = <620>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@sdc_fhd_60{
|
||||
qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsc-scr-version = <0x1>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsi-timing-default;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1094400000>;
|
||||
qcom,mdss-dsi-panel-width = <1240>;
|
||||
qcom,mdss-dsi-panel-height = <2772>;
|
||||
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <120>;
|
||||
qcom,mdss-dsi-h-pulse-width = <8>;
|
||||
qcom,mdss-dsi-h-sync-skew = <1>;
|
||||
qcom,mdss-dsi-v-back-porch = <30>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,lm-split = <620 620>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-slice-height = <44>;
|
||||
qcom,mdss-dsc-slice-width = <620>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@raw_fhd_120 {
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
//qcom,mdss-dsi-panel-clockrate = <1320000000>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <1660>;
|
||||
|
||||
qcom,mdss-dsi-h-front-porch = <64>;
|
||||
qcom,mdss-dsi-h-back-porch = <50>;
|
||||
qcom,mdss-dsi-h-pulse-width = <8>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <8>;
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_panel_AA536_P_3_A0001_dsc_cmd_2nd {
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <4095>;
|
||||
|
||||
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,ulps-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@sdc_fhd_120 { /* FHD+ 120hz 1094.4Mbps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 25 09 0A 1A 25 09 0A 09 02 04 00 1E 0F];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@sdc_fhd_90 { /* FHD+ 90hz 1094.4Mbps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 25 09 0A 1A 25 09 0A 09 02 04 00 1E 0F];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@sdc_fhd_60 { /* FHD+ 60hz 1094.4Mbps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 25 09 0A 1A 25 09 0A 09 02 04 00 1E 0F];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@raw_fhd_120 {
|
||||
qcom,mdss-dsi-panel-clockrate = <1440000000>;
|
||||
qcom,mdss-mdp-transfer-time-us = <6800>; //same as main panel
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2E 0C 0C 1D 1B 0C 0D 0B 02 04 00 25 11];
|
||||
qcom,display-topology = <1 0 1>,<2 0 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
81
qcom/display/oplus/pxlw-xigua/dsi-panel-pxlw.dtsi
Normal file
81
qcom/display/oplus/pxlw-xigua/dsi-panel-pxlw.dtsi
Normal file
@@ -0,0 +1,81 @@
|
||||
/* Copyright (c) 2020, Pixelworks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "pxlw-iris7-cfg-dsi-panel-AA536-P-3-A0001-dsc-cmd.dtsi"
|
||||
#include "dsi-panel-AA536-P-3-A0001-dsc-cmd-2nd.dtsi"
|
||||
|
||||
&soc {
|
||||
dsi_iris_pwr_supply: dsi_iris_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "px_v18r";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <62000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* avoid failed to parse power config */
|
||||
dsi_panel_pwr_sec_supply: dsi_panel_pwr_sec_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "dummy";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <60700>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* select panel */
|
||||
&mdss_mdp {
|
||||
pxlw,dsi-display-primary-active = "qcom,mdss_dsi_panel_AA536_P_3_A0001_dsc_cmd";
|
||||
pxlw,dsi-display-secondary-active = "qcom,mdss_dsi_panel_AA536_P_3_A0001_dsc_cmd_2nd";
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
pxlw,iris-lightup-config = <&mdss_iris_cfg_AA536_P_3_A0001_dsc_cmd>;
|
||||
px_v18r-supply = <&L12B>;
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
px_v18r-supply = <&L12B>;
|
||||
};
|
||||
|
||||
&dsi_panel_AA536_P_3_A0001_dsc_cmd {
|
||||
pxlw,iris-chip-capability = <0x1 0x1 0x7 0x7f 0x1>;
|
||||
qcom,iris-supply-entries = <&dsi_iris_pwr_supply>;
|
||||
};
|
||||
|
||||
&dsi_panel_AA536_P_3_A0001_dsc_cmd_2nd {
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
pxlw,iris-chip-capability = <0x1 0x1 0x7 0x7f 0x1>;
|
||||
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_sec_supply>;
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
pxlw,iris-chip-capability = <0x1 0x1 0x7 0x3 0x1>;
|
||||
qcom,iris-supply-entries = <&dsi_iris_pwr_supply>;
|
||||
};
|
||||
@@ -0,0 +1,408 @@
|
||||
/*Fullchip
|
||||
|
||||
//dtype, last, wait, ip, opt, dlen
|
||||
//sys*/
|
||||
//commit: 3b83060ebad9589ff5a1decaa3c4ec73305dfb5d
|
||||
//build : 2023-03-31 16:48:52
|
||||
&soc {
|
||||
pxlw {
|
||||
mdss_iris_cfg_AA536_P_3_A0001_dsc_cmd: pxlw,mdss_iris_cfg_AA536_P_3_A0001_dsc_cmd {
|
||||
pxlw,platform = <1>;
|
||||
pxlw,panel-type = "PANEL_OLED";
|
||||
/*low power control: dynamic power gating, ulps low power, analog bypass */
|
||||
pxlw,low-power = [01 01 02];
|
||||
/* virtual channel enable: PT, FRC */
|
||||
pxlw,virtual-channel-enable = [00 00];
|
||||
pxlw,virtual-channel-id = [00 02 03];
|
||||
pxlw,chip-ver = <0x6935>;
|
||||
pxlw,pkt-payload-size = <228>;
|
||||
pxlw,min-color-temp = <2500>;
|
||||
pxlw,max-color-temp = <10000>;
|
||||
/*first value represents lightup, second is pq update*/
|
||||
/*0: non-embedded, 1: embedded-no-ma, 2: embedded-ma*/
|
||||
pxlw,dsi-trans-mode = [00 01];
|
||||
/*the 3 groups represent 3 trans modes, non-embedded, embedded-no-ma, embedded-ma*/
|
||||
/*in non-embedded mode, the value must be a multiple of 256*/
|
||||
/*in embedded mode, the value must be a multiple of (pkt-payload-size + 8)*/
|
||||
pxlw,dsi-trans-len = <0x1000 0x400>, <0x0 0x0>, <0x0 0x0>;
|
||||
/* 0: DSI_VIDEO_MODE, 1: DSI_CMD_MODE */
|
||||
pxlw,iris-tx-mode = /bits/ 8 <1>;
|
||||
pxlw,panel-dimming-brightness = <4095>;
|
||||
pxlw,panel-te = <120>;
|
||||
pxlw,ap-te = <120>;
|
||||
pxlw,esd-ctrl = <7>;
|
||||
pxlw,timing-cmd-map = [02 01 00];
|
||||
pxlw,master-timing-cmd-map = [00 00 00];
|
||||
pxlw,frc-dsc-init-delay= <4047>;
|
||||
pxlw,cmd-param-from-firmware = <1>;
|
||||
pxlw,ocp_read_by_i2c = <1>;
|
||||
pxlw,iris-lightup-sequence-pre0= [
|
||||
/*sys*/
|
||||
00 a0 00
|
||||
00 00 00
|
||||
00 06 00
|
||||
];
|
||||
pxlw,iris-lightup-sequence-pre1= [
|
||||
/*sys*/
|
||||
00 a0 00
|
||||
00 00 00
|
||||
00 06 00
|
||||
];
|
||||
pxlw,iris-lightup-sequence-cont-splash= [
|
||||
/* rx ctrl */
|
||||
01 f0 00
|
||||
/* tx */
|
||||
02 01 00
|
||||
02 00 00
|
||||
/* dtg */
|
||||
05 00 00
|
||||
05 f0 00
|
||||
/*dport*/
|
||||
04 f0 00
|
||||
04 80 00
|
||||
/*pwil*/
|
||||
03 00 00
|
||||
03 01 00
|
||||
03 02 00
|
||||
03 03 00
|
||||
03 04 00
|
||||
03 80 00
|
||||
23 00 00
|
||||
23 80 00
|
||||
];
|
||||
pxlw,iris-lightup-sequence= [
|
||||
/* sys */
|
||||
00 f4 01
|
||||
/* rx ctrl */
|
||||
01 f0 01
|
||||
01 01 00
|
||||
01 02 01
|
||||
/* rx1 ctrl */
|
||||
21 f1 01
|
||||
21 f0 01
|
||||
/*tx*/
|
||||
02 01 01
|
||||
02 03 00
|
||||
02 04 01
|
||||
02 00 00
|
||||
/*dtg*/
|
||||
05 00 00
|
||||
05 f1 00
|
||||
05 f0 00
|
||||
/*gamma,65-bin*/
|
||||
86 00 01
|
||||
/*3dlut,17-bin*/
|
||||
81 02 01
|
||||
81 03 01
|
||||
81 04 01
|
||||
81 05 01
|
||||
81 06 01
|
||||
81 09 01
|
||||
81 0a 01
|
||||
81 0b 01
|
||||
81 0c 01
|
||||
81 0d 01
|
||||
/*dpp pre_lut*/
|
||||
92 10 01
|
||||
92 00 01
|
||||
/*dpp demura lut*/
|
||||
8d 00 01
|
||||
8d 10 01
|
||||
8d 20 01
|
||||
8d 30 01
|
||||
/* hdr lut */
|
||||
82 01 01
|
||||
82 11 01
|
||||
82 21 01
|
||||
82 31 01
|
||||
82 40 01
|
||||
82 50 01
|
||||
82 60 01
|
||||
82 70 01
|
||||
82 80 01
|
||||
82 90 01
|
||||
82 a0 01
|
||||
82 b0 01
|
||||
82 c0 01
|
||||
/*blending lut */
|
||||
93 00 01
|
||||
93 20 01
|
||||
93 30 01
|
||||
/* scaler1d filter lut */
|
||||
83 00 01
|
||||
83 40 01
|
||||
83 80 01
|
||||
83 c0 01
|
||||
8e 00 01
|
||||
8e 40 01
|
||||
8e 80 01
|
||||
8e c0 01
|
||||
8a 00 01
|
||||
8a 40 01
|
||||
8a 80 01
|
||||
8a c0 01
|
||||
8f 00 01
|
||||
8f 40 01
|
||||
8f 80 01
|
||||
8f c0 01
|
||||
/* SR filter */
|
||||
94 00 01
|
||||
/*dport*/
|
||||
04 f0 01
|
||||
04 e0 01
|
||||
04 80 00
|
||||
/*blending*/
|
||||
2e f0 01
|
||||
2e 40 01
|
||||
2e 50 01
|
||||
2e 60 01
|
||||
2e 90 01
|
||||
2e 80 01
|
||||
/* scaler1d */
|
||||
0b f0 01
|
||||
2f f0 01
|
||||
/* pwil */
|
||||
03 f0 01
|
||||
03 90 01
|
||||
03 d0 01
|
||||
03 a0 01
|
||||
03 60 01
|
||||
03 b0 01
|
||||
03 70 01
|
||||
03 50 01
|
||||
03 40 01
|
||||
03 81 01
|
||||
03 80 01
|
||||
03 c0 01
|
||||
03 df 01
|
||||
03 e0 01
|
||||
03 e3 01
|
||||
03 e1 01
|
||||
/* psr_mif */
|
||||
2d f0 01
|
||||
2d 80 01
|
||||
/* pwil_v11 */
|
||||
23 f0 01
|
||||
/* dsc dec aux */
|
||||
37 f0 01
|
||||
37 90 01
|
||||
37 80 00
|
||||
/* osd_comp */
|
||||
2a f0 01
|
||||
/* osd_decomp */
|
||||
2b f0 01
|
||||
/* dpp */
|
||||
0e f0 01
|
||||
0e 00 01
|
||||
0e 10 01
|
||||
0e 20 01
|
||||
0e 30 01
|
||||
0e 51 01
|
||||
0e 50 01
|
||||
0e 52 01
|
||||
0e 60 01
|
||||
0e 61 01
|
||||
0e 62 01
|
||||
0e 63 01
|
||||
0e 54 01
|
||||
0e 21 01
|
||||
0e 40 01
|
||||
0e 31 01
|
||||
0e 23 01
|
||||
0e 32 01
|
||||
0e 33 01
|
||||
0e 34 01
|
||||
0e a0 01
|
||||
0e 90 01
|
||||
0e 81 01
|
||||
/* dsc */
|
||||
07 f0 01
|
||||
07 90 01
|
||||
07 80 00
|
||||
08 f0 01
|
||||
08 f1 01
|
||||
08 a0 01
|
||||
08 b0 01
|
||||
24 f1 00
|
||||
25 f1 00
|
||||
26 f1 00
|
||||
38 f1 00
|
||||
39 f0 01
|
||||
/* ai */
|
||||
12 10 01
|
||||
12 20 01
|
||||
12 30 01
|
||||
12 40 01
|
||||
12 80 01
|
||||
/* hdr */
|
||||
09 00 01
|
||||
09 10 01
|
||||
09 20 01
|
||||
09 30 01
|
||||
09 40 01
|
||||
09 50 01
|
||||
09 60 01
|
||||
0a 50 01
|
||||
09 70 01
|
||||
09 90 01
|
||||
09 a0 01
|
||||
09 b0 01
|
||||
09 c0 01
|
||||
09 d0 01
|
||||
09 e0 01
|
||||
0a 00 01
|
||||
0a 10 01
|
||||
0a 20 01
|
||||
0a 30 01
|
||||
0a 40 01
|
||||
09 80 00
|
||||
/*DMA*/
|
||||
11 f0 01
|
||||
11 d0 01
|
||||
11 d1 01
|
||||
11 d2 01
|
||||
11 d3 01
|
||||
11 e1 00
|
||||
0e 80 01
|
||||
11 e9 00
|
||||
];
|
||||
pxlw,iris-fps-switch-sequence= [
|
||||
/* sys */
|
||||
00 f3 00
|
||||
/* mipi tx */
|
||||
//02 04 00
|
||||
/* blending */
|
||||
2e f0 00
|
||||
//2e 20 01
|
||||
/* dma */
|
||||
//11 e5 00
|
||||
];
|
||||
pxlw,iris-fps-clk-switch-sequence= [
|
||||
/* sys */
|
||||
00 a0 00
|
||||
00 f3 00
|
||||
00 f6 00
|
||||
/* mipi rx */
|
||||
01 01 00
|
||||
21 f1 01
|
||||
/* mipi tx */
|
||||
02 04 00
|
||||
/* blending */
|
||||
2e f0 00
|
||||
//2e 20 01
|
||||
/* dma */
|
||||
11 e1 00
|
||||
];
|
||||
pxlw,iris-pq-default-val= [
|
||||
/* sys */
|
||||
00 a0
|
||||
/* rx */
|
||||
01 e0
|
||||
/* tx */
|
||||
02 00
|
||||
/*DTG*/
|
||||
05 00
|
||||
05 f0
|
||||
/*DPORT*/
|
||||
04 f0
|
||||
04 80
|
||||
/* scaler1d */
|
||||
0b f0
|
||||
2f f0
|
||||
/* scaler1d filter lut */
|
||||
83 00
|
||||
83 40
|
||||
83 80
|
||||
83 c0
|
||||
8e 00
|
||||
8e 40
|
||||
8e 80
|
||||
8e c0
|
||||
8a 00
|
||||
8a 40
|
||||
8a 80
|
||||
8a c0
|
||||
8f 00
|
||||
8f 40
|
||||
8f 80
|
||||
8f c0
|
||||
/* SR filter */
|
||||
94 00
|
||||
/* blending */
|
||||
2e f0
|
||||
2e 40
|
||||
2e 50
|
||||
2e 60
|
||||
2e 90
|
||||
/* pwil */
|
||||
03 f0
|
||||
03 d0
|
||||
03 a0
|
||||
03 60
|
||||
03 b0
|
||||
03 70
|
||||
03 50
|
||||
03 40
|
||||
03 80
|
||||
/* dsc */
|
||||
07 f0
|
||||
07 90
|
||||
07 80
|
||||
08 f0
|
||||
08 f1
|
||||
08 a0
|
||||
08 b0
|
||||
24 f1
|
||||
25 f1
|
||||
26 f1
|
||||
/* dpp */
|
||||
0e 20
|
||||
0e 30
|
||||
0e 51
|
||||
0e 52
|
||||
0e 50
|
||||
0e 60
|
||||
0e 61
|
||||
0e 62
|
||||
0e 63
|
||||
0e 54
|
||||
0e 90
|
||||
81 00
|
||||
92 00
|
||||
86 00
|
||||
86 10
|
||||
86 20
|
||||
/* hdr */
|
||||
09 00
|
||||
09 10
|
||||
09 20
|
||||
09 30
|
||||
09 40
|
||||
09 50
|
||||
09 60
|
||||
09 70
|
||||
09 90
|
||||
09 a0
|
||||
09 b0
|
||||
09 c0
|
||||
09 d0
|
||||
0a 00
|
||||
0a 10
|
||||
0a 20
|
||||
0a 30
|
||||
0a 50
|
||||
/* hdr lut */
|
||||
82 01
|
||||
82 11
|
||||
/*dpp demura lut*/
|
||||
8d 00
|
||||
8d 10
|
||||
8d 20
|
||||
8d 30
|
||||
/* ai */
|
||||
12 10
|
||||
12 20
|
||||
];
|
||||
};
|
||||
};
|
||||
};
|
||||
129
qcom/display/oplus/pxlw-zonda/dsi-panel-pxlw.dtsi
Normal file
129
qcom/display/oplus/pxlw-zonda/dsi-panel-pxlw.dtsi
Normal file
@@ -0,0 +1,129 @@
|
||||
/* Copyright (c) 2020, Pixelworks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "pxlw-iris7-cfg-zonda-tianma-nt37705-1240-2772-dsc-cmd.dtsi"
|
||||
#include "dsi-panel-zonda-tianma-nt37705-1240-2772-dsc-cmd-2nd.dtsi"
|
||||
|
||||
&soc {
|
||||
dsi_iris_pwr_supply: dsi_iris_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "px_v18r";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <62000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* avoid failed to parse power config */
|
||||
dsi_panel_pwr_sec_supply: dsi_panel_pwr_sec_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "dummy";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <60700>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_oplus_boe_rm692e5_1080_2412_dsc_cmd {
|
||||
qcom,mdss-dsi-te-using-wd;
|
||||
pxlw,iris-chip-capability = <0x1 0x1 0x7 0x7f 0x1>;
|
||||
qcom,iris-supply-entries = <&dsi_iris_pwr_supply>;
|
||||
};
|
||||
|
||||
/* select panel */
|
||||
&mdss_mdp {
|
||||
pxlw,dsi-display-primary-active = "qcom,mdss_dsi_oplus_zonda_tianma_nt37705_1240_2772_dsc_cmd";
|
||||
pxlw,dsi-display-secondary-active = "qcom,mdss_dsi_panel_zonda_tianma_nt37705_1240_2772_dsc_cmd_2nd";
|
||||
pxlw,dsi-display-primary-active-2nd = "qcom,mdss_dsi_oplus_zonda_sec_tianma_nt37705_1240_2772_dsc_cmd";
|
||||
pxlw,dsi-display-secondary-active-2nd = "qcom,mdss_dsi_panel_zonda_tianma_nt37705_1240_2772_dsc_cmd_2nd";
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
pxlw,iris-lightup-config = <&mdss_iris_cfg_zonda_tianma_nt37705_1240_2772_dsc_cmd>;
|
||||
px_v18r-supply = <&L12B>;
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
px_v18r-supply = <&L12B>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
pxlw,iris-chip-capability = <0x1 0x1 0x7 0x3 0x1>;
|
||||
qcom,iris-supply-entries = <&dsi_iris_pwr_supply>;
|
||||
};
|
||||
|
||||
|
||||
&dsi_oplus_zonda_tianma_nt37705_1240_2772_dsc_cmd {
|
||||
pxlw,iris-chip-capability = <0x1 0x1 0x7 0x7f 0x1>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,iris-supply-entries = <&dsi_iris_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
};
|
||||
|
||||
&dsi_oplus_zonda_sec_tianma_nt37705_1240_2772_dsc_cmd {
|
||||
pxlw,iris-chip-capability = <0x1 0x1 0x7 0x7f 0x1>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,iris-supply-entries = <&dsi_iris_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 133 0>;
|
||||
};
|
||||
|
||||
&dsi_panel_zonda_tianma_nt37705_1240_2772_dsc_cmd_2nd {
|
||||
pxlw,iris-chip-capability = <0x1 0x1 0x7 0x7f 0x1>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_sec_supply>;
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@sdc_fhd_120 { /* FHD+ 120hz */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 1A 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@sdc_fhd_90 { /* FHD+ 90hz */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 1A 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@sdc_fhd_60 { /* FHD+ 60hz */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 1A 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
timing@sdc_fhd_144 { /* FHD+ 144hz */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2C 0C 0C 1D 1A 0C 0C 0B 02 04 00 24 11];
|
||||
qcom,display-topology = <1 1 1>,<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,241 @@
|
||||
/* Copyright (c) 2022, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_panel_zonda_tianma_nt37705_1240_2772_dsc_cmd_2nd: qcom,mdss_dsi_panel_zonda_tianma_nt37705_1240_2772_dsc_cmd_2nd {
|
||||
qcom,mdss-dsi-panel-name = "zonda tm nt37705 dsc cmd mode panel 2nd";
|
||||
oplus,mdss-dsi-vendor-name = "TM_NT37705 2nd";
|
||||
oplus,mdss-dsi-manufacture = "TM1240 2nd";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <30>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-loading-effect;
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 2>, <0 5>, <1 10>;
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-pan-physical-width-dimension = <70>;
|
||||
qcom,mdss-pan-physical-height-dimension = <155>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-lp11-init;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
/* HDR Setting */
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <5400000>;
|
||||
qcom,mdss-dsi-panel-average-brightness = <2000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <4000>;
|
||||
|
||||
//qcom,esd-check-enabled;
|
||||
//oplus,esd-check-flag-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [
|
||||
06 01 00 01 05 00 02 0A 00
|
||||
];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9C>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,dynamic-mode-switch-enabled;
|
||||
qcom,dynamic-mode-switch-type = "dynamic-resolution-switch-immediate";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@sdc_fhd_120{
|
||||
qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-mdp-transfer-time-us-min = <6000>;
|
||||
qcom,mdss-mdp-transfer-time-us-max = <7500>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsc-scr-version = <0x1>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1240>;
|
||||
qcom,mdss-dsi-panel-height = <2772>;
|
||||
|
||||
qcom,mdss-dsi-h-front-porch = <4>;
|
||||
qcom,mdss-dsi-h-back-porch = <4>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-v-back-porch = <2>;
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
|
||||
oplus,fod-on-vblank = <0>;
|
||||
oplus,fod-off-vblank = <0>;
|
||||
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <620>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@sdc_fhd_90{
|
||||
qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-mdp-transfer-time-us-min = <6000>;
|
||||
qcom,mdss-mdp-transfer-time-us-max = <7500>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsc-scr-version = <0x1>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1240>;
|
||||
qcom,mdss-dsi-panel-height = <2772>;
|
||||
|
||||
qcom,mdss-dsi-h-front-porch = <64>;
|
||||
qcom,mdss-dsi-h-back-porch = <49>;
|
||||
qcom,mdss-dsi-h-pulse-width = <8>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <8>;
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
oplus,fod-on-vblank = <0>;
|
||||
oplus,fod-off-vblank = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <620>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@sdc_fhd_60{
|
||||
qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-mdp-transfer-time-us-min = <6000>;
|
||||
qcom,mdss-mdp-transfer-time-us-max = <7500>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsc-scr-version = <0x1>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1240>;
|
||||
qcom,mdss-dsi-panel-height = <2772>;
|
||||
|
||||
qcom,mdss-dsi-h-front-porch = <64>;
|
||||
qcom,mdss-dsi-h-back-porch = <48>;
|
||||
qcom,mdss-dsi-h-pulse-width = <8>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <8>;
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
|
||||
oplus,fod-on-vblank = <0>;
|
||||
oplus,fod-off-vblank = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <620>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@sdc_fhd_144{
|
||||
qcom,mdss-mdp-transfer-time-us = <6000>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsc-scr-version = <0x1>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1363200000>;
|
||||
qcom,mdss-dsi-panel-width = <1240>;
|
||||
qcom,mdss-dsi-panel-height = <2772>;
|
||||
|
||||
qcom,mdss-dsi-h-front-porch = <64>;
|
||||
qcom,mdss-dsi-h-back-porch = <48>;
|
||||
qcom,mdss-dsi-h-pulse-width = <8>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <8>;
|
||||
qcom,mdss-dsi-v-front-porch = <2>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
oplus,fod-on-vblank = <0>;
|
||||
oplus,fod-off-vblank = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <620>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@raw_fhd_120 {
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
//qcom,mdss-dsi-panel-clockrate = <1320000000>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <1660>;
|
||||
qcom,mdss-dsi-h-front-porch = <4>;
|
||||
qcom,mdss-dsi-h-back-porch = <4>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <2>;
|
||||
qcom,mdss-dsi-v-back-porch = <2>;
|
||||
qcom,mdss-dsi-v-front-porch = <15>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1440000000>;
|
||||
qcom,mdss-mdp-transfer-time-us = <7468>; //same as main panel
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2E 0C 0C 1D 1B 0C 0D 0B 02 04 00 25 11];
|
||||
qcom,display-topology = <1 0 1>,<2 0 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,408 @@
|
||||
/*Fullchip
|
||||
|
||||
//dtype, last, wait, ip, opt, dlen
|
||||
//sys*/
|
||||
//commit: b87c0b361dd272e250768a39e6fc173966be32c6
|
||||
//build : 2023-03-27 16:22:37
|
||||
&soc {
|
||||
pxlw {
|
||||
mdss_iris_cfg_zonda_tianma_nt37705_1240_2772_dsc_cmd: pxlw,mdss_iris_cfg_zonda_tianma_nt37705_1240_2772_dsc_cmd {
|
||||
pxlw,platform = <1>;
|
||||
pxlw,panel-type = "PANEL_OLED";
|
||||
/*low power control: dynamic power gating, ulps low power, analog bypass */
|
||||
pxlw,low-power = [01 01 02];
|
||||
/* virtual channel enable: PT, FRC */
|
||||
pxlw,virtual-channel-enable = [00 00];
|
||||
pxlw,virtual-channel-id = [00 02 03];
|
||||
pxlw,chip-ver = <0x6935>;
|
||||
pxlw,pkt-payload-size = <228>;
|
||||
pxlw,min-color-temp = <2500>;
|
||||
pxlw,max-color-temp = <10000>;
|
||||
/*first value represents lightup, second is pq update*/
|
||||
/*0: non-embedded, 1: embedded-no-ma, 2: embedded-ma*/
|
||||
pxlw,dsi-trans-mode = [00 01];
|
||||
/*the 3 groups represent 3 trans modes, non-embedded, embedded-no-ma, embedded-ma*/
|
||||
/*in non-embedded mode, the value must be a multiple of 256*/
|
||||
/*in embedded mode, the value must be a multiple of (pkt-payload-size + 8)*/
|
||||
pxlw,dsi-trans-len = <0x1000 0x400>, <0x0 0x0>, <0x0 0x0>;
|
||||
/* 0: DSI_VIDEO_MODE, 1: DSI_CMD_MODE */
|
||||
pxlw,iris-tx-mode = /bits/ 8 <1>;
|
||||
pxlw,panel-dimming-brightness = <4095>;
|
||||
pxlw,panel-te = <60>;
|
||||
pxlw,ap-te = <60>;
|
||||
pxlw,esd-ctrl = <7>;
|
||||
pxlw,timing-cmd-map = [02 01 00 03 FF];
|
||||
pxlw,master-timing-cmd-map = [00 00 00 00 00];
|
||||
pxlw,frc-dsc-init-delay= <4047>;
|
||||
pxlw,cmd-param-from-firmware = <1>;
|
||||
pxlw,ocp_read_by_i2c = <1>;
|
||||
pxlw,iris-lightup-sequence-pre0= [
|
||||
/*sys*/
|
||||
00 a0 00
|
||||
00 00 00
|
||||
00 06 00
|
||||
];
|
||||
pxlw,iris-lightup-sequence-pre1= [
|
||||
/*sys*/
|
||||
00 a0 00
|
||||
00 00 00
|
||||
00 06 00
|
||||
];
|
||||
pxlw,iris-lightup-sequence-cont-splash= [
|
||||
/* rx ctrl */
|
||||
01 f0 00
|
||||
/* tx */
|
||||
02 01 00
|
||||
02 00 00
|
||||
/* dtg */
|
||||
05 00 00
|
||||
05 f0 00
|
||||
/*dport*/
|
||||
04 f0 00
|
||||
04 80 00
|
||||
/*pwil*/
|
||||
03 00 00
|
||||
03 01 00
|
||||
03 02 00
|
||||
03 03 00
|
||||
03 04 00
|
||||
03 80 00
|
||||
23 00 00
|
||||
23 80 00
|
||||
];
|
||||
pxlw,iris-lightup-sequence= [
|
||||
/* sys */
|
||||
00 f4 01
|
||||
/* rx ctrl */
|
||||
01 f0 01
|
||||
01 01 00
|
||||
01 02 01
|
||||
/* rx1 ctrl */
|
||||
21 f1 01
|
||||
21 f0 01
|
||||
/*tx*/
|
||||
02 01 01
|
||||
02 03 00
|
||||
02 04 01
|
||||
02 00 00
|
||||
/*dtg*/
|
||||
05 00 00
|
||||
05 f1 00
|
||||
05 f0 00
|
||||
/*gamma,65-bin*/
|
||||
86 00 01
|
||||
/*3dlut,17-bin*/
|
||||
81 01 01
|
||||
81 04 01
|
||||
81 05 01
|
||||
81 06 01
|
||||
81 08 01
|
||||
81 09 01
|
||||
81 0a 01
|
||||
81 0b 01
|
||||
81 0c 01
|
||||
81 0d 01
|
||||
/*dpp pre_lut*/
|
||||
92 10 01
|
||||
92 00 01
|
||||
/*dpp demura lut*/
|
||||
8d 00 01
|
||||
8d 10 01
|
||||
8d 20 01
|
||||
8d 30 01
|
||||
/* hdr lut */
|
||||
82 01 01
|
||||
82 11 01
|
||||
82 21 01
|
||||
82 31 01
|
||||
82 40 01
|
||||
82 50 01
|
||||
82 60 01
|
||||
82 70 01
|
||||
82 80 01
|
||||
82 90 01
|
||||
82 a0 01
|
||||
82 b0 01
|
||||
82 c0 01
|
||||
/*blending lut */
|
||||
93 00 01
|
||||
93 20 01
|
||||
93 30 01
|
||||
/* scaler1d filter lut */
|
||||
83 00 01
|
||||
83 40 01
|
||||
83 80 01
|
||||
83 c0 01
|
||||
8e 00 01
|
||||
8e 40 01
|
||||
8e 80 01
|
||||
8e c0 01
|
||||
8a 00 01
|
||||
8a 40 01
|
||||
8a 80 01
|
||||
8a c0 01
|
||||
8f 00 01
|
||||
8f 40 01
|
||||
8f 80 01
|
||||
8f c0 01
|
||||
/* SR filter */
|
||||
94 00 01
|
||||
/*dport*/
|
||||
04 f0 01
|
||||
04 e0 01
|
||||
04 80 00
|
||||
/*blending*/
|
||||
2e f0 01
|
||||
2e 40 01
|
||||
2e 50 01
|
||||
2e 60 01
|
||||
2e 90 01
|
||||
2e 80 01
|
||||
/* scaler1d */
|
||||
0b f0 01
|
||||
2f f0 01
|
||||
/* pwil */
|
||||
03 f0 01
|
||||
03 90 01
|
||||
03 d0 01
|
||||
03 a0 01
|
||||
03 60 01
|
||||
03 b0 01
|
||||
03 70 01
|
||||
03 50 01
|
||||
03 40 01
|
||||
03 81 01
|
||||
03 80 01
|
||||
03 c0 01
|
||||
03 df 01
|
||||
03 e0 01
|
||||
03 e3 01
|
||||
03 e1 01
|
||||
/* psr_mif */
|
||||
2d f0 01
|
||||
2d 80 01
|
||||
/* pwil_v11 */
|
||||
23 f0 01
|
||||
/* dsc dec aux */
|
||||
37 f0 01
|
||||
37 90 01
|
||||
37 80 00
|
||||
/* osd_comp */
|
||||
2a f0 01
|
||||
/* osd_decomp */
|
||||
2b f0 01
|
||||
/* dpp */
|
||||
0e f0 01
|
||||
0e 00 01
|
||||
0e 10 01
|
||||
0e 20 01
|
||||
0e 30 01
|
||||
0e 51 01
|
||||
0e 50 01
|
||||
0e 52 01
|
||||
0e 60 01
|
||||
0e 61 01
|
||||
0e 62 01
|
||||
0e 63 01
|
||||
0e 54 01
|
||||
0e 21 01
|
||||
0e 40 01
|
||||
0e 31 01
|
||||
0e 23 01
|
||||
0e 32 01
|
||||
0e 33 01
|
||||
0e 34 01
|
||||
0e a0 01
|
||||
0e 90 01
|
||||
0e 81 01
|
||||
/* dsc */
|
||||
07 f0 01
|
||||
07 90 01
|
||||
07 80 00
|
||||
08 f0 01
|
||||
08 f1 01
|
||||
08 a0 01
|
||||
08 b0 01
|
||||
24 f1 00
|
||||
25 f1 00
|
||||
26 f1 00
|
||||
38 f1 00
|
||||
39 f0 01
|
||||
/* ai */
|
||||
12 10 01
|
||||
12 20 01
|
||||
12 30 01
|
||||
12 40 01
|
||||
12 80 01
|
||||
/* hdr */
|
||||
09 00 01
|
||||
09 10 01
|
||||
09 20 01
|
||||
09 30 01
|
||||
09 40 01
|
||||
09 50 01
|
||||
09 60 01
|
||||
0a 50 01
|
||||
09 70 01
|
||||
09 90 01
|
||||
09 a0 01
|
||||
09 b0 01
|
||||
09 c0 01
|
||||
09 d0 01
|
||||
09 e0 01
|
||||
0a 00 01
|
||||
0a 10 01
|
||||
0a 20 01
|
||||
0a 30 01
|
||||
0a 40 01
|
||||
09 80 00
|
||||
/*DMA*/
|
||||
11 f0 01
|
||||
11 d0 01
|
||||
11 d1 01
|
||||
11 d2 01
|
||||
11 d3 01
|
||||
11 e1 00
|
||||
0e 80 01
|
||||
11 e9 00
|
||||
];
|
||||
pxlw,iris-fps-switch-sequence= [
|
||||
/* sys */
|
||||
00 f3 00
|
||||
/* mipi tx */
|
||||
//02 04 00
|
||||
/* blending */
|
||||
2e f0 00
|
||||
//2e 20 01
|
||||
/* dma */
|
||||
//11 e5 00
|
||||
];
|
||||
pxlw,iris-fps-clk-switch-sequence= [
|
||||
/* sys */
|
||||
00 a0 00
|
||||
00 f3 00
|
||||
00 f6 00
|
||||
/* mipi rx */
|
||||
01 01 00
|
||||
21 f1 01
|
||||
/* mipi tx */
|
||||
02 04 00
|
||||
/* blending */
|
||||
2e f0 00
|
||||
//2e 20 01
|
||||
/* dma */
|
||||
11 e1 00
|
||||
];
|
||||
pxlw,iris-pq-default-val= [
|
||||
/* sys */
|
||||
00 a0
|
||||
/* rx */
|
||||
01 e0
|
||||
/* tx */
|
||||
02 00
|
||||
/*DTG*/
|
||||
05 00
|
||||
05 f0
|
||||
/*DPORT*/
|
||||
04 f0
|
||||
04 80
|
||||
/* scaler1d */
|
||||
0b f0
|
||||
2f f0
|
||||
/* scaler1d filter lut */
|
||||
83 00
|
||||
83 40
|
||||
83 80
|
||||
83 c0
|
||||
8e 00
|
||||
8e 40
|
||||
8e 80
|
||||
8e c0
|
||||
8a 00
|
||||
8a 40
|
||||
8a 80
|
||||
8a c0
|
||||
8f 00
|
||||
8f 40
|
||||
8f 80
|
||||
8f c0
|
||||
/* SR filter */
|
||||
94 00
|
||||
/* blending */
|
||||
2e f0
|
||||
2e 40
|
||||
2e 50
|
||||
2e 60
|
||||
2e 90
|
||||
/* pwil */
|
||||
03 f0
|
||||
03 d0
|
||||
03 a0
|
||||
03 60
|
||||
03 b0
|
||||
03 70
|
||||
03 50
|
||||
03 40
|
||||
03 80
|
||||
/* dsc */
|
||||
07 f0
|
||||
07 90
|
||||
07 80
|
||||
08 f0
|
||||
08 f1
|
||||
08 a0
|
||||
08 b0
|
||||
24 f1
|
||||
25 f1
|
||||
26 f1
|
||||
/* dpp */
|
||||
0e 20
|
||||
0e 30
|
||||
0e 51
|
||||
0e 52
|
||||
0e 50
|
||||
0e 60
|
||||
0e 61
|
||||
0e 62
|
||||
0e 63
|
||||
0e 54
|
||||
0e 90
|
||||
81 00
|
||||
92 00
|
||||
86 00
|
||||
86 10
|
||||
86 20
|
||||
/* hdr */
|
||||
09 00
|
||||
09 10
|
||||
09 20
|
||||
09 30
|
||||
09 40
|
||||
09 50
|
||||
09 60
|
||||
09 70
|
||||
09 90
|
||||
09 a0
|
||||
09 b0
|
||||
09 c0
|
||||
09 d0
|
||||
0a 00
|
||||
0a 10
|
||||
0a 20
|
||||
0a 30
|
||||
0a 50
|
||||
/* hdr lut */
|
||||
82 01
|
||||
82 11
|
||||
/*dpp demura lut*/
|
||||
8d 00
|
||||
8d 10
|
||||
8d 20
|
||||
8d 30
|
||||
/* ai */
|
||||
12 10
|
||||
12 20
|
||||
];
|
||||
};
|
||||
};
|
||||
};
|
||||
33
qcom/display/oplus/xigua-22851-display-kalama-overlay.dts
Normal file
33
qcom/display/oplus/xigua-22851-display-kalama-overlay.dts
Normal file
@@ -0,0 +1,33 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
#include <dt-bindings/oplus/hw-id.h>
|
||||
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h>
|
||||
#include "../display/kalama-sde-display-mtp-overlay.dts"
|
||||
#include "kalama-display-overlay-common.dtsi"
|
||||
#include "xigua-22851-display-kalama-overlay.dtsi"
|
||||
/* #if defined(CONFIG_PXLW_IRIS) */
|
||||
#include "pxlw-iris7-kalama-common.dtsi"
|
||||
#include "pxlw-xigua/dsi-panel-pxlw.dtsi"
|
||||
/* #endif */
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama MTP,xigua";
|
||||
|
||||
oplus,project-id = <22851>;
|
||||
};
|
||||
|
||||
/*Adapt parameters to obtain screen temperature*/
|
||||
&pmk8550_vadc {
|
||||
disp0_con_therm_adc {
|
||||
reg = <PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU>;
|
||||
label = "disp0_con_therm_adc";
|
||||
qcom,pre-scaling = <1 1>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dsi{
|
||||
io-channels = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU>;
|
||||
io-channel-names = "disp0_con_therm_adc";
|
||||
};
|
||||
91
qcom/display/oplus/xigua-22851-display-kalama-overlay.dtsi
Normal file
91
qcom/display/oplus/xigua-22851-display-kalama-overlay.dtsi
Normal file
@@ -0,0 +1,91 @@
|
||||
/* add for custom clk by gpio5 */
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include "panel/dsi-panel-AA536-P-3-A0001-dsc-cmd.dtsi"
|
||||
|
||||
&soc {
|
||||
oplus_display_dev: oplus,dsi-display-dev {
|
||||
oplus,dsi-panel-primary = <
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_panel_AA536_P_3_A0001_dsc_cmd
|
||||
>;
|
||||
oplus,dsi-panel-secondary = <
|
||||
>;
|
||||
oplus,dsi-panel-extended = <>;
|
||||
};
|
||||
|
||||
oplus_xigua_dsi_panel_pwr_supply: oplus_xigua_dsi_panel_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <200000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <2>;
|
||||
qcom,supply-pre-off-sleep = <23>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "vci";
|
||||
qcom,supply-min-voltage = <3000000>;
|
||||
qcom,supply-max-voltage = <3000000>;
|
||||
qcom,supply-enable-load = <10000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
qcom,supply-pre-on-sleep = <2>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
qcom,supply-pre-off-sleep = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,platform-te-gpio-1 = <&tlmm 87 0>;
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend",
|
||||
"te1_active", "te1_suspend";
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
|
||||
pinctrl-2 = <&sde_te1_active>;
|
||||
pinctrl-3 = <&sde_te1_suspend>;
|
||||
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 2>,
|
||||
<&mdss_dsi_phy1 3>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
/* add for custom clk by gpio5 */
|
||||
<&rpmhcc RPMH_DIV_CLK1>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1",
|
||||
"mdp_core_clk",
|
||||
/* add for custom clk by gpio5 */
|
||||
"div_clk";
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_te1_active>;
|
||||
pinctrl-1 = <&sde_te1_suspend>;
|
||||
|
||||
/delete-property/ vddio-supply;
|
||||
/delete-property/ vci-supply;
|
||||
/delete-property/ vdd-supply;
|
||||
};
|
||||
&mdss_dsi_phy0 {
|
||||
/delete-property/ qcom,dsi-pll-ssc-en;
|
||||
/delete-property/ qcom,dsi-pll-ssc-mode;
|
||||
};
|
||||
|
||||
&mdss_dsi_phy1 {
|
||||
/delete-property/ qcom,dsi-pll-ssc-en;
|
||||
/delete-property/ qcom,dsi-pll-ssc-mode;
|
||||
};
|
||||
|
||||
&L13B {
|
||||
regulator-max-microvolt = <3200000>;
|
||||
qcom,init-voltage = <3000000>;
|
||||
};
|
||||
@@ -1,15 +1,19 @@
|
||||
#include "panel/dsi-panel-boe-nt37705-1116-2484-dsc-cmd.dtsi"
|
||||
#include "panel/dsi-panel-boe-nt37900-2440-2268-dsc-cmd.dtsi"
|
||||
#include "panel/dsi-panel-AC052-S-3-A0001-dsc-cmd.dtsi"
|
||||
#include "panel/dsi-panel-AC052-P-3-A0003-dsc-cmd.dtsi"
|
||||
#include "panel/dsi-panel-AC052-P-1-A0002-dsc-cmd.dtsi"
|
||||
#include "panel/dsi-panel-AC052-P-3-A0003-dsc-cmd-pvt.dtsi"
|
||||
|
||||
&soc {
|
||||
oplus_display_dev: oplus,dsi-display-dev {
|
||||
oplus,dsi-panel-primary = <
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_panel_boe_nt37900_2440_2268_dsc_cmd
|
||||
&dsi_panel_AC052_P_3_A0003_dsc_cmd
|
||||
&dsi_panel_AC052_P_1_A0002_dsc_cmd
|
||||
&dsi_panel_AC052_P_3_A0003_dsc_cmd_pvt
|
||||
>;
|
||||
oplus,dsi-panel-secondary = <
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_panel_boe_nt37705_1116_2484_dsc_cmd
|
||||
&dsi_panel_AC052_S_3_A0001_dsc_cmd
|
||||
>;
|
||||
oplus,dsi-panel-extended = <>;
|
||||
};
|
||||
@@ -139,4 +143,4 @@
|
||||
function = "gpio";
|
||||
power-source = <1>; /* 1.8V */
|
||||
};
|
||||
};
|
||||
};
|
||||
33
qcom/display/oplus/zonda-22635-display-kalama-overlay.dts
Normal file
33
qcom/display/oplus/zonda-22635-display-kalama-overlay.dts
Normal file
@@ -0,0 +1,33 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
#include <dt-bindings/oplus/hw-id.h>
|
||||
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h>
|
||||
#include "../display/kalama-sde-display-mtp-overlay.dts"
|
||||
#include "kalama-display-overlay-common.dtsi"
|
||||
#include "zonda-22635-display-kalama-overlay.dtsi"
|
||||
/* #if defined(CONFIG_PXLW_IRIS) */
|
||||
#include "pxlw-iris7-kalama-common.dtsi"
|
||||
#include "pxlw-zonda/dsi-panel-pxlw.dtsi"
|
||||
/* #endif */
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama MTP,zonda";
|
||||
|
||||
oplus,project-id = <22635 22714 23603 23667>;
|
||||
};
|
||||
|
||||
/*Adapt parameters to obtain screen temperature*/
|
||||
&pmk8550_vadc {
|
||||
disp0_con_therm_adc {
|
||||
reg = <PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU>;
|
||||
label = "disp0_con_therm_adc";
|
||||
qcom,pre-scaling = <1 1>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dsi{
|
||||
io-channels = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU>;
|
||||
io-channel-names = "disp0_con_therm_adc";
|
||||
};
|
||||
79
qcom/display/oplus/zonda-22635-display-kalama-overlay.dtsi
Normal file
79
qcom/display/oplus/zonda-22635-display-kalama-overlay.dtsi
Normal file
@@ -0,0 +1,79 @@
|
||||
/* add for custom clk by gpio5 */
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include "panel/dsi-panel-oplus-zonda-tianma-nt37705-1240-2772-dsc-cmd.dtsi"
|
||||
#include "panel/dsi-panel-oplus-zonda-sec-tianma-nt37705-1240-2772-dsc-cmd.dtsi"
|
||||
#include "panel/dsi_panel_oplus_boe_rm692e5_1080_2412_dsc_cmd.dtsi"
|
||||
|
||||
&soc {
|
||||
oplus_display_dev: oplus,dsi-display-dev {
|
||||
oplus,dsi-panel-primary = <
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_oplus_boe_rm692e5_1080_2412_dsc_cmd
|
||||
&dsi_oplus_zonda_tianma_nt37705_1240_2772_dsc_cmd
|
||||
&dsi_oplus_zonda_sec_tianma_nt37705_1240_2772_dsc_cmd
|
||||
>;
|
||||
oplus,dsi-panel-secondary = <
|
||||
>;
|
||||
oplus,dsi-panel-extended = <>;
|
||||
};
|
||||
|
||||
oplus_zonda_dsi_panel_pwr_supply: oplus_zonda_dsi_panel_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <200000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <1>;
|
||||
qcom,supply-pre-off-sleep = <30>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@2 {
|
||||
reg = <2>;
|
||||
qcom,supply-name = "vci";
|
||||
qcom,supply-min-voltage = <3000000>;
|
||||
qcom,supply-max-voltage = <3000000>;
|
||||
qcom,supply-enable-load = <2000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
qcom,supply-post-on-sleep = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,platform-te-gpio-1 = <&tlmm 87 0>;
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend",
|
||||
"te1_active", "te1_suspend";
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
|
||||
pinctrl-2 = <&sde_te1_active>;
|
||||
pinctrl-3 = <&sde_te1_suspend>;
|
||||
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 2>,
|
||||
<&mdss_dsi_phy1 3>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
/* add for custom clk by gpio5 */
|
||||
<&rpmhcc RPMH_DIV_CLK1>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1",
|
||||
"mdp_core_clk",
|
||||
/* add for custom clk by gpio5 */
|
||||
"div_clk";
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_te1_active>;
|
||||
pinctrl-1 = <&sde_te1_suspend>;
|
||||
|
||||
/delete-property/ vddio-supply;
|
||||
/delete-property/ vci-supply;
|
||||
/delete-property/ vdd-supply;
|
||||
};
|
||||
Reference in New Issue
Block a user