Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: msm: Add idle states and soc sleep stats for sm6150

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Add various CPU idle states and soc sleep stats device.

Change-Id: I57081c20790af6caccb0fba244dcbab7823c6338
This commit is contained in:
Maulik Shah
2022-03-31 20:52:30 +05:30
committed by Gerrit - the friendly Code Review server
parent 1ef2c7fd94
commit 1fafdf745b
1 changed files with 147 additions and 0 deletions
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147
qcom/sm6150.dtsi
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@@ -26,6 +26,9 @@
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
@@ -49,6 +52,9 @@
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
@@ -67,6 +73,9 @@
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
@@ -84,6 +93,9 @@
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
@@ -101,6 +113,9 @@
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
@@ -118,6 +133,9 @@
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
@@ -135,6 +153,9 @@
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
capacity-dmips-mhz = <1740>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
@@ -152,6 +173,9 @@
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
capacity-dmips-mhz = <1740>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
@@ -204,9 +228,123 @@
};
};
idle-states {
SILVER_OFF: silver-c3 { /* C3 */
compatible = "arm,idle-state";
idle-state-name = "pc";
entry-latency-us = <549>;
exit-latency-us = <901>;
min-residency-us = <1774>;
arm,psci-suspend-param = <0x40000003>;
local-timer-stop;
};
SILVER_PLL_OFF: silver-c4 { /* C4 */
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <702>;
exit-latency-us = <915>;
min-residency-us = <4001>;
arm,psci-suspend-param = <0x40000004>;
local-timer-stop;
};
GOLD_OFF: gold-c3 { /* C3 */
compatible = "arm,idle-state";
idle-state-name = "pc";
entry-latency-us = <523>;
exit-latency-us = <1244>;
min-residency-us = <2207>;
arm,psci-suspend-param = <0x40000003>;
local-timer-stop;
};
GOLD_RAIL_OFF: gold-c4 { /* C4 */
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <526>;
exit-latency-us = <1854>;
min-residency-us = <5555>;
arm,psci-suspend-param = <0x40000004>;
local-timer-stop;
};
CLUSTER_OFF: cluster-d4 { /* D4 */
compatible = "domain-idle-state";
idle-state-name = "llcc-off";
entry-latency-us = <2752>;
exit-latency-us = <3048>;
min-residency-us = <6118>;
arm,psci-suspend-param = <0x41000044>;
};
CX_RET: cx-ret { /* Cx Ret */
compatible = "domain-idle-state";
idle-state-name = "llcc-off";
entry-latency-us = <3263>;
exit-latency-us = <4562>;
min-residency-us = <8467>;
arm,psci-suspend-param = <0x41001344>;
};
APSS_OFF: cluster-e3 { /* AOSS sleep */
compatible = "domain-idle-state";
idle-state-name = "llcc-off";
entry-latency-us = <3638>;
exit-latency-us = <6562>;
min-residency-us = <9826>;
arm,psci-suspend-param = <0x4100b344>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu-pd0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD1: cpu-pd1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD2: cpu-pd2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD3: cpu-pd3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD4: cpu-pd4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD5: cpu-pd5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD6: cpu-pd6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD7: cpu-pd7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CLUSTER_PD: cluster-pd {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_OFF &CX_RET &APSS_OFF>;
};
};
chosen { };
@@ -422,6 +560,7 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&CLUSTER_PD>;
apps_rsc_drv2: drv@2 {
qcom,drv-id = <2>;
@@ -573,6 +712,14 @@
status = "ok";
};
};
soc-sleep-stats@c3f0000 {
compatible = "qcom,rpmh-sleep-stats-legacy";
reg = <0xc3f0000 0x400>;
ss-name = "modem", "adsp", "adsp_island",
"cdsp", "slpi", "slpi_island",
"apss";
};
};
#include "sm6150-pinctrl.dtsi"