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Add 'qcom/mmrm/' from commit 'a53e8c9dcd51e716d41a4b89051b8f91d9cefe2b'

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git-subtree-dir: qcom/mmrm
git-subtree-mainline: 2c4116e901
git-subtree-split: a53e8c9dcd
This commit is contained in:
Bruno Martins
2023-09-14 09:56:16 +01:00
parent 2c4116e901 a53e8c9dcd
commit 2acdfb55cb
26 changed files with 964 additions and 0 deletions
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28
qcom/mmrm/Kbuild Normal file
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ifeq ($(CONFIG_ARCH_KALAMA), y)
ifneq ($(CONFIG_ARCH_QTI_VM), y)
dtbo-y += kalama-mmrm.dtbo
dtbo-y += kalama-mmrm-test.dtbo
dtbo-y += kalama-mmrm-v2.dtbo
dtbo-y += kalama-mmrm-test-v2.dtbo
ifeq ($(CONFIG_MSM_MMRM_VM),y)
dtbo-y += kalama-mmrm-vm-be.dtbo
endif
else
ifeq ($(CONFIG_MSM_MMRM_VM),y)
dtbo-y += kalama-mmrm-vm-fe.dtbo
dtbo-y += kalama-mmrm-vm-fe-test.dtbo
endif
endif
endif
ifeq ($(CONFIG_ARCH_WAIPIO), y)
dtbo-y += waipio-mmrm.dtbo
dtbo-y += waipio-mmrm-test.dtbo
dtbo-y += waipio-v2-mmrm.dtbo
dtbo-y += waipio-v2-mmrm-test.dtbo
endif
always-y := $(dtb-y) $(dtbo-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb *.dtbo

9
qcom/mmrm/Makefile Normal file
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KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
all: dtbs
clean:
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
%:
$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)

32
qcom/mmrm/bindings/msm-mmrm-test.txt Normal file
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* Qualcomm Technologies, Inc. MSM MMRM
[Root level node]
MMRM
=====
Required properties:
- compatible : one of:
- "qcom,msm-mmrm-test"
- "qcom,waipio-mmrm-test" : Invokes driver specific data for Waipio.
- clock-names: an array of clocks that the driver uses for testing.
The clocks names here correspond to the clock names used in
clk_get.
- clocks: Must contain an entry for each clock in clock-names.
Example:
qcom,mmrm-test {
compatible = "qcom,msm-mmrm-test";
clock-names =
"cam_cc_ife_0_clk_src",
"cam_cc_ife_1_clk_src",
"video_cc_mvs1_clk_src",
"disp_cc_mdss_mdp_clk_src",
"video_cc_mvs0_clk_src";
clocks =
<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
<&clock_videocc VIDEO_CC_MVS1_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&clock_videocc VIDEO_CC_MVS0_CLK_SRC>;
};

35
qcom/mmrm/bindings/msm-mmrm.txt Normal file
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* Qualcomm Technologies, Inc. MSM MMRM
[Root level node]
MMRM
=====
Required properties:
- compatible : one of:
- "qcom,msm-mmrm"
- "qcom,waipio-mmrm" : Invokes driver specific data for Waipio.
Optional properties:
- mm-rail-corners : an array of voltage corner names supported by driver.
- mm-rail-fact-volt : an array of voltage coner factors corresponding to
voltage corners supported by driver for a chipset.
- scaling-fact-dyn : an array of dynamic scaling factors corresponding to
voltage corners supported by driver for a chipset.
- scaling-fact-leak: an array of leakage scaling factors corresponding to
voltage corners supported by driver for a chipset.
- client-info : an array of information for each clock source. Each entry
includes client domain, clk src id & corresponding power factors.
Example:
qcom,mmrm {
compatible = "qcom,msm-mmrm";
mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
mm-rail-fact-volt = <36439 41157 44827 49152 54526>;
/* Scaling factors */
scaling-fact-dyn = <35390 45876 54395 66192 82576>;
scaling-fact-leak = <451544 548537 633078 746456 920126>;
client-info =
<0x4 VIDEO_CC_MVS0_CLK_SRC 28970189 582288>;
};

15
qcom/mmrm/kalama-mmrm-test-v2.dts Normal file
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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-kalama.h>
#include <dt-bindings/clock/qcom,videocc-kalama.h>
#include <dt-bindings/clock/qcom,dispcc-kalama.h>
#include "kalama-mmrm-test-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kalama v2 SoC";
compatible = "qcom,kalama";
qcom,msm-id = <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

109
qcom/mmrm/kalama-mmrm-test-v2.dtsi Normal file
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&soc {
msm_mmrm_test: qcom,mmrm-test {
compatible = "qcom,msm-mmrm-test", "qcom,kalama-mmrm-test";
status = "disable";
/* Clock info */
clock-names =
"cam_cc_ife_0_clk_src",
"cam_cc_ife_1_clk_src",
"cam_cc_ife_2_clk_src",
"cam_cc_csid_clk_src",
"cam_cc_sfe_0_clk_src",
"cam_cc_sfe_1_clk_src",
"cam_cc_ipe_nps_clk_src",
"cam_cc_bps_clk_src",
"cam_cc_ife_lite_clk_src",
"cam_cc_jpeg_clk_src",
"cam_cc_camnoc_axi_clk_src",
"cam_cc_ife_lite_csid_clk_src",
"cam_cc_icp_clk_src",
"cam_cc_cphy_rx_clk_src",
"cam_cc_csi0phytimer_clk_src",
"cam_cc_csi1phytimer_clk_src",
"cam_cc_csi2phytimer_clk_src",
"cam_cc_csi3phytimer_clk_src",
"cam_cc_csi4phytimer_clk_src",
"cam_cc_csi5phytimer_clk_src",
"cam_cc_csi6phytimer_clk_src",
"cam_cc_csi7phytimer_clk_src",
"cam_cc_cci_0_clk_src",
"cam_cc_cci_1_clk_src",
"cam_cc_cci_2_clk_src",
"cam_cc_slow_ahb_clk_src",
"cam_cc_fast_ahb_clk_src",
"cam_cc_cre_clk_src",
"video_cc_mvs1_clk_src",
"disp_cc_mdss_mdp_clk_src",
"disp_cc_mdss_dptx0_link_clk_src",
"video_cc_mvs0_clk_src";
clocks =
<&camcc CAM_CC_IFE_0_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CLK_SRC>,
<&camcc CAM_CC_CSID_CLK_SRC>,
<&camcc CAM_CC_SFE_0_CLK_SRC>,
<&camcc CAM_CC_SFE_1_CLK_SRC>,
<&camcc CAM_CC_IPE_NPS_CLK_SRC>,
<&camcc CAM_CC_BPS_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_JPEG_CLK_SRC>,
<&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&camcc CAM_CC_ICP_CLK_SRC>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI6PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI7PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CCI_0_CLK_SRC>,
<&camcc CAM_CC_CCI_1_CLK_SRC>,
<&camcc CAM_CC_CCI_2_CLK_SRC>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&camcc CAM_CC_CRE_CLK_SRC>,
<&videocc VIDEO_CC_MVS1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&videocc VIDEO_CC_MVS0_CLK_SRC>;
clock_rates =
<0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_SFE_1_CLK_SRC 364000000 500000000 600000000 700000000 700000000>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>,
<0x1 CAM_CC_CRE_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>;
};
};

15
qcom/mmrm/kalama-mmrm-test.dts Normal file
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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-kalama.h>
#include <dt-bindings/clock/qcom,videocc-kalama.h>
#include <dt-bindings/clock/qcom,dispcc-kalama.h>
#include "kalama-mmrm-test.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kalama v1 SoC";
compatible = "qcom,kalama";
qcom,msm-id = <519 0x10000>, <536 0x10000>, <600 0x10000>, <601 0x10000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

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qcom/mmrm/kalama-mmrm-test.dtsi Normal file
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&soc {
msm_mmrm_test: qcom,mmrm-test {
compatible = "qcom,msm-mmrm-test", "qcom,kalama-mmrm-test";
status = "disable";
/* Clock info */
clock-names =
"cam_cc_ife_0_clk_src",
"cam_cc_ife_1_clk_src",
"cam_cc_ife_2_clk_src",
"cam_cc_csid_clk_src",
"cam_cc_sfe_0_clk_src",
"cam_cc_sfe_1_clk_src",
"cam_cc_ipe_nps_clk_src",
"cam_cc_bps_clk_src",
"cam_cc_ife_lite_clk_src",
"cam_cc_jpeg_clk_src",
"cam_cc_camnoc_axi_clk_src",
"cam_cc_ife_lite_csid_clk_src",
"cam_cc_icp_clk_src",
"cam_cc_cphy_rx_clk_src",
"cam_cc_csi0phytimer_clk_src",
"cam_cc_csi1phytimer_clk_src",
"cam_cc_csi2phytimer_clk_src",
"cam_cc_csi3phytimer_clk_src",
"cam_cc_csi4phytimer_clk_src",
"cam_cc_csi5phytimer_clk_src",
"cam_cc_csi6phytimer_clk_src",
"cam_cc_csi7phytimer_clk_src",
"cam_cc_cci_0_clk_src",
"cam_cc_cci_1_clk_src",
"cam_cc_cci_2_clk_src",
"cam_cc_slow_ahb_clk_src",
"cam_cc_fast_ahb_clk_src",
"cam_cc_cre_clk_src",
"video_cc_mvs1_clk_src",
"disp_cc_mdss_mdp_clk_src",
"disp_cc_mdss_dptx0_link_clk_src",
"video_cc_mvs0_clk_src";
clocks =
<&camcc CAM_CC_IFE_0_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CLK_SRC>,
<&camcc CAM_CC_CSID_CLK_SRC>,
<&camcc CAM_CC_SFE_0_CLK_SRC>,
<&camcc CAM_CC_SFE_1_CLK_SRC>,
<&camcc CAM_CC_IPE_NPS_CLK_SRC>,
<&camcc CAM_CC_BPS_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_JPEG_CLK_SRC>,
<&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&camcc CAM_CC_ICP_CLK_SRC>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI6PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI7PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CCI_0_CLK_SRC>,
<&camcc CAM_CC_CCI_1_CLK_SRC>,
<&camcc CAM_CC_CCI_2_CLK_SRC>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&camcc CAM_CC_CRE_CLK_SRC>,
<&videocc VIDEO_CC_MVS1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&videocc VIDEO_CC_MVS0_CLK_SRC>;
clock_rates =
<0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_SFE_1_CLK_SRC 364000000 500000000 600000000 700000000 700000000>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>,
<0x1 CAM_CC_CRE_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>;
};
};

14
qcom/mmrm/kalama-mmrm-v2.dts Normal file
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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-kalama.h>
#include <dt-bindings/clock/qcom,videocc-kalama.h>
#include <dt-bindings/clock/qcom,dispcc-kalama.h>
#include "kalama-mmrm-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kalama v2 SoC";
compatible = "qcom,kalama";
qcom,msm-id = <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

54
qcom/mmrm/kalama-mmrm-v2.dtsi Normal file
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&soc {
msm_mmrm: qcom,mmrm {
compatible = "qcom,msm-mmrm", "qcom,kalama-mmrm";
status = "okay";
/* MMRM clock threshold */
mmrm-peak-threshold = <10000>;
/* MM Rail info */
mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
mm-rail-fact-volt = <37484 41157 44827 47710 52429>;
/* Scaling factors */
scaling-fact-dyn = <39951 48654 58347 66676 81756>;
scaling-fact-leak = <39951 671796 784171 884467 1082937>;
/* Client info */
mmrm-client-info =
<0x1 CAM_CC_IFE_0_CLK_SRC 31201472 238551 1>,
<0x1 CAM_CC_IFE_1_CLK_SRC 31201427 238551 1>,
<0x1 CAM_CC_IFE_2_CLK_SRC 31201427 238551 1>,
<0x1 CAM_CC_CSID_CLK_SRC 1858221 0 3>,
<0x1 CAM_CC_SFE_0_CLK_SRC 15273820 257556 1>,
<0x1 CAM_CC_SFE_1_CLK_SRC 15273820 257556 1>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 88824873 986972 1>,
<0x1 CAM_CC_BPS_CLK_SRC 30096753 84541 1>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 1460651 20054 2>,
<0x1 CAM_CC_JPEG_CLK_SRC 661914 18350 4>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 2930770 388628 1>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 225444 0 2>,
<0x1 CAM_CC_ICP_CLK_SRC 270533 0 1>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 0 10>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CCI_0_CLK_SRC 0 0 1>,
<0x1 CAM_CC_CCI_1_CLK_SRC 0 0 1>,
<0x1 CAM_CC_CCI_2_CLK_SRC 0 0 1>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 60306 0 1>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 30435 0 1>,
<0x1 CAM_CC_CRE_CLK_SRC 327680 0 1>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 66109440 476447 1>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 22714778 196608 1>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 897843 3277 1>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 13745521 486277 1>;
};
};

15
qcom/mmrm/kalama-mmrm-vm-be.dts Normal file
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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-kalama.h>
#include <dt-bindings/clock/qcom,videocc-kalama.h>
#include <dt-bindings/clock/qcom,dispcc-kalama.h>
#include "kalama-mmrm-vm-be.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kalama v1 SoC";
compatible = "qcom,kalama";
qcom,msm-id = <519 0x10000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

7
qcom/mmrm/kalama-mmrm-vm-be.dtsi Normal file
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&soc {
mmrm_vm_be: qcom,mmrm-vm-be {
compatible = "qcom,mmrm-vm-be";
status = "disable";
};
};

15
qcom/mmrm/kalama-mmrm-vm-fe-test.dts Normal file
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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-kalama.h>
#include <dt-bindings/clock/qcom,videocc-kalama.h>
#include <dt-bindings/clock/qcom,dispcc-kalama.h>
#include "kalama-mmrm-vm-fe-test.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kalama";
compatible = "qcom,kalama";
qcom,msm-id = <519 0x10000>, <536 0x10000>;
qcom,board-id = <0x10001 0>;
};

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&soc {
mmrm_vm_fe_test: qcom,mmrm-vm-fe-test {
compatible = "qcom,mmrm-vm-fe-test";
status = "okay";
/* Clock info */
clock-names =
"cam_cc_ife_0_clk_src",
"cam_cc_ife_1_clk_src",
"cam_cc_ife_2_clk_src",
"cam_cc_csid_clk_src",
"cam_cc_sfe_0_clk_src",
"cam_cc_sfe_1_clk_src",
"cam_cc_ipe_nps_clk_src",
"cam_cc_bps_clk_src",
"cam_cc_ife_lite_clk_src",
"cam_cc_jpeg_clk_src",
"cam_cc_camnoc_axi_clk_src",
"cam_cc_ife_lite_csid_clk_src",
"cam_cc_icp_clk_src",
"cam_cc_cphy_rx_clk_src",
"cam_cc_cci_0_clk_src",
"cam_cc_cci_1_clk_src",
"cam_cc_slow_ahb_clk_src",
"cam_cc_fast_ahb_clk_src";
clock_rates =
<0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
<0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
<0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
<0x1 CAM_CC_SFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 364000000 500000000 600000000 700000000 700000000>,
<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>;
};
};

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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-kalama.h>
#include <dt-bindings/clock/qcom,videocc-kalama.h>
#include <dt-bindings/clock/qcom,dispcc-kalama.h>
#include "kalama-mmrm-vm-fe.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kalama";
compatible = "qcom,kalama";
qcom,msm-id = <519 0x10000>, <536 0x10000>;
qcom,board-id = <0x10001 0>;
};

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&soc {
mmrm_vm_fe: qcom,mmrm-vm-fe {
compatible = "qcom,mmrm-vm-fe";
status = "disable";
/* Client info */
mmrm-client-info =
<0x1 CAM_CC_IFE_0_CLK_SRC>,
<0x1 CAM_CC_IFE_1_CLK_SRC>,
<0x1 CAM_CC_IFE_2_CLK_SRC>,
<0x1 CAM_CC_CSID_CLK_SRC>,
<0x1 CAM_CC_SFE_0_CLK_SRC>,
<0x1 CAM_CC_SFE_1_CLK_SRC>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC>,
<0x1 CAM_CC_BPS_CLK_SRC>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC>,
<0x1 CAM_CC_JPEG_CLK_SRC>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<0x1 CAM_CC_ICP_CLK_SRC>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<0x1 CAM_CC_CCI_0_CLK_SRC>,
<0x1 CAM_CC_CCI_1_CLK_SRC>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC>;
};
};

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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-kalama.h>
#include <dt-bindings/clock/qcom,videocc-kalama.h>
#include <dt-bindings/clock/qcom,dispcc-kalama.h>
#include "kalama-mmrm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kalama v1 SoC";
compatible = "qcom,kalama";
qcom,msm-id = <519 0x10000>, <536 0x10000>, <600 0x10000>, <601 0x10000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

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&soc {
msm_mmrm: qcom,mmrm {
compatible = "qcom,msm-mmrm", "qcom,kalama-mmrm";
status = "okay";
/* MMRM clock threshold */
mmrm-peak-threshold = <10000>;
/* MM Rail info */
mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
mm-rail-fact-volt = <37484 41157 44827 47710 52429>;
/* Scaling factors */
scaling-fact-dyn = <39951 48654 58347 66676 81756>;
scaling-fact-leak = <39951 671796 784171 884467 1082937>;
/* Client info */
mmrm-client-info =
<0x1 CAM_CC_IFE_0_CLK_SRC 31201472 238551 1>,
<0x1 CAM_CC_IFE_1_CLK_SRC 31201427 238551 1>,
<0x1 CAM_CC_IFE_2_CLK_SRC 31201427 238551 1>,
<0x1 CAM_CC_CSID_CLK_SRC 1858221 0 3>,
<0x1 CAM_CC_SFE_0_CLK_SRC 15273820 257556 1>,
<0x1 CAM_CC_SFE_1_CLK_SRC 15273820 257556 1>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 88824873 986972 1>,
<0x1 CAM_CC_BPS_CLK_SRC 30096753 84541 1>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 1460651 20054 2>,
<0x1 CAM_CC_JPEG_CLK_SRC 661914 18350 4>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 2930770 388628 1>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 225444 0 2>,
<0x1 CAM_CC_ICP_CLK_SRC 270533 0 1>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 0 10>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 5636 0 1>,
<0x1 CAM_CC_CCI_0_CLK_SRC 0 0 1>,
<0x1 CAM_CC_CCI_1_CLK_SRC 0 0 1>,
<0x1 CAM_CC_CCI_2_CLK_SRC 0 0 1>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 60306 0 1>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 30435 0 1>,
<0x1 CAM_CC_CRE_CLK_SRC 327680 0 1>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 66109440 476447 1>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 22714778 196608 1>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 897843 3277 1>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 13745521 486277 1>;
};
};

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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-waipio.h>
#include <dt-bindings/clock/qcom,videocc-waipio.h>
#include <dt-bindings/clock/qcom,dispcc-waipio.h>
#include "waipio-mmrm-test.dtsi"
/ {
model = "Qualcomm Technologies, Inc. waipio v1 & v2 SoC";
compatible = "qcom,waipio";
qcom,msm-id = <457 0x10000>, <482 0x10000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

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&soc {
msm_mmrm_test: qcom,mmrm-test {
compatible = "qcom,msm-mmrm-test", "qcom,waipio-mmrm-test";
status = "disable";
/* Clock info */
clock-names =
"cam_cc_ife_0_clk_src",
"cam_cc_ife_1_clk_src",
"cam_cc_ife_2_clk_src",
"cam_cc_csid_clk_src",
"cam_cc_sfe_0_clk_src",
"cam_cc_sfe_1_clk_src",
"cam_cc_ipe_nps_clk_src",
"cam_cc_bps_clk_src",
"cam_cc_ife_lite_clk_src",
"cam_cc_jpeg_clk_src",
"cam_cc_camnoc_axi_clk_src",
"cam_cc_ife_lite_csid_clk_src",
"cam_cc_icp_clk_src",
"cam_cc_cphy_rx_clk_src",
"cam_cc_csi0phytimer_clk_src",
"cam_cc_csi1phytimer_clk_src",
"cam_cc_csi2phytimer_clk_src",
"cam_cc_csi3phytimer_clk_src",
"cam_cc_csi4phytimer_clk_src",
"cam_cc_csi5phytimer_clk_src",
"cam_cc_cci_0_clk_src",
"cam_cc_cci_1_clk_src",
"cam_cc_slow_ahb_clk_src",
"cam_cc_fast_ahb_clk_src",
"video_cc_mvs1_clk_src",
"disp_cc_mdss_mdp_clk_src",
"disp_cc_mdss_dptx0_link_clk_src",
"video_cc_mvs0_clk_src";
clocks =
<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_2_CLK_SRC>,
<&clock_camcc CAM_CC_CSID_CLK_SRC>,
<&clock_camcc CAM_CC_SFE_0_CLK_SRC>,
<&clock_camcc CAM_CC_SFE_1_CLK_SRC>,
<&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>,
<&clock_camcc CAM_CC_BPS_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&clock_camcc CAM_CC_JPEG_CLK_SRC>,
<&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&clock_camcc CAM_CC_ICP_CLK_SRC>,
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CCI_0_CLK_SRC>,
<&clock_camcc CAM_CC_CCI_1_CLK_SRC>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&clock_videocc VIDEO_CC_MVS1_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&clock_videocc VIDEO_CC_MVS0_CLK_SRC>;
clock_rates =
<0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
<0x1 CAM_CC_SFE_1_CLK_SRC 364000000 500000000 600000000 700000000 700000000>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>;
};
};

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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-waipio.h>
#include <dt-bindings/clock/qcom,videocc-waipio.h>
#include <dt-bindings/clock/qcom,dispcc-waipio.h>
#include "waipio-mmrm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. waipio v1 SoC";
compatible = "qcom,waipio";
qcom,msm-id = <457 0x10000>, <482 0x10000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

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&soc {
msm_mmrm: qcom,mmrm {
compatible = "qcom,msm-mmrm", "qcom,waipio-mmrm";
status = "okay";
/* MMRM clock threshold */
mmrm-peak-threshold = <9000>;
/* MM Rail info */
mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
mm-rail-fact-volt = <36439 41157 44827 49152 54526>;
/* Scaling factors */
scaling-fact-dyn = <35390 45876 54395 66192 82576>;
scaling-fact-leak = <451544 548537 633078 746456 920126>;
/* Client info */
mmrm-client-info =
<0x1 CAM_CC_IFE_0_CLK_SRC 36280730 260834 1>,
<0x1 CAM_CC_IFE_1_CLK_SRC 36280730 260834 1>,
<0x1 CAM_CC_IFE_2_CLK_SRC 36280730 260834 1>,
<0x1 CAM_CC_CSID_CLK_SRC 2160722 0 3>,
<0x1 CAM_CC_SFE_0_CLK_SRC 20833895 135660 1>,
<0x1 CAM_CC_SFE_1_CLK_SRC 20833895 135660 1>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 67423437 608830 1>,
<0x1 CAM_CC_BPS_CLK_SRC 70584894 212992 1>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 1698431 20055 5>,
<0x1 CAM_CC_JPEG_CLK_SRC 1011876 0 2>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 3407872 589824 1>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 262144 0 5>,
<0x1 CAM_CC_ICP_CLK_SRC 314573 0 1>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 222823 0 9>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CCI_0_CLK_SRC 656 0 1>,
<0x1 CAM_CC_CCI_1_CLK_SRC 656 0 1>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 70124 0 1>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 35390 0 1>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 81149297 488244 1>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 21954560 184812 1>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 1004667 4916 1>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 28970189 582288 1>;
};
};

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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-waipio.h>
#include <dt-bindings/clock/qcom,videocc-waipio.h>
#include <dt-bindings/clock/qcom,dispcc-waipio.h>
#include "waipio-v2-mmrm-test.dtsi"
/ {
model = "Qualcomm Technologies, Inc. waipio v1 & v2 SoC";
compatible = "qcom,waipio";
qcom,msm-id = <457 0x20000>, <482 0x20000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

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&soc {
msm_mmrm_test: qcom,mmrm-test {
compatible = "qcom,msm-mmrm-test", "qcom,waipio-mmrm-test";
status = "disable";
/* Clock info */
clock-names =
"cam_cc_ife_0_clk_src",
"cam_cc_ife_1_clk_src",
"cam_cc_ife_2_clk_src",
"cam_cc_csid_clk_src",
"cam_cc_sfe_0_clk_src",
"cam_cc_sfe_1_clk_src",
"cam_cc_ipe_nps_clk_src",
"cam_cc_bps_clk_src",
"cam_cc_ife_lite_clk_src",
"cam_cc_jpeg_clk_src",
"cam_cc_camnoc_axi_clk_src",
"cam_cc_ife_lite_csid_clk_src",
"cam_cc_icp_clk_src",
"cam_cc_cphy_rx_clk_src",
"cam_cc_csi0phytimer_clk_src",
"cam_cc_csi1phytimer_clk_src",
"cam_cc_csi2phytimer_clk_src",
"cam_cc_csi3phytimer_clk_src",
"cam_cc_csi4phytimer_clk_src",
"cam_cc_csi5phytimer_clk_src",
"cam_cc_cci_0_clk_src",
"cam_cc_cci_1_clk_src",
"cam_cc_slow_ahb_clk_src",
"cam_cc_fast_ahb_clk_src",
"video_cc_mvs1_clk_src",
"disp_cc_mdss_mdp_clk_src",
"disp_cc_mdss_dptx0_link_clk_src",
"video_cc_mvs0_clk_src";
clocks =
<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_2_CLK_SRC>,
<&clock_camcc CAM_CC_CSID_CLK_SRC>,
<&clock_camcc CAM_CC_SFE_0_CLK_SRC>,
<&clock_camcc CAM_CC_SFE_1_CLK_SRC>,
<&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>,
<&clock_camcc CAM_CC_BPS_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&clock_camcc CAM_CC_JPEG_CLK_SRC>,
<&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&clock_camcc CAM_CC_ICP_CLK_SRC>,
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CCI_0_CLK_SRC>,
<&clock_camcc CAM_CC_CCI_1_CLK_SRC>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&clock_videocc VIDEO_CC_MVS1_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&clock_videocc VIDEO_CC_MVS0_CLK_SRC>;
clock_rates =
<0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
<0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
<0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
<0x1 CAM_CC_SFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 364000000 500000000 600000000 700000000 700000000>,
<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>;
};
};

14
qcom/mmrm/waipio-v2-mmrm.dts Normal file
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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-waipio.h>
#include <dt-bindings/clock/qcom,videocc-waipio.h>
#include <dt-bindings/clock/qcom,dispcc-waipio.h>
#include "waipio-v2-mmrm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. waipio v2 SoC";
compatible = "qcom,waipio";
qcom,msm-id = <457 0x20000>, <482 0x20000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

48
qcom/mmrm/waipio-v2-mmrm.dtsi Normal file
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&soc {
msm_mmrm: qcom,mmrm {
compatible = "qcom,msm-mmrm", "qcom,waipio-mmrm";
status = "okay";
/* MMRM clock threshold */
mmrm-peak-threshold = <9000>;
/* MM Rail info */
mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
mm-rail-fact-volt = <36438 41157 44827 49152 54526>;
/* Scaling factors */
scaling-fact-dyn = <35389 45876 54395 66192 82575>;
scaling-fact-leak = <451543 548537 633078 746456 920125>;
/* Client info */
mmrm-client-info =
<0x1 CAM_CC_IFE_0_CLK_SRC 33751040 279839 1>,
<0x1 CAM_CC_IFE_1_CLK_SRC 33751040 279839 1>,
<0x1 CAM_CC_IFE_2_CLK_SRC 33751040 279839 1>,
<0x1 CAM_CC_CSID_CLK_SRC 2160722 0 3>,
<0x1 CAM_CC_SFE_0_CLK_SRC 19333120 132383 1>,
<0x1 CAM_CC_SFE_1_CLK_SRC 19333120 132383 1>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 67436544 587203 1>,
<0x1 CAM_CC_BPS_CLK_SRC 70584893 334234 1>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 8492155 11796 5>,
<0x1 CAM_CC_JPEG_CLK_SRC 1097073 595067 2>,
<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 7602176 3533701 1>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 262144 0 5>,
<0x1 CAM_CC_ICP_CLK_SRC 314573 0 1>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 222822 0 9>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CCI_0_CLK_SRC 655 0 1>,
<0x1 CAM_CC_CCI_1_CLK_SRC 655 0 1>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 70124 0 1>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 35389 0 1>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 81149297 488243 1>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 21954560 184812 1>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 1004667 5243 1>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 28970189 582287 1>;
};
};