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Merge "ARM: dts: msm: Add devicetree bindings snapshot for Waipio Support"

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qctecmdr
2021-08-20 16:23:03 -07:00
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112
bindings/arm/arch_timer.txt Normal file
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@@ -0,0 +1,112 @@
* ARM architected timer
ARM cores may have a per-core architected timer, which provides per-cpu timers,
or a memory mapped architected timer, which provides up to 8 frames with a
physical and optional virtual timer per frame.
The per-core architected timer is attached to a GIC to deliver its
per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
to deliver its interrupts via SPIs.
** CP15 Timer node properties:
- compatible : Should at least contain one of
"arm,armv7-timer"
"arm,armv8-timer"
- interrupts : Interrupt list for secure, non-secure, virtual and
hypervisor timers, in that order.
- clock-frequency : The frequency of the main counter, in Hz. Should be present
only where necessary to work around broken firmware which does not configure
CNTFRQ on all CPUs to a uniform correct value. Use of this property is
strongly discouraged; fix your firmware unless absolutely impossible.
- always-on : a boolean property. If present, the timer is powered through an
always-on power domain, therefore it never loses context.
- fsl,erratum-a008585 : A boolean property. Indicates the presence of
QorIQ erratum A-008585, which says that reading the counter is
unreliable unless the same value is returned by back-to-back reads.
This also affects writes to the tval register, due to the implicit
counter read.
- hisilicon,erratum-161010101 : A boolean property. Indicates the
presence of Hisilicon erratum 161010101, which says that reading the
counters is unreliable in some cases, and reads may return a value 32
beyond the correct value. This also affects writes to the tval
registers, due to the implicit counter read.
** Optional properties:
- arm,cpu-registers-not-fw-configured : Firmware does not initialize
any of the generic timer CPU registers, which contain their
architecturally-defined reset values. Only supported for 32-bit
systems which follow the ARMv7 architected reset values.
- arm,no-tick-in-suspend : The main counter does not tick when the system is in
low-power system suspend on some SoCs. This behavior does not match the
Architecture Reference Manual's specification that the system counter "must
be implemented in an always-on power domain."
Example:
timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
clock-frequency = <100000000>;
};
** Memory mapped timer node properties:
- compatible : Should at least contain "arm,armv7-timer-mem".
- clock-frequency : The frequency of the main counter, in Hz. Should be present
only when firmware has not configured the MMIO CNTFRQ registers.
- reg : The control frame base address.
Note that #address-cells, #size-cells, and ranges shall be present to ensure
the CPU can address a frame's registers.
A timer node has up to 8 frame sub-nodes, each with the following properties:
- frame-number: 0 to 7.
- interrupts : Interrupt list for physical and virtual timers in that order.
The virtual timer interrupt is optional.
- reg : The first and second view base addresses in that order. The second view
base address is optional.
- status : "disabled" indicates the frame is not available for use. Optional.
Example:
timer@f0000000 {
compatible = "arm,armv7-timer-mem";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0xf0000000 0x1000>;
clock-frequency = <50000000>;
frame@f0001000 {
frame-number = <0>
interrupts = <0 13 0x8>,
<0 14 0x8>;
reg = <0xf0001000 0x1000>,
<0xf0002000 0x1000>;
};
frame@f0003000 {
frame-number = <1>
interrupts = <0 15 0x8>;
reg = <0xf0003000 0x1000>;
};
};

162
bindings/arm/coresight.txt
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@@ -105,12 +105,49 @@ its hardware characteristcs.
coresight component and CPU in the same power domain. When the CPU
powers down the coresight component also powers down and loses its
context. This property is currently only used for the ETM 4.x driver.
- Coresight Trace, Profiling & Diagnostic module:
"qcom,coresight-tpda"
"qcom,coresight-tpdm"
- Coresight control register:
"qcom,coresight-csr"
- Coresight Hardware Event
"qcom,coresight-hwevent"
- Coresight dummy device:
"qcom,coresight-dummy"
- Coresight remote ETM:
"qcom,coresight-remote-etm"
* port or ports: see "Graph bindings for Coresight" below.
* Additional required property for coresight-tgu devices:
* tgu-steps: must be present. Indicates number of steps supported
by the TGU.
* tgu-conditions: must be present. Indicates the number of conditions
supported by the TGU.
* tgu-regs: must be present. Indicates the number of regs supported
by the TGU.
* tgu-timer-counters: must be present. Indicates the number of timers and
counters available in the TGU to do a comparision.
* Optional properties for all components:
* reg-names: names corresponding to each reg property value.
* qcom,proxy-regs: List of regulators required.
* qcom,proxy-clks: List of additional clocks required.
* Optional properties for ETM/PTMs:
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
* qcom,tupwr-disable: For ETM, don't keep trace unit powered across
power collapse.
* qcom,skip-power-up: boolean. Indicates that an implementation can
skip powering up the trace unit. TRCPDCR.PU does not have to be set
on Qualcomm Technologies Inc. systems since ETMs are in the same power
@@ -127,9 +164,102 @@ its hardware characteristcs.
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
use the SG mode on this system.
* Optional property for CATU :
* usb_bam_support: boolean. Indicates that the TMC-ETR supports usb
bam connection.
* csr-atid-offset: When there are two ETRs, each of the ETR has its own ATID config
csr registers. It is the ETR_ATID0 register offset to the CSR base address.
* csr-irqctrl-offset: When there are two ETRs, each of the ETR has its own ETRIRQCTRL
register. It is the IRQCTRL register offset to the CSR base address.
* byte-cntr-name: The name of the byte-cntr
* byte-cntr-class-name: The name for class_create in byte-cntr driver.
* Optional property for CATU and APSS :
* interrupts : Exactly one SPI may be listed for reporting the address
error
error for CATU and four interrupts for TGU to get trigger from four
type of events.
* Required property for TPDAs:
* qcom,tpda-atid: must be present. Specifies the ATID for TPDA.
* Optional properties for TPDAs:
* qcom,bc-elem-size: specifies the BC element size supported by each
monitor connected to the aggregator on each port. Should be specified
in pairs (port, bc element size).
* qcom,tc-elem-size: specifies the TC element size supported by each
monitor connected to the aggregator on each port. Should be specified
in pairs (port, tc element size).
* qcom,dsb-elem-size: specifies the DSB element size supported by each
monitor connected to the aggregator on each port. Should be specified
in pairs (port, dsb element size).
* qcom,cmb-elem-size: specifies the CMB element size supported by each
monitor connected to the aggregator on each port. Should be specified
in pairs (port, cmb element size).
* Optional properties for TPDM:
* qcom,clk-enable: specifies whether additional clock bit needs to be
set for M4M TPDM.
* qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed
after enabling the subunit.
* qcom,cmb-msr-skip: boolean, indicating cmb MSR don't need to be programmed.
* qcom,hw-enable-check: Check if the tpdm need to be probed as some tpdms
are not enabled in secure device.
* Optional properties for CSRs:
* qcom,usb-bam-support: boolean, indicates CSR has the ability to operate on
usb bam, include enable,disable and flush.
* qcom,hwctrl-set-support: boolean, indicates CSR has the ability to operate on
to "HWCTRL" register.
* qcom,set-byte-cntr-support:boolean, indicates CSR has the ability to operate on
to "BYTECNT" register.
* qcom,timestamp-support:boolean, indicates CSR support sys interface to read
timestamp value.
* qcom,perflsheot-set-support: boolean, indicates PERFLSHEOT bit of USBFLSHCTRL
register will be set to 1 when usb sink is enabled.
* qcom,msr-support: boolean, indicates that CSR supports configure msr config for
tpdm.
* Required property for Remote ETMs:
* qcom,inst-id: must be present. QMI instance id for remote ETMs.
* Optional properties for funnels:
* source: specifies the source that binds to this output port. Only
trace from that source routes to this output port.
* qcom,duplicate-funnel: boolean, indicates its a duplicate of an
existing funnel. Funnel devices are now capable of supporting
multiple-input and multiple-output configuration with in built
hardware filtering for TPDM devices. Each set of input-output
combination is treated as independent funnel device.
funnel-base-dummy and funnel-base-real reg-names must be specified
when this property is enabled.
* reg-names: funnel-base-dummy: dummy register space used by a
duplicate funnel. Should be a valid register address space that
no other device is using.
* reg-names: funnel-base-real: actual register space for the
duplicate funnel.
* Optional property for configurable replicators:
@@ -137,6 +267,14 @@ its hardware characteristcs.
will lose register context when AMBA clock is removed which is observed
in some replicator designs.
* Optional property for CTIs:
* qcom,extended_cti: boolean. Indicates that cti is an extended cti.
* Optional property for all source components:
* atid: atid for the trace data of the source. If the data has two atids, configure
two ids for the source. This is for multi ETR sink.
Graph bindings for Coresight
-------------------------------
@@ -393,5 +531,25 @@ Example:
};
};
6. TGUs
ipcb_tgu: tgu@6b0c000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x0003b999>;
reg = <0x06B0C000 0x1000>;
reg-names = "tgu-base";
tgu-steps = <3>;
tgu-conditions = <4>;
tgu-regs = <4>;
tgu-timer-counters = <8>;
interrupts = <GIC_SPI 23 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 24 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 25 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 26 IRQ_TYPE_TRIGGER_HIGH>;
coresight-name = "coresight-tgu-ipcb";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
};
[1]. There is currently two version of STM: STM32 and STM500. Both
have the same HW interface and as such don't need an explicit binding name.

65
bindings/arm/msm/heap-sharing.txt Normal file
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* Memory Share Driver (MEMSHARE)
The Memshare driver implements a Kernel QMI service on the
LA-APSS, which is responsible for providing contiguous physical
memory to MPSS for use cases when the modem requires additional
memory (e.g. GPS).
Required properties for Memshare
-Root Node-
- compatible: Must be "qcom,memshare"
Required properties for child nodes:
- compatible: Must be "qcom,memshare-peripheral"
- qcom,peripheral-size: Indicates the size (in bytes) required for that child.
- qcom,client-id: Indicates the client id of the child node.
- label: Indicates the peripheral information for the node. Should be one of
the following:
- modem /* Represent Modem Peripheral */
- adsp /* Represent ADSP Peripheral */
- wcnss /* Represent WCNSS Peripheral */
Optional properties for child nodes:
- qcom,allocate-boot-time: Indicates whether clients needs boot time memory allocation.
- qcom,allocate-on-request: Indicates memory allocation happens only upon client request
Note: qcom,allocate-boot-time and qcom,allocate-on-request are mutually exclusive rite now.
- qcom,guard-band: Indicates addition of a guard band memory allocation in addition to the client's memory region.
Example 1:
qcom,memshare {
compatible = "qcom,memshare";
qcom,client_1 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x200000>;
qcom,client-id = <0>;
qcom,allocate-boot-time;
label = "modem";
};
};
Example 2:
qcom,memshare {
compatible = "qcom,memshare";
qcom,client_3 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x500000>;
qcom,client-id = <1>;
qcom,allocate-on-request;
qcom,guard-band;
label = "modem";
};
};

9
bindings/arm/msm/hyp_core_ctl.txt Normal file
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@@ -0,0 +1,9 @@
Qualcomm Technologies, Inc. Core Control for Hypervisor
Required properties:
- compatible: should be "qcom,hyp-core-ctl"
Example:
hyp-core-ctl {
compatible = "qcom,hyp-core-ctl";
};

164
bindings/arm/msm/mdm-modem.txt Normal file
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@@ -0,0 +1,164 @@
Attached MDM Modem Devices
External modems are devices that are attached to the msm and controlled by gpios.
There is also a data channel between the msm and the external modem that sometimes needs
to be reset.
Required Properties:
- compatible: The bus devices need to be compatible with "qcom,ext-mdm9x55", "qcom,ext-sdx50m",
"qcom,ext-sdx55m", "qcom,ext-lemur".
Required named gpio properties:
- qcom,mdm2ap-errfatal-gpio: gpio for the external modem to indicate to the apps processor
of an error fatal condition on the modem.
- qcom,ap2mdm-errfatal-gpio: gpio for the apps processor to indicate to the external modem
of an error fatal condition on the apps processor.
- qcom,mdm2ap-status-gpio: gpio to indicate to the apps processor when there is a watchdog
bite on the external modem.
- qcom,ap2mdm-status-gpio: gpio for the apps processor to indicate to the modem that an apps
processor watchdog bite has occurred.
- qcom,ap2mdm-soft-reset-gpio: gpio for the apps processor to use to soft-reset the external
modem. If the flags parameter has a value of 0x1 then the gpio is active LOW.
Required Interrupts:
- "err_fatal_irq": Interrupt generated on the apps processor when the error fatal gpio is pulled
high by the external modem.
- "status_irq": Interrupt generated on the apps processor when the mdm2ap-status gpio falls low
on the external modem. This usually indicates a watchdog bite on the modem.
- "plbrdy_irq": Interrupt generated on the aps processor when the mdm2ap-pblrdy gpio is pulled
either high or low by the external modem. This is an indication that the modem
has rebooted.
- "mdm2ap_vddmin_irq": Interrupt generated on the apps processor when the external modem goes
into vddmin power state.
Optional named gpio properties:
- qcom,mdm2ap-pblrdy-gpio: gpio used by some external modems to indicate when the modem has
booted into the PBL bootloader.
- qcom,ap2mdm-wakeup-gpio: gpio used by the apps processor to wake the external modem
out of a low power state.
- qcom,ap2mdm-chnl-rdy-gpio: gpio used by the apps processor to inform the external modem
that data link is ready.
- qcom,mdm2ap-wakeup-gpio: gpio from the external modem to the apps processor to wake it
out of a low power state.
- qcom,ap2mdm-vddmin-gpio: gpio to indicate to the external modem when the apps processor
is about to enter vddmin power state.
- qcom,mdm2ap-vddmin-gpio: gpio used by the external modem to inform the apps processor
when it is about to enter vddmin power state.
- qcom,ap2mdm-kpdpwr-gpio: gpio used to simulate a power button press on the external
modem. Some modems use this as part of their initial power-up sequence.
If the "flags" parameter has a value of 0x1 then it is active LOW.
- qcom,ap2mdm-pmic-pwr-en-gpio: Some modems need this gpio for the apps processor to enable
the pmic on the external modem.
- qcom,use-usb-port-gpio: some modems use this gpio to switch a port connection from uart to usb.
This is used during firmware upgrade of some modems.
- qcom,mdm-link-detect-gpio: some modems may support two interfaces. This gpio
indicates whether only one or both links can be used.
Optional driver parameters:
- qcom,ramdump-delay-ms: time in milliseconds to wait before starting to collect ramdumps.
This interval is the time to wait after an error on the external modem is
signaled to the apps processor before starting to collect ramdumps. Its
value depends on the type of external modem (e.g. MDM vs QSC), and how
error fatal handing is done on the modem.
The default value is 2 seconds (2000 milliseconds) as specified by the
mdm9x15 software developer. Consultation with the developer of the modem
software is required to determine this value for that modem.
- qcom,ps-hold-delay-ms: minimum delay in milliseconds between consecutive PS_HOLD toggles.
SGLTE targets that use a QSC1215 modem require a minimum delay between consecutive
toggling of the PS_HOLD pmic input. For one target it is 500 milliseconds but it
may vary depending on the target and how the external modem is connected. The value
is specified by the hardware designers.
- qcom,early-power-on: boolean flag to indicate if to power on the modem when the device is probed.
- qcom,sfr-query: boolean flag to indicate if to query the modem for a reset reason.
- qcom,no-powerdown-after-ramdumps: boolean flag to indicate if to power down the modem after ramdumps.
- qcom,no-a2m-errfatal-on-ssr: boolean to tell driver not to raise ap2mdm errfatal during SSR.
- qcom,no-reset-on-first-powerup: boolean to tell driver not to reset the modem when first
powering up the modem.
- qcom,ramdump-timeout-ms: ramdump timeout interval in milliseconds.
This interval is the time to wait for collection of the external modem's ramdump
to complete. It's value depends on the speed of the data connection between the
external modem and the apps processor on the platform. If the connection is a
UART port then this delay needs to be longer in order to avoid premature timeout
of the ramdump collection.
The default value is 2 minutes (120000 milliseconds) which is based on the
measured time it takes over a UART connection. It is reduced when the data
connection is an HSIC port. The value is usually tuned empirically for a
particular target.
- qcom,image-upgrade-supported: boolean flag to indicate if software upgrade is supported.
- qcom,support-shutdown: boolean flag to indicate if graceful shutdown is supported.
- qcom,vddmin-drive-strength: drive strength in milliamps of the ap2mdm-vddmin gpio.
The ap2mdm_vddmin gpio is controlled by the RPM processor. It is pulled low
to indicate to the external modem that the apps processor has entered vddmin
state, and high to indicate the reverse. Its parameters are passed to the RPM
software from the HLOS because the RPM software has to way of saving this type
of configuration when an external modem is attached.
The value of the drive strength is specified by the hardware designers. A value
of 8 milliamps is typical.
This property is ignored if the property "qcom,ap2mdm-vddmin-gpio" is
not set.
- qcom,vddmin-modes: a string indicating the "modes" requested for the ap2mdm-vddmin gpio.
This value is passed to RPM and is used by the RPM module to determine the
gpio mux function. The only currently supported modes string is "normal" and
corresponds to the value 0x03 that is passed to RPM.
- qcom,restart-group: List of subsystems that will need to restart together.
- qcom,mdm-dual-link: Boolean indicates whether both links can used for
communication.
- qcom,ssctl-instance-id: Instance id used by the subsystem to connect with the SSCTL service.
- qcom,sysmon-id: platform device id that sysmon is probed with for the subsystem.
- qcom,pil-force-shutdown: Boolean. If set, the SSR framework will not trigger graceful shutdown
on behalf of the subsystem driver.
- qcom,mdm-link-info: a string indicating additional info about the physical link.
For example: "devID_domain.bus.slot" in case of PCIe.
- qcom,mdm-auto-boot: Boolean. To indicate this instance of esoc boots independently.
- qcom,mdm-statusline-not-a-powersource: Boolean. If set, status line to esoc device is not a
power source.
- qcom,mdm-userspace-handle-shutdown: Boolean. If set, userspace handles shutdown requests.
- qcom,shutdown-timeout-ms: graceful shutdown timeout in milliseconds.
This interval is the time needed for the external modem to gracefully shutdown
after the host sends a shutdown command. The value depends on how long it takes
for the high level OS in the external modem to shutdown gracefully. The default
value is 10000 milliseconds.
- qcom,reset-time-ms: time it takes for the external modem to forcefully reset in milliseconds.
This interval is the time it takes to toggle the reset of an external modem by
holding down the reset pin. The value depends on the external modem's power
management boot options. The default value is 203 milliseconds.
- qcom,esoc-skip-restart-for-mdm-crash: Boolean. If set, the esoc framework would skip the warm
reboot phase during the momem crash.
Example:
mdm0: qcom,mdm0 {
compatible = "qcom,ext-lemur";
cell-index = <0>;
#address-cells = <0>;
interrupt-parent = <&mdm0>;
interrupts = <0 1 2 3>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map =
<0 &msmgpio 82 0x3
1 &msmgpio 46 0x3
2 &msmgpio 80 0x3
3 &msmgpio 27 0x3>;
interrupt-names =
"err_fatal_irq",
"status_irq",
"plbrdy_irq",
"mdm2ap_vddmin_irq";
qcom,mdm2ap-errfatal-gpio = <&msmgpio 82 0x00>;
qcom,ap2mdm-errfatal-gpio = <&msmgpio 106 0x00>;
qcom,mdm2ap-status-gpio = <&msmgpio 46 0x00>;
qcom,ap2mdm-status-gpio = <&msmgpio 105 0x00>;
qcom,ap2mdm-soft-reset-gpio = <&msmgpio 24 0x00>;
qcom,mdm2ap-pblrdy-gpio = <&msmgpio 80 0x00>;
qcom,ap2mdm-wakeup-gpio = <&msmgpio 104 0x00>;
qcom,ap2mdm-vddmin-gpio = <&msmgpio 108 0x00>;
qcom,mdm2ap-vddmin-gpio = <&msmgpio 27 0x00>;
qcom,ramdump-delay-ms = <2000>;
qcom,ramdump-timeout-ms = <120000>;
qcom,vddmin-modes = "normal";
qcom,vddmin-drive-strength = <8>;
qcom,ssctl-instance-id = <10>;
qcom,sysmon-id = <20>;
};

82
bindings/arm/msm/memory-offline.yaml Normal file
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@@ -0,0 +1,82 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/arm/msm/memory-offline.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Memory Offline Driver binding
maintainers:
- Isaac J. Manjarres <isaacm@quicinc.com>
description: |+
The memory offline driver supports the onlining and offlining of DDR memory.
Through the mem-offline node you can configure how much of the DDR will
support being offlined/onlined.
By default all memory is onlined when the device has booted up.
Note that offlinable memory can only support movable memory allocations so
designating too much memory as offlinable can result in system performance and
stability issues.
For more information on how to request the onlining and offlining of memory
see the memory hotplug documentation (Documentation/memory-hotplug.txt).
properties:
compatible:
items:
- const: qcom,mem-offline
granule:
$ref: '/schemas/types.yaml#/definitions/uint32'
maxItems: 1
description:
The minimum granule size in mega-bytes for memory onlining/offlining.
offline-sizes:
$ref: '/schemas/types.yaml#/definitions/uint32-array'
minItems: 1
description:
Array of offlinable memory region sizes to apply to targets based on
their DDR size.
Each entry in the array is a pair of sizes, where the first size in the
pair is the minimum amount of DDR required in the system in bytes, and
the second item in the pair is the size of the offlinable region in
bytes which will be applied to the system.
The offlinable memory region size from the entry where the minimum amount
of DDR required in the system is closest, but not greater, than the
amount of DDR in the system will be applied.
If there are no entries with a minimum amount of DDR required that is less
than the amount of DDR in the system then no offlinable region will be
created.
For example, in the following configuration:
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
<0x1 0xc0000000 0x0 0x80000000>;
On a 4GB target no offlinable region will be created.
On a 6GB target a 1GB offlinable region will be created.
On an 8GB target a 2GB offlinable region will be created.
On a 12GB target a 2GB offlinable region will be created.
mboxes:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
maxItems: 1
description:
Reference to the mailbox used by the driver to make requests to
online/offline memory.
required:
- compatible
- offline-sizes
- mboxes
examples:
- |
mem-offline {
compatible = "qcom,mem-offline";
granule = <512>;
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
<0x1 0xc0000000 0x0 0x80000000>;
mboxes = <&qmp_aop 0>;
};

1
bindings/arm/msm/msm.txt
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@@ -253,6 +253,7 @@ compatible = "qcom,waipio-mtp"
compatible = "qcom,waipio-atp"
compatible = "qcom,waipio-cdp"
compatible = "qcom,waipio-qrd"
compatible = "qcom,waipiop-hdk"
compatible = "qcom,waipiop-mtp"
compatible = "qcom,waipiop-cdp"
compatible = "qcom,waipiop-qrd"

60
bindings/arm/msm/msm_qmp.txt Normal file
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@@ -0,0 +1,60 @@
Qualcomm Technologies, Inc. QTI Mailbox Protocol
QMP Driver
===================
Required properties:
- compatible : should be "qcom,qmp-mbox".
- label : the name of the remote proc this link connects to.
- reg : The location and size of shared memory.
The irq register base address for triggering interrupts.
- reg-names : "msgram" - string to identify the shared memory region.
"irq-reg-base" - string to identify the irq register region.
- qcom,irq-mask : the bitmask to trigger an interrupt.
- mboxes: - Handle to outgoing interrupt if not using irq-reg-base
- interrupt : the receiving interrupt line.
- mbox-desc-offset : offset of mailbox descriptor from start of the msgram.
- priority : the priority of this mailbox compared to other mailboxes.
- #mbox-cells: Common mailbox binding property to identify the number of cells
required for the mailbox specifier, should be 1.
Optional properties:
- qcom,early-boot : bool to indicate that this remote proc will boot before QMP.
- mbox-offset : offset of the mcore mailbox from the offset of msgram. If this
property is not used, qmp will use the configuration
provided by the ucore.
- mbox-size : size of the mcore mailbox. If this property is not used, qmp will
use the configuration provided by the ucore.
Example:
qmp_aop: qcom,qmp-aop {
compatible = "qcom,qmp-mbox";
label = "aop";
qcom,early-boot;
reg = <0xc300000 0x100000>,
<0x1799000C 0x4>;
reg-names = "msgram", "irq-reg-base";
qcom,irq-mask = <0x1>;
interrupt = <0 389 1>;
mbox-desc-offset = <0x100>;
priority = <1>;
mbox-offset = <0x500>;
mbox-size = <0x400>;
#mbox-cells = <1>;
};
Mailbox Client
==============
"mboxes" and the optional "mbox-names" (please see
Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each value
of the mboxes property should contain a phandle to the mailbox controller
device node and second argument is the channel index. It must be 0 (qmp
supports only one channel).The equivalent "mbox-names" property value can be
used to give a name to the communication channel to be used by the client user.
Example:
qmp-client {
compatible = "qcom,qmp-client";
mbox-names = "aop";
mboxes = <&qmp_aop 0>,
};

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%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/msm/msm_rtb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Register Trace Buffer (RTB)
maintainers:
- Elliot Berman <eberman@quicinc.com>
description: |
The RTB is used to log discrete events in the system in an uncached buffer that
can be post processed from RAM dumps. The RTB must reserve memory using
the msm specific memory reservation bindings.
properties:
$nodename:
const: qcom,msm-rtb
compatible:
items:
-const: qcom,msm-rtb
qcom,rtb-size:
maxItems: 1
description: size of the RTB buffer in bytes
linux,contiguous-region:
$ref: '/schemas/types.yaml#/definitions/phandle'
maxItems: 1
description: phandle reference to a CMA region
required:
- compatible
- qcom,rtb-size
examples:
- |
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
};

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Qualcomm Technologies, Inc. Secure Execution Environment IPC Interrupt Bridge
[Root level node]
Required properties:
-compatible : should be "qcom,qsee-ipc-irq-bridge";
[Second level nodes]
qcom,qsee-ipc-irq-subsystem
Required properties:
-qcom,dev-name: the bridge device name
-interrupt: IPC interrupt line from remote subsystem to QSEE
-label : The name of this subsystem.
Required properties if interrupt type is IRQ_TYPE_LEVEL_HIGH[4]:
-qcom,rx-irq-clr : the register to clear the level triggered rx interrupt
-qcom,rx-irq-clr-mask : the bitmask to clear the rx interrupt
Example:
qcom,qsee_ipc_irq_bridge {
compatible = "qcom,qsee-ipc-irq-bridge";
qcom,qsee-ipc-irq-spss {
qcom,rx-irq-clr = <0x1d08008 0x4>;
qcom,rx-irq-clr-mask = <0x2>;
qcom,dev-name = "qsee_ipc_irq_spss";
interrupts = <0 349 4>;
label = "spss";
};
};

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Qualcomm Technologies, Inc. Remote Debugger (RDBG) driver
Required properties:
-compatible : Should be one of
To communicate with adsp
qcom,smp2p-interrupt-rdbg-2-in (inbound)
qcom,smp2p-interrupt-rdbg-2-out (outbound)
To communicate with cdsp
qcom,smp2p-interrupt-rdbg-5-in (inbound)
qcom,smp2p-interrupt-rdbg-5-out (outbound)
Example:
qcom,smp2p_interrupt_rdbg_2_in {
compatible = "qcom,smp2p-interrupt-rdbg-2-in";
};

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Qualcomm Technologies, Inc. SMSM Point-to-Point (SMP2P) Sleepstate driver
Required properties:
-compatible : should be one of the following:
- "qcom,smp2p-sleepstate"
-qcom,smem-states : the relevant outgoing smp2p entry
- interrupt-parent: specifies the phandle to the parent interrupt controller
this one is cascaded from
- interrupts: specifies the interrupt number, the irq line to be used
- interrupt-names: Interrupt name string, must be "smp2p-sleepstate-in"
Example:
qcom,smp2p_sleepstate {
compatible = "qcom,smp2p-sleepstate";
qcom,smem-states = <&sleepstate_smp2p_out 0>;
interrupt-parent = <&sleepstate_smp2p_in>;
interrupts = <0 0>;
interrupt-names = "smp2p-sleepstate-in";
};

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SYSTEM PM VIOLATORS
System PM Violoators is a virtual device sends a QMP message to AOP to start
recording subsystems that are preventing system low power modes - AOSS sleep,
CX PC, DDR low power from happening during a test duration. The stats are
saved in MSGRAM and are read and displayed from Linux in debugfs.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: must have "qcom,sys-pm-violators". Additionally, one of the
below SoC specific compatible must be specified.
- "qcom,sys-pm-lahaina"
- "qcom,sys-pm-waipio"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: The address on the AOP Message RAM from where the stats
are read.
- mbox:
Usage: required
Value type: <phandle>
Definition: handle to the QMP mailbox.
The second argument, channel is always '0'.
EXAMPLE
sys-pm-vx@c320000 {
compatible = "qcom,sys-pm-violators", "qcom,sys-pm-lahaina";
reg = <0xc320000 0x0400>;
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
};

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TMECOM QMP client:
-----------------
QTI Messaging Protocol(QMP) TMECom client is an interface for other clients to
send data to Trust Management Engine (TME) on MSM platforms
Required properties :
- compatible : must be "qcom,tmecom-qmp-client"
- mboxes : list of QMP mailbox phandle and channel identifier tuples.
- mbox-names : names of the listed mboxes
Example :
qcom,tmecom-qmp-client {
compatible = "qcom,tmecom-qmp-client";
mboxes = <&qmp_tme 0>;
mbox-names = "tmecom";
label = "tmecom";
depends-on-supply = <&qmp_tme>;
};

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* ARM Performance Monitor Units
ARM cores often have a PMU for counting cpu and cache events like cache misses
and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
representation in the device tree should be done as under:-
Required properties:
- compatible : should be one of
"arm,armv8-pmuv3"
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
interrupt (PPI) then 1 interrupt should be specified.
Optional properties:
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
events.
Example:
pmu {
compatible = "arm,armv8-pmu3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};

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* Power State Coordination Interface (PSCI)
Firmware implementing the PSCI functions described in ARM document number
ARM DEN 0022A ("Power State Coordination Interface System Software on ARM
processors") can be used by Linux to initiate various CPU-centric power
operations.
Issue A of the specification describes functions for CPU suspend, hotplug
and migration of secure software.
Functions are invoked by trapping to the privilege level of the PSCI
firmware (specified as part of the binding below) and passing arguments
in a manner similar to that specified by AAPCS:
r0 => 32-bit Function ID / return value
{r1 - r3} => Parameters
Note that the immediate field of the trapping instruction must be set
to #0.
Main node required properties:
- compatible : should contain at least one of:
* "arm,psci" : For implementations complying to PSCI versions prior
to 0.2.
For these cases function IDs must be provided.
* "arm,psci-0.2" : For implementations complying to PSCI 0.2.
Function IDs are not required and should be ignored by
an OS with PSCI 0.2 support, but are permitted to be
present for compatibility with existing software when
"arm,psci" is later in the compatible list.
* "arm,psci-1.0" : For implementations complying to PSCI 1.0.
PSCI 1.0 is backward compatible with PSCI 0.2 with
minor specification updates, as defined in the PSCI
specification[2].
- method : The method of calling the PSCI firmware. Permitted
values are:
"smc" : SMC #0, with the register assignments specified
in this binding.
"hvc" : HVC #0, with the register assignments specified
in this binding.
Main node optional properties:
- cpu_suspend : Function ID for CPU_SUSPEND operation
- cpu_off : Function ID for CPU_OFF operation
- cpu_on : Function ID for CPU_ON operation
- migrate : Function ID for MIGRATE operation
Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
state nodes, as per bindings in [1]) must specify the following properties:
- arm,psci-suspend-param
Usage: Required for state nodes[1] if the corresponding
idle-states node entry-method property is set
to "psci".
Value type: <u32>
Definition: power_state parameter to pass to the PSCI
suspend call.
Example:
Case 1: PSCI v0.1 only.
psci {
compatible = "arm,psci";
method = "smc";
cpu_suspend = <0x95c10000>;
cpu_off = <0x95c10001>;
cpu_on = <0x95c10002>;
migrate = <0x95c10003>;
};
Case 2: PSCI v0.2 only
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
Case 3: PSCI v0.2 and PSCI v0.1.
A DTB may provide IDs for use by kernels without PSCI 0.2 support,
enabling firmware and hypervisors to support existing and new kernels.
These IDs will be ignored by kernels with PSCI 0.2 support, which will
use the standard PSCI 0.2 IDs exclusively.
psci {
compatible = "arm,psci-0.2", "arm,psci";
method = "hvc";
cpu_on = < arbitrary value >;
cpu_off = < arbitrary value >;
...
};
[1] Kernel documentation - ARM idle states bindings
Documentation/devicetree/bindings/arm/idle-states.txt
[2] Power State Coordination Interface (PSCI) specification
http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf

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* BTFM Slimbus Slave Driver
BTFM Slimbus Slave driver configure and initialize slimbus slave device.
Bluetooth A2DP, SCO and FM Audio data is transferred over slimbus interface.
Required properties:
- compatible: Should be set to the following where 217 is manufacture id and 221 is prod id:
ex. HSP elmental address is 0x000120021702
compatible = "slim217,221"
- reg should be filled as per specs
reg = <1 0>;
Example:
slimbus: btfmslim-driver {
compatible = "slim217,221";
reg = <1 0>;
};

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* Bluetooth Controller
Bluetooth controller communicates with the Bluetooth Host using HCI Transport
layer. HCI Transport layer can be based on UART or USB serial communication
protocol.
Required properties:
- compatible: "qcom,<chip>"
chip: Should be set to one of the following:
qcom,qca6174
qcom,wcn3990
qcom,qca6390
qcom,qca6490
- qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset
Optional properties:
- qcom,xo-clk-gpio: GPIO for enabling clock at bootstrap
- qcom,bt-vdd-pa-supply: Bluetooth VDD PA regulator handle
- qcom,bt-vdd-io-supply: Bluetooth VDD IO regulator handle
- qcom,bt-vdd-ldo-supply: Bluetooth VDD LDO regulator handle. Kept under
optional parameters as some of the chipsets doesn't require ldo
or it may use from same vddio.
- qcom,bt-vdd-xtal-supply: Bluetooth VDD XTAL regulator handle
- qcom,bt-vdd-core-supply: Bluetooth VDD CORE regulator handle
- qcom,bt-vdd-asd-supply: Bluetooth VDD regulator handle for antenna switch
- reg: Memory regions defined as starting address and size
- reg-names: Names of the memory regions defined in reg entry
diversity.
- qcom,bt-chip-pwd-supply: Chip power down gpio is required when bluetooth
module and other modules like wifi co-exist in a singe chip and
shares a common gpio to bring chip out of reset.
- qcom,<supply>-config: Specifies voltage/current levels for supply. Should specified
in pairs (min, max), units uV. There can be optional
load in curr, unit uA. Last entry specifies if the retention
mode is supported for the regulator.
- mboxes: Specifies mbox channel data for AOP messaging
- qcom,vreg_ipa: Specifies Voltage regulator used for QCA6490 Internal Power
Amp config
Example:
bluetooth: bt_qca6490 {
compatible = "qcom,qca6390", "qcom,qca6490";
pinctrl-names = "default";
pinctrl-0 = <&bt_en_sleep>;
qcom,bt-reset-gpio = <&tlmm 81 0>; /* BT_EN */
qcom,wl-reset-gpio = <&tlmm 80 0>; /* WL_EN */
qcom,bt-sw-ctrl-gpio = <&tlmm 82 0>; /* SW_CTRL */
qcom,bt-xo-clk-gpio = <&tlmm 204 0>; /* XO */
qcom,bt-vdd-aon-supply = <&S11B>;
qcom,bt-vdd-dig-supply = <&S11B>;
qcom,bt-vdd-rfa1-supply = <&S1C>;
qcom,bt-vdd-rfa2-supply = <&S12B>;
qcom,bt-vdd-asd-supply = <&L7E>;
qcom,bt-vdd-aon-config = <966000 966000 0 1>;
qcom,bt-vdd-dig-config = <966000 966000 0 1>;
qcom,bt-vdd-rfa1-config = <1880000 1880000 0 1>;
qcom,bt-vdd-rfa2-config = <1350000 1350000 0 1>;
qcom,bt-vdd-asd-config = <2800000 2800000 0 1>;
};

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Richwave FM radio device
-FM RX playback with RDS
FM signal is demodulated then audio L/R samples are sent to external audio codec.
FM Rx RDS data received sent to host processor on I2C.
Required Properties:
- compatible: "rtc6226"
Example:
rtc6226 {
compatible = "rtc6226";
};

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* Qualcomm Technologies, Inc. ConNectivity SubSystem Platform Driver
This platform driver adds support for the CNSS subsystem used for PCIe
based Wi-Fi devices. It also adds support to integrate PCIe WLAN module
to subsystem restart framework. Apart from that, it also manages the
3.3V voltage regulator, WLAN Enable GPIO signal and PCIe link dynamically
with support for suspend and resume by retaining the PCI config space
states when PCIe link is shutdown. The main purpose of this device tree
entry below is to invoke the CNSS platform driver and provide handle to
the WLAN enable GPIO, 3.3V fixed voltage regulator resources. It also
provides the reserved RAM dump memory location and size.
Required properties:
- compatible: "qcom,cnss" for QCA6174 device
"qcom,cnss-qca6290" for QCA6290 device
"qcom,cnss-qca6390" for QCA6390 device
"qcom,cnss-qca6490" for QCA6490 device
"qcom,cnss-wcn7850" for WCN7850 device
- wlan-en-gpio: WLAN_EN GPIO signal specified by the chip specifications
- vdd-wlan-supply: phandle to the regulator device tree node
- pinctrl-names: Names corresponding to the numbered pinctrl states
- pinctrl-<n>: Pinctrl states as described in
bindings/pinctrl/pinctrl-bindings.txt
- qcom,wlan-rc-num: List of PCIe root complex numbers which WLAN device may
attach to
- qcom,wlan: Signature string for WLAN devices which all CNSS family drivers
are able to search for
Optional properties:
- qcom,notify-modem-status: Boolean property to decide whether modem
notification should be enabled or not in this
platform
- wlan-soc-swreg-supply: phandle to the external 1.15V regulator for QCA6174
- wlan-ant-switch-supply: phandle to the 2.7V regulator for the antenna
switch of QCA6174
- qcom,wlan-uart-access: Boolean property to decide whether QCA6174
has exclusive access to UART.
- vdd-wlan-io-supply: phandle to the 1.8V IO regulator for QCA6174
- vdd-wlan-xtal-supply: phandle to the 1.8V XTAL regulator for QCA6174
- vdd-wlan-xtal-aon-supply: phandle to the LDO-4 regulator. This is needed
on platforms where XTAL regulator depends on
always on regulator in VDDmin.
- vdd-wlan-ctrl1-supply: phandle to the DBU1 - 1.8V for QCA6595 or 3.3V for
QCA6174 on auto platform.
- vdd-wlan-ctrl2-supply: phandle to the DBU4 - 2.2V for QCA6595 or 3.85V for
QCA6696 on auto platform.
- vdd-wlan-core-supply: phandle to the 1.3V CORE regulator for QCA6174
- vdd-wlan-sp2t-supply: phandle to the 2.7V SP2T regulator for QCA6174
- <supply-name>-supply: phandle to the regulator device tree node.
optional "supply-name" is "vdd-wlan-rfa"
- qcom,<supply>-config: Specifies voltage levels for supply. Should specified
in pairs (min, max), units uV. There can be optional
load in uA and Regulator settle delay in us
- qcom,smmu-s1-enable: Boolean property to decide whether to enable SMMU
S1 stage or not
- qcom,wlan-smmu-iova-address: I/O virtual address range as <start length>
format to be used for allocations associated
between WLAN/PCIe and SMMU
- qcom,wlan-ramdump-dynamic: To enable CNSS RAMDUMP collection
by providing the size of CNSS DUMP
- qcom,cmd_db_name: CommandDB name indicating the PMIC rail used for open
loop CPR
- reg: Memory regions defined as starting address and size
- reg-names: Names of the memory regions defined in reg entry
- wlan-bootstrap-gpio: WLAN_BOOTSTRAP GPIO signal specified by QCA6174
which should be drived depending on platforms
- qcom,is-dual-wifi-enabled: Boolean property to control wlan enable(wlan-en)
gpio on dual-wifi platforms.
- vdd-wlan-en-supply: WLAN_EN fixed regulator specified by QCA6174
specifications.
- qcom,wlan-en-vreg-support: Boolean property to decide the whether the
WLAN_EN pin is a gpio or fixed regulator.
- qcom,mhi: phandle to indicate the device which needs MHI support.
- qcom,cap-tsf-gpio: WLAN_TSF_CAPTURED GPIO signal specified by the chip
specifications, should be drived depending on products
- cnss-daemon-support: Boolean property to decide whether cnss_daemon
userspace QMI client is supported.
- use-nv-mac: Boolean property to indicate whether NV MAC is used or not.
- qcom,set-wlaon-pwr-ctrl: Boolean property to indicate if set
WLAON_QFPROM_PWR_CTRL_REG register during power on
and off sequences.
- use-pm-domain: Boolean property to indicate if driver needs to use PM
domain or not.
- qcom,wlan-cbc-enabled: boolean property to control cold boot calibration
- interconnects: Interconnect framework setup for bus configuration
- interconnect-names: Interconnect path names as strings
- qcom,icc-path-count: Number of Interconnect paths for this platform
- qcom,bus-bw-cfg-count: Number of bus bandwidth voting cases
- qcom,bus-bw-cfg: Bus bandwidth voting data
- qcom,tcs_offset_int_pow_amp_vreg: TCS CMD register offset for Voltage
regulator used in internal power amplifier for QCA6490
- cnss-enable-self-recovery: Boolean property to enable self recovery when
recovery is trigeered with reason link down.
- qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO
enable to resolve PMU power up issues. Provide BT GPIO using
this config param.
- qcom,same-dt-multi-dev: Boolean property to decide whether it supports
multiple WLAN devices using the same DT node
without sub-nodes.
- qcom,converged-dt: Boolean property to decide whether it supports multiple
WLAN devices using the same DT node with sub-nodes.
- mboxes: Specifies mbox channel data for AOP messaging
- qcom,vreg_ipa: Specifies voltage regulator used for WLAN device internal
power amp config
- qcom,xo-clk-gpio: Added for QCA6490 XO CLK selection leakage prevention.
Examples:
qcom,cnss@0d400000 {
compatible = "qcom,cnss";
reg = <0x0d400000 0x200000>;
reg-names = "ramdump";
qcom,wlan-ramdump-dynamic = <0x200000>;
wlan-en-gpio = <&msmgpio 82 0>;
vdd-wlan-supply = <&wlan_vreg>;
qcom,notify-modem-status;
wlan-soc-swreg-supply = <&pma8084_l27>;
pinctrl-names = "default";
pinctrl-0 = <&cnss_default>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-smmu-iova-address = <0 0x10000000>;
qcom,mhi = <&mhi_wlan>;
qcom,cap-tsf-gpio = <&tlmm 126 1>;
};
wlan: qcom,cnss-qca6490@b0000000 {
compatible = "qcom,cnss-qca6490";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
wlan-en-gpio = <&tlmm 80 0>;
qcom,bt-en-gpio = <&tlmm 81 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x420000>;
qcom,wlan-cbc-enabled;
use-pm-domain;
cnss-enable-self-recovery;
qcom,same-dt-multi-dev;
mboxes = <&qmp_aop 0>;
qcom,vreg_ipa="s3e";
qcom,xo-clk-gpio = <&tlmm 204 0>;
vdd-wlan-aon-supply = <&S2E>;
qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 1>;
vdd-wlan-dig-supply = <&S11B>;
qcom,vdd-wlan-dig-config = <966000 966000 0 0 1>;
vdd-wlan-io-supply = <&S10B>;
qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
vdd-wlan-rfa1-supply = <&S1C>;
qcom,vdd-wlan-rfa1-config = <1900000 2100000 0 0 1>;
vdd-wlan-rfa2-supply = <&S12B>;
qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
wlan-ant-switch-supply = <&L7E>;
qcom,wlan-ant-switch-config = <2800000 2800000 0 0 1>;
};

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Qualcomm Technologies, Inc. CPUFREQ Hardware Debug Bindings
--------------------------------------------------------------------
CPUFREQ HW debug provide support to print the CPUFREQ_HW debug
registers.
Required Properties:
- compatible: shall contain the following:
"qcom,cpufreq-hw-debug" or "qcom,cpufreq-hw-epss-debug".
- reg: shall contain base register location and length.
- reg-names: shall contain the frequency domain name.
Optional Properties:
- qcom,freq-hw-domain: phandle to the frequency domain device node.
Usage :
The following debug node would get created under qcom-cpufreq-hw directory.
- print_cpufreq_debug_regs
Function: Print cpufreq hardware debug registers
Input: cat print_cpufreq_debug_regs
Example:
cpufreq_hw_debug: qcom,cpufreq-hw-debug@18591000 {
compatible = "qcom,cpufreq-hw-debug";
reg = <0x18591000 0x800>;
reg-names = "domain-top";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>,
<&cpufreq_hw 2>;
};

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- compatible
Usage: required
Value type: <string>
Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss" or "qcom,cpufreq-hw-epss".
- clocks
Usage: required
@@ -35,6 +35,25 @@ Properties:
Usage: required.
Definition: Number of cells in a freqency domain specifier.
- qcom,lut-row-size
Usage: Optional
Value type: <u32>
Definition: Size of the LUT row size.
- qcom,skip-enable-check
Usage: Optional
Value type: bool
Definition: Indicate to check for Enable of FW before registering
with cpufreq.
- qcom,perf-lock-support
Usage: Optional
Value type: bool
Definition: Indicate to check for performance lock support in FW.
In case this property is present, the reg & reg-names
should have the "pdmem-domainX" to indicate the
corresponding bases.
* Property qcom,freq-domain
Devices supporting freq-domain must set their "qcom,freq-domain" property with
phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.

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Introduction:
=============
This driver provides IOCTLS for user space application to access crypto
engine hardware for the qcedev crypto services. The driver supports the
following crypto algorithms
- AES-128, AES-256 (ECB, CBC and CTR mode)
- AES-192, (ECB, CBC and CTR mode)
(support exists on platform supporting CE 3.x hardware)
- SHA1/SHA256
- AES-128, AES-256 (XTS), AES CMAC, SHA1/SHA256 HMAC
(support exists on platform supporting CE 4.x hardware)
Device tree settings:
==============
Required properties:
- compatible : Should be "qcom,qcedev"
- reg : Offset and length of the register set for the device
- interconnect-names: interconnect names
- interconnects: interconnect setting defines belong to which NoC device
- qcom_cedev_ns_cb compatible: Should be "qcom,qcedev,context-bank"
- qcom_cedev_s_cb compatible: Should be "qcom,qcedev,context-bank"
Optional property:
Example:
qcom_cedev: qcedev@1de0000 {
compatible = "qcom,qcedev";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <3>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,bam-ee = <0>;
interconnect-names = "data_path";
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_HWKM>;
qcom,smmu-s1-enable;
qcom,no-clock-support;
iommus = <&apps_smmu 0x0586 0x0011>,
<&apps_smmu 0x0596 0x0011>;
qcom,iommu-dma = "atomic";
qcom_cedev_ns_cb {
compatible = "qcom,qcedev,context-bank";
label = "ns_context";
iommus = <&apps_smmu 0x592 0>,
<&apps_smmu 0x598 0>,
<&apps_smmu 0x599 0>,
<&apps_smmu 0x59F 0>;
};
qcom_cedev_s_cb {
compatible = "qcom,qcedev,context-bank";
label = "secure_context";
iommus = <&apps_smmu 0x593 0>,
<&apps_smmu 0x59C 0>,
<&apps_smmu 0x59D 0>,
<&apps_smmu 0x59E 0>;
qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
qcom,secure-context-bank;
};
};
Hardware description:
=====================
Crypto 3E provides cipher and hash algorithms as defined in the
3GPP forum specifications.
Software description
====================
The driver is a Linux platform device driver. For an msm target,
there can be multiple crypto devices assigned for QCEDEV.
The driver is a misc device driver as well.
The following operations are registered in the driver,
-qcedev_ioctl()
-qcedev_open()
-qcedev_release()
The following IOCTLS are available to the user space application(s)-
Cipher IOCTLs:
--------------
QCEDEV_IOCTL_ENC_REQ is for encrypting data.
QCEDEV_IOCTL_DEC_REQ is for decrypting data.
Hashing/HMAC IOCTLs
-------------------
QCEDEV_IOCTL_SHA_INIT_REQ is for initializing a hash/hmac request.
QCEDEV_IOCTL_SHA_UPDATE_REQ is for updating hash/hmac.
QCEDEV_IOCTL_SHA_FINAL_REQ is for ending the hash/mac request.
QCEDEV_IOCTL_GET_SHA_REQ is for retrieving the hash/hmac for data
packet of known size.
QCEDEV_IOCTL_GET_CMAC_REQ is for retrieving the MAC (using AES CMAC
algorithm) for data packet of known size.
The requests are synchronous. The driver will put the process to
sleep, waiting for the completion of the requests using wait_for_completion().
Since the requests are coming out of user space application, before giving
the requests to the low level qce driver, the ioctl requests and the
associated input/output buffer will have to be safe checked, and copied
to/from kernel space.
The extra copying of requests/buffer can affect the performance. The issue
with copying the data buffer is resolved by having the client use PMEM
allocated buffers.
NOTE: Using memory allocated via PMEM is supported only for in place
operations where source and destination buffers point to the same
location. Support for different source and destination buffers
is not supported currently.
Furthermore, when using PMEM, and in AES CTR mode, when issuing an
encryption or decryption request, a non-zero byteoffset is not
supported.
The design of the driver is to allow multiple open, and multiple requests
to be issued from application(s). Therefore, the driver will internally queue
the requests, and serialize the requests to the low level qce (or qce40) driver.
On an IOCTL request from an application, if there is no outstanding
request, a the driver will issue a "qce" request, otherwise,
the request is queued in the driver queue. The process is suspended
waiting for completion.
On completion of a request by the low level qce driver, the internal
tasklet (done_tasklet) is scheduled. The sole purpose of done_tasklet is
to call the completion of the current active request (complete()), and
issue more requests to the qce, if any.
When the process wakes up from wait_for_completion(), it will collect the
return code, and return the ioctl.
A spin lock is used to protect the critical section of internal queue to
be accessed from multiple tasks, SMP, and completion callback
from qce.
The driver maintains a set of statistics using debug fs. The files are
in /debug/qcedev/stats1, /debug/qcedev/stats2, /debug/qcedev/stats3;
one for each instance of device. Reading the file associated with
a device will retrieve the driver statistics for that device.
Any write to the file will clear the statistics.
Power Management
================
n/a
Interface:
==========
Linux user space applications will need to open a handle
(file descriptor) to the qcedev device. This is achieved by doing
the following to retrieve a file descriptor to the device.
fd = open("/dev/qce", O_RDWR);
..
ioctl(fd, ...);
Once a valid fd is retrieved, user can call the following ioctls with
the fd as the first parameter and a pointer to an appropriate data
structure, qcedev_cipher_op_req or qcedev_sha_op_req (depending on
cipher/hash functionality) as the second parameter.
The following IOCTLS are available to the user space application(s)-
Cipher IOCTLs:
--------------
QCEDEV_IOCTL_ENC_REQ is for encrypting data.
QCEDEV_IOCTL_DEC_REQ is for decrypting data.
The caller of the IOCTL passes a pointer to the structure shown
below, as the second parameter.
struct qcedev_cipher_op_req {
int use_pmem;
union{
struct qcedev_pmem_info pmem;
struct qcedev_vbuf_info vbuf;
};
uint32_t entries;
uint32_t data_len;
uint8_t in_place_op;
uint8_t enckey[QCEDEV_MAX_KEY_SIZE];
uint32_t encklen;
uint8_t iv[QCEDEV_MAX_IV_SIZE];
uint32_t ivlen;
uint32_t byteoffset;
enum qcedev_cipher_alg_enum alg;
enum qcedev_cipher_mode_enum mode;
enum qcedev_oper_enum op;
};
Hashing/HMAC IOCTLs
-------------------
QCEDEV_IOCTL_SHA_INIT_REQ is for initializing a hash/hmac request.
QCEDEV_IOCTL_SHA_UPDATE_REQ is for updating hash/hmac.
QCEDEV_IOCTL_SHA_FINAL_REQ is for ending the hash/mac request.
QCEDEV_IOCTL_GET_SHA_REQ is for retrieving the hash/hmac for data
packet of known size.
QCEDEV_IOCTL_GET_CMAC_REQ is for retrieving the MAC (using AES CMAC
algorithm) for data packet of known size.
The caller of the IOCTL passes a pointer to the structure shown
below, as the second parameter.
struct qcedev_sha_op_req {
struct buf_info data[QCEDEV_MAX_BUFFERS];
uint32_t entries;
uint32_t data_len;
uint8_t digest[QCEDEV_MAX_SHA_DIGEST];
uint32_t diglen;
uint8_t *authkey;
uint32_t authklen;
enum qcedev_sha_alg_enum alg;
struct qcedev_sha_ctxt ctxt;
};
The IOCTLs and associated request data structures are defined in qcedev.h
Module parameters:
==================
The following module parameters are defined in the board init file.
-CE hardware nase register address
-Data mover channel used for transfer to/from CE hardware
These parameters differ in each platform.
Dependencies:
=============
qce driver. Please see Documentation/arm/msm/qce.txt.
User space utilities:
=====================
none
Known issues:
=============
none.
To do:
======
Enhance Cipher functionality:
(1) Add support for handling > 32KB for ciphering functionality when
- operation is not an "in place" operation (source != destination).
(when using PMEM allocated memory)
Limitations:
============
(1) In case of cipher functionality, Driver does not support
a combination of different memory sources for source/destination.
In other words, memory pointed to by src and dst,
must BOTH (src/dst) be "pmem" or BOTH(src/dst) be "vbuf".
(2) In case of hash functionality, driver does not support handling data
buffers allocated via PMEM.
(3) Do not load this driver if your device already has kernel space apps
that need to access the crypto hardware.
Make sure to have qcedev module disabled/unloaded and implement your user
space application to use the software implementation (ex: openssl/crypto)
of the crypto algorithms.
(NOTE: Please refer to details on the limitations listed in qce.txt)
(4) If your device has Playready (Windows Media DRM) application enabled
and uses the qcedev module to access the crypto hardware accelerator,
please be informed that for performance reasons, the CE hardware will
need to be dedicated to playready application. Any other user space
application should be implemented to use the software implementation
(ex: openssl/crypto) of the crypto algorithms.

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Qualcomm Technologies Inc GPI DMA controller
MSM GPI DMA controller provides DMA capabilities for
peripheral buses such as I2C, UART, and SPI.
==============
Node Structure
==============
Main node properties:
- #dma-cells
Usage: required
Value type: <u32>
Definition: Number of parameters client will provide. Must be set to 5.
1st parameter: channel index, 0 for TX, 1 for RX
2nd parameter: serial engine index
3rd parameter: bus protocol, 1 for SPI, 2 for UART, 3 for I2C
4th parameter: channel ring length in transfer ring elements
5th parameter: event processing priority, set to 0 for lowest latency
- compatible
Usage: required
Value type: <string>
Definition: "qcom,gpi-dma"
- reg
Usage: required
Value type: Array of <u32>
Definition: register address space location and size
- reg-name
Usage: required
Value type: <string>
Definition: register space name, must be "gpi-top"
- interrupts
Usage: required
Value type: Array of <u32>
Definition: Array of tuples which describe interrupt line for each GPII
instance.
- qcom,max-num-gpii
Usage: required
Value type: <u32>
Definition: Total number of GPII instances available for this controller.
- qcom,gpii-mask
Usage: required
Value type: <u32>
Definition: Bitmap of supported GPII instances in hlos.
- qcom,ev-factor
Usage: required
Value type: <u32>
Definition: Event ring transfer size compare to channel transfer ring. Event
ring length = ev-factor * transfer ring size
- iommus
Usage: required
Value type: <phandle u32 u32>
Definition: phandle for apps smmu controller and SID, and mask
for the controller. For more detail please check binding
documentation arm,smmu.txt
Optional property:
- qcom,gpi-ee-offset
Usage: optional
Value type: u64
Definition: Specifies the gsi ee register offset for the QUP.
- qcom,iommu-dma-addr-pool
Usage: optional
Value type: tuple of <address size>.
Definition: Indicates the range of addresses that the dma layer will use.
- qcom,le-vm
Usage: optional
Value type: boolean
Definition: flag to support I2C functionality in trusted VM.
- qcom,static-gpii-mask
Usage: optional
Value type: boolean
Definition: GPII number statically assigned to TUI LA touch se.
========
Example:
========
gpi_dma0: qcom,gpi-dma@0x800000 {
#dma-cells = <5>;
compatible = "qcom,gpi-dma";
reg = <0x800000 0x60000>;
reg-names = "gpi-top";
interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,
<0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,
<0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>,
<0 256 0>;
qcom,max-num-gpii = <13>;
qcom,gpii-mask = <0xfa>;
qcom,ev-factor = <2>;
iommus = <&apps_smmu 0x0016 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
status = "ok";
};

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SPS (Smart Peripheral Switch) may be used as a DMA engine to move data
in either the Peripheral-to-Peripheral (a.k.a. BAM-to-BAM) mode or the
Peripheral-to-Memory (a.k.a. BAM-System) mode. SPS includes BAM (Bus
Access Module) hardware block, BAM DMA peripheral, and pipe memory.
Required property:
- compatible: should be "qcom,msm-sps" or "qcom,msm-sps-4k"
Optional properties:
- reg: offset and size for the memory mapping, including maps for
BAM DMA BAM, BAM DMA peripheral, pipe memory and reserved memory.
- reg-names: indicates various resources passed to driver (via reg
property) by name. "reg-names" examples are "bam_mem", "core_mem"
, "pipe_mem" and "res_mem".
- interrupts: IRQ line
- qcom,device-type: specify the device configuration of BAM DMA and
pipe memory. Can be one of
1 - With BAM DMA and without pipe memory
2 - With BAM DMA and with pipe memory
3 - Without BAM DMA and without pipe memory
- qcom,pipe-attr-ee: BAM pipes are attributed to a specific EE, with
which we can know the pipes belong to apps side and can have the
error interrupts at the pipe level.
- clocks: This property shall provide a list of entries each of which
contains a phandle to clock controller device and a macro that is
the clock's name in hardware.These should be "clock_rpm" as clock
controller phandle and "clk_pnoc_sps_clk" as macro for "dfab_clk"
and "clock_gcc" as clock controller phandle and "clk_gcc_bam_dma_ahb_clk"
as macro for "dma_bam_pclk".
- clock-names: This property shall contain the clock input names used
by driver in same order as the clocks property.These should be "dfab_clk"
and "dma_bam_pclk".
Example:
qcom,sps@f9980000 {
compatible = "qcom,msm-sps";
reg = <0xf9984000 0x15000>,
<0xf9999000 0xb000>,
<0xfe803000 0x4800>;
interrupts = <0 94 0>;
qcom,device-type = <2>;
qcom,pipe-attr-ee;
clocks = <&clock_rpm clk_pnoc_sps_clk>,
<&clock_gcc clk_gcc_bam_dma_ahb_clk>;
clock-names = "dfab_clk", "dma_bam_pclk";
};

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%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/edac/kryo-edac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Kryo EDAC(Error Detection and Correction) node binding
maintainers:
- Murali Nalajala <mnalajal@quicinc.com>
description: |+
Kryo EDAC node is defined to describe on-chip error detection and correction
for the Kryo core.
Kryo will report all SBE and DBE found in L1/L2/L3/SCU caches in two registers:
ERRXSTATUS - Error Record Primary Status Register
ERRXMISC0 - Error Record Miscellaneous Register
Current implementation of Kryo ECC mechanism is based on interrupts.
The following section describes the DT node binding for kryo_cpu_erp.
properties:
compatible:
const: arm,arm64-kryo-cpu-erp
description:
Implements cache error detection and correction for Kryo CPUs.
interrupts:
description: Interrupt-specifier for L1/L2, L3/SCU error IRQ(s)
interrupt-names:
description: Descriptive names of the interrupts
required:
- compatible
- interrupts
- interrupt-names
examples:
- |
kryo-erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq",
"l1-l2-errirq",
"l3-scu-errirq",
"l3-scu-faultirq";
};

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* TZLOG (Trust Zone Log)
The tz_log driver is a platform device driver that exposes a debugfs
interface for accessing and displaying diagnostic information
related to secure code (Trustzone/QSEE).
Required properties:
- compatible : Should be "qcom,tz-log"
- reg : Offset and size of the register set for the device
Optional properties:
- qcom,hyplog-enabled : (boolean) indicates if driver supports HYP logger service.
- hyplog-address-offset : Register offset to get the HYP log base address.
- hyplog-size-offset : Register offset to get the HYP log size parameter.
Example:
qcom,tz-log@146bf720 {
compatible = "qcom,tz-log";
reg = <0x146bf720, 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = 0x410;
hyplog-size-offset = 0x414;
};

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Qualcomm Technologies, Inc. GPU Graphics Management Unit (GMU)
Required properties:
- compatible :
- "qcom,gpu-gmu"
- "qcom,gpu-gmu-hwsched"
- "qcom,gpu-rgmu"
- "qcom,genc-gmu"
- "qcom,genc-gmu-hwsched"
- reg: Specifies the GMU register base address and size.
- reg-names: Resource names used for the physical address
and length of GMU registers.
- interrupts: Interrupt mapping for GMU and HFI IRQs.
- interrupt-names: String property to describe the name of each interrupt.
Bus Scaling Data:
qcom,msm-bus,name: String property to describe the name of bus client.
qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.
qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.
qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2
<.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n
This property is a series of all vectors for all Bus Scaling Usecases.
Each set of vectors for each usecase describes bandwidth votes for a combination
of src/dst ports. The driver will set the desired use case based on the selected
power level and the desired bandwidth vote will be registered for the port pairs.
GMU GDSC/regulators:
- regulator-names: List of regulator name strings
- vddcx-supply: Phandle for vddcx regulator device node.
- vdd-supply: Phandle for vdd regulator device node.
- clock: List of clocks to be used for GMU register access and DCVS. See
Documentation/devicetree/bindings/clock/clock-bindings.txt
for information about the format. For each clock specified
here, there must be a corresponding entry in clock-names
(see below).
- clock-names: List of clock names corresponding to the clocks specified in
the "clocks" property (above). See
Documentation/devicetree/bindings/clock/clock-bindings.txt
for more info. Currently GMU required these clock names:
"gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk",
"rbcpr_clk"
- List of sub nodes, one for each of the translation context banks needed
for GMU to access system memory in different operating mode. Currently
supported names are:
- gmu_user: used for GMU 'user' mode address space.
- gmu_kernel: used for GMU 'kernel' mode address space.
Each sub node has the following required properties:
- compatible : "qcom,smmu-gmu-user-cb" or "qcom,smmu-gmu-kernel-cb"
- iommus : Specifies the SID's used by this context bank, this
needs to be <kgsl_smmu SID> pair, kgsl_smmu is the string
parsed by iommu driver to match this context bank with the
kgsl_smmu device defined in iommu device tree. On targets
where the msm iommu driver is used rather than the arm smmu
driver, this property may be absent.
Example:
gmu: qcom,gmu@2c6a000 {
label = "kgsl-gmu";
compatible = "qcom,gpu-gmu";
reg = <0x2c6a000 0x30000>;
reg-names = "kgsl_gmu_reg";
interrupts = <0 304 0>, <0 305 0>;
interrupt-names = "kgsl_gmu_irq", "kgsl_hfi_irq";
qcom,msm-bus,name = "cnoc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<26 10036 0 0>, // CNOC off
<26 10036 0 100>; // CNOC on
regulator-name = "vddcx", "vdd";
vddcx-supply = <&gpu_cx_gdsc>;
vdd-supply = <&gpu_gx_gdsc>;
clocks = <&clock_gpugcc clk_gcc_gmu_clk>,
<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
<&clock_gpucc GPU_CC_CXO_CLK>,
<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&clock_gpucc GPU_CC_RBCPR_CLK>;
clock-names = "gmu_clk", "ahb_clk", "cxo_clk",
"axi_clk", "memnoc_clk", "rbcpr_clk";
gmu_user: gmu_user {
compatible = "qcom,smmu-gmu-user-cb";
iommus = <&kgsl_smmu 4>;
};
gmu_kernel: gmu_kernel {
compatible = "qcom,smmu-gmu-kernel-cb";
iommus = <&kgsl_smmu 5>;
};
};

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Qualcomm Technologies, Inc. GPU IOMMU
Required properties:
Required properties:
- compatible : one of:
- "qcom,kgsl-smmu-v1"
- "qcom,kgsl-smmu-v2"
- reg : Base address and size of the SMMU.
- clocks : List of clocks to be used during SMMU register access. See
Documentation/devicetree/bindings/clock/clock-bindings.txt
for information about the format. For each clock specified
here, there must be a corresponding entry in clock-names
(see below).
- clock-names : List of clock names corresponding to the clocks specified in
the "clocks" property (above). See
Documentation/devicetree/bindings/clock/clock-bindings.txt
for more info.
- qcom,protect : The GPU register region which must be protected by a CP
protected mode. On some targets this region must cover
the entire SMMU register space, on others there
is a separate aperture for CP to program context banks.
Optional properties:
- qcom,retention : A boolean specifying if retention is supported on this target
- qcom,global_pt : A boolean specifying if global pagetable should be used.
When not set we use per process pagetables
- qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target
for secure buffer allocation
- List of sub nodes, one for each of the translation context banks supported.
The driver uses the names of these nodes to determine how they are used,
currently supported names are:
- gfx3d_user : Used for the 'normal' GPU address space.
- gfx3d_secure : Used for the content protection address space.
- gfx3d_secure_alt : Used for the content protection address space for alternative SID.
Each sub node has the following required properties:
- compatible : "qcom,smmu-kgsl-cb"
- iommus : Specifies the SID's used by this context bank, this needs to be
<kgsl_smmu SID> pair, kgsl_smmu is the string parsed by iommu
driver to match this context bank with the kgsl_smmu device
defined in iommu device tree. On targets where the msm iommu
driver is used rather than the arm smmu driver, this property
may be absent.
Example:
msm_iommu: qcom,kgsl-iommu@2ca0000 {
compatible = "qcom,kgsl-smmu-v2";
reg = <0x2ca0000 0x10000>;
qcom,protect = <0xa0000 0xc000>;
clocks = <&clock_mmss clk_gpu_ahb_clk>,
<&clock_gcc clk_gcc_mmss_bimc_gfx_clk>,
<&clock_mmss clk_mmss_mmagic_ahb_clk>,
<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>;
clock-names = "gpu_ahb_clk", "bimc_gfx_clk", "mmagic_ahb_clk", "mmagic_cfg_ahb_clk";
qcom,secure_align_mask = <0xfff>;
qcom,retention;
qcom,global_pt;
gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0>,
<&kgsl_smmu 1>;
};
gfx3d_secure: gfx3d_secure {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 2>;
};
gfx3d_secure_alt: gfx3d_secure_alt {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 2>, <&kgsl_smmu 1>;
};
};

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Qualcomm Technologies, Inc. GPU powerlevels
Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins)
can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a
voltage, bus, bandwidth level, and a DVM value.
- qcom,gpu-pwrlevel-bins: Contains one or more qcom,gpu-pwrlevels sets
Properties:
- compatible: Must be qcom,gpu-pwrlevel-bins
- qcom,gpu-pwrlevels: Defines a set of powerlevels
Properties:
- qcom,speed-bin: Speed bin identifier for the set - must match
the value read from the hardware
- qcom,initial-pwrlevel: GPU wakeup powerlevel
- qcom,gpu-pwrlevel: A single powerlevel
- qcom,ca-target-pwrlevel:
This value indicates which qcom,gpu-pwrlevel
to jump on in case of context aware power level
jump.
Required Properties:
- reg: Index of the powerlevel (0 = highest perf)
- qcom,gpu-freq GPU frequency for the powerlevel (in Hz)
- qcom,bus-freq Index to a bus level (defined by the bus
settings).
- qcom,bus-freq-ddrX If specified, define the DDR specific bus
frequency for the power level. X will be the
return value from of_fdt_get_ddrtype().
Optional Properties:
- qcom,bus-min Minimum bus level to set for the power level
- qcom,bus-min-ddrX If specified, define the DDR specific minimum
bus level for the power level. X will be the
return value from of_fdt_get_ddrtype().
- qcom,bus-max maximum bus level to set for the power level
- qcom,bus-max-ddrX If specified, define the DDR specific maximum
bus level for the power level. X will be the
return value from of_fdt_get_ddrtype().
- qcom,acd-level: Value that is used as a register setting for
the ACD power feature. It helps to determine
the threshold for when ACD activates. Zero is
the default value, and the setting where ACD
will never activate.
Example:
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <0>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
qcom,bus-max = <0>;
qcom,acd-level = <0xffffffff>;
};
Example for DDR4/DDR5 specific part:
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <480000000>;
/* DDR5 */
qcom,bus-freq-ddr8 = <10>;
qcom,bus-min-ddr8 = <9>;
qcom,bus-max-ddr8 = <11>;
/* DDR 4 */
qcom,bus-freq-ddr7 = <9>;
qcom,bus-min-ddr7 = <7>;
qcom,bus-max-ddr7 = <9>;
qcom,acd-level = <0xffffffff>;
};

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Qualcomm Technologies, Inc. GPU
Qualcomm Technologies, Inc. Adreno GPU
Required properties:
- compatible: Must be "qcom,kgsl-3d0".
May also includes "qcom,adreno-gpu-*" for few targets.
Must include "qcom,adreno-gpu-a619-holi" for Holi target.
Must include "qcom,adreno-gpu-a660-shima" for Shima target.
Must include "qcom,adreno-gpu-c500" for Waipio target.
Must include "qcom,adreno-gpu-c500v2" for Waipio V2 target.
- reg: Specifies the list of register regions for the device.
- reg-names: Resource names used for the register regions specified
in reg.
- interrupts: Interrupt mapping for GPU nterrupts.
- interrupt-names: String property to describe the names of the interrupts.
- qcom,gpu-bimc-interface-clk-freq:
GPU-BIMC interface clock needs to set to this value for
targets where B/W requirements does not meet GPU Turbo
use cases.
- clocks: List of phandle and clock specifier pairs, one pair
for each clock input to the device.
- clock-names: List of clock input name strings sorted in the same
order as the clocks property.
- qcom,base-leakage-coefficient: Dynamic leakage coefficient.
- qcom,lm-limit: Current limit for GPU limit management.
- qcom,isense-clk-on-level: below or equal this power level isense clock is at XO rate,
above this powerlevel isense clock is at working frequency.
Bus Scaling Data:
- qcom,gpu-bus-table: Defines a bus voting table with the below properties. Multiple sets of bus
voting tables can be defined for given platform based on the type of ddr system.
Properties:
- compatible: Must be "qcom,gpu-bus-table". Additionally, "qcom,gpu-bus-table-ddr" must also
be provided, with the ddr type value(integer) appended to the string.
- qcom,msm-bus,name: String property to describe the name of the 3D graphics processor.
- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases defined in the vectors property.
- qcom,msm-bus,active-only: A boolean flag indicating if it is active only.
- qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.
- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2
<.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n
This property is a series of all vectors for all Bus Scaling Usecases.
Each set of vectors for each usecase describes bandwidth votes for a combination
of src/dst ports. The driver will set the desired use case based on the selected
power level and the desired bandwidth vote will be registered for the port pairs.
Current values of src are:
0 = MSM_BUS_MASTER_GRAPHICS_3D
1 = MSM_BUS_MASTER_GRAPHICS_3D_PORT1
2 = MSM_BUS_MASTER_V_OCMEM_GFX3D
Current values of dst are:
0 = MSM_BUS_SLAVE_EBI_CH0
1 = MSM_BUS_SLAVE_OCMEM
ab: Represents aggregated bandwidth. This value is 0 for Graphics.
ib: Represents instantaneous bandwidth. This value has a range <0 8000 MB/s>
- qcom,ocmem-bus-client: Container for another set of bus scaling properties
qcom,msm-bus,name
qcom,msm-bus,num-cases
qcom,msm-bus,num-paths
qcom,msm-bus,vectors-KBps
to be used by ocmem msm bus scaling client.
GDSC Oxili Regulators:
- regulator-names: List of regulator name strings sorted in power-on order
- vddcx-supply: Phandle for vddcx regulator device node.
- vdd-supply: Phandle for vdd regulator device node.
IOMMU Data:
- iommu: Phandle for the KGSL IOMMU device node
GPU Power levels:
- qcom,gpu-pwrlevel-bins: Container for sets of GPU power levels (see
adreno-pwrlevels.txt)
DCVS Core info
- qcom,dcvs-core-info Container for the DCVS core info (see
dcvs-core-info.txt)
Optional Properties:
- qcom,initial-powerlevel: This value indicates which qcom,gpu-pwrlevel should be used at start time
and when coming back out of resume
- qcom,throttle-pwrlevel: This value indicates which qcom,gpu-pwrlevel LM throttling
may start to occur
- qcom,bus-control: Boolean. Enables an independent bus vote from the gpu frequency
- qcom,bus-width: Bus width in number of bytes. This enables dynamic AB bus voting based on
bus width and actual bus transactions.
- qcom,bus-accesses: Parameter for tuning bus dcvs.
- qcom,bus-accesses-ddrX: Parameter for tuning bus dcvs for each DDR configuration where
X will be the return value from of_fdt_get_ddrtype().
- qcom,gpubw-dev: a phandle to a device representing bus bandwidth requirements
(see devdw.txt)
- qcom,idle-timeout: This property represents the time in milliseconds for idle timeout.
- qcom,no-nap: If it exists software clockgating will be disabled at boot time.
- qcom,chipid: If it exists this property is used to replace
the chip identification read from the GPU hardware.
This is used to override faulty hardware readings.
- qcom,gpu-model: If it exists this property is used for GPU model name.
- qcom,vk-device-id: If it exists this property is used to specify vulkan device ID.
- qcom,disable-wake-on-touch: Boolean. Disables the GPU power up on a touch input event.
- qcom,disable-busy-time-burst:
Boolean. Disables the busy time burst to avoid switching
of power level for large frames based on the busy time limit.
- qcom,pm-qos-active-latency:
Right after GPU wakes up from sleep, driver votes for
acceptable maximum latency to the pm-qos driver. This
voting demands that the system can not go into any
power save state *if* the latency to bring system back
into active state is more than this value.
Value is in microseconds.
- qcom,pm-qos-wakeup-latency:
Similar to the above. Driver votes against deep low
power modes right before GPU wakes up from sleep.
- qcom,l2pc-cpu-mask-latency:
The CPU mask latency in microseconds to avoid L2PC
on masked CPUs.
- qcom,gpu-cx-ipeak:
CX Ipeak is a mitigation scheme which throttles cDSP frequency
if all the clients are running at their respective threshold
frequencies to limit CX peak current.
<phandle bit>
phandle - phandle of CX Ipeak device node
bit - Every bit corresponds to a client of CX Ipeak
driver in the relevant register.
- qcom, gpu-cx-ipeak-freq:
GPU frequency threshold for CX Ipeak voting. GPU votes
to CX Ipeak driver when GPU clock crosses this threshold.
CX Ipeak can limit peak current based on voting from other clients.
- qcom,force-32bit:
Force the GPU to use 32 bit data sizes even if
it is capable of doing 64 bit.
- qcom,gpu-speed-bin: GPU speed bin information in the format
<offset mask shift>
offset - offset of the efuse register from the base.
mask - mask for the relevant bits in the efuse register.
shift - number of bits to right shift to get the speed bin
value.
- qcom,gpu-disable-fuse: GPU disable fuse
<offset mask shift>
offset - offset of the efuse register from the base.
mask - mask for the relevant bits in the efuse register.
shift - number of bits to right shift to get the disable_gpu
fuse bit value.
- qcom,soc-hw-rev-efuse: SOC hardware revision fuse information in the format
<offset bit_position mask>
offset - offset of the efuse register from the base.
bit_position - hardware revision starting bit in the efuse register.
mask - mask for the relevant bits in the efuse register.
- qcom,highest-bank-bit:
Specify the bit of the highest DDR bank. This
is programmed into protected registers and also
passed to the user as a property.
- qcom,min-access-length:
Specify the minimum access length for the chip.
Either 32 or 64 bytes.
Based on the above options, program the appropriate bit into
certain protected registers and also pass to the user as
a property.
- qcom,ubwc-mode:
Specify the ubwc mode for this chip.
1: UBWC 1.0
2: UBWC 2.0
3: UBWC 3.0
Based on the ubwc mode, program the appropriate bit into
certain protected registers and also pass to the user as
a property.
- qcom,l2pc-cpu-mask:
Disables L2PC on masked CPUto the string.rendering thread is running on masked CPUs.
Bit 0 is for CPU-0, bit 1 is for CPU-1...
- qcom,l2pc-update-queue:
Disables L2PC on masked CPUs at queue time when it's true.
- qcom,snapshot-size:
Specify the size of snapshot in bytes. This will override
snapshot size defined in the driver code.
- qcom,enable-ca-jump:
Boolean. Enables use of context aware DCVS
- qcom,ca-busy-penalty:
This property represents the time in microseconds required to
initiate context aware power level jump.
- qcom,ca-target-pwrlevel:
This value indicates which qcom,gpu-pwrlevel to jump on in case
of context aware power level jump.
- qcom,gpu-qdss-stm:
<baseAddr size>
baseAddr - base address of the gpu channels in the qdss stm memory region
size - size of the gpu stm region
- qcom,gpu-qtimer:
<baseAddr size>
baseAddr - base address of the qtimer memory region
size - size of the qtimer region
- qcom,tzone-names:
Specify the names of GPU thermal zones. These will be used
to get gpu temperature from the thermal driver API.
nvmem-cells:
A phandle to the configuration data such as gpu speed bin, gpu gaming mode,
gpu model name provided by a nvmem device. If unspecified default values shall be used.
nvmem-cell-names:
Should be "speed_bin", "gaming_bin", "gpu_model"
GPU Quirks:
- qcom,gpu-quirk-two-pass-use-wfi:
Signal the GPU to set TWOPASSUSEWFI bit in
PC_DBG_ECO_CNTL (5XX and 6XX only)
- qcom,gpu-quirk-critical-packets:
Submit a set of critical PM4 packets when the GPU wakes up
- qcom,gpu-quirk-fault-detect-mask:
Mask out RB1-3 activity signals from HW hang
detection logic
- qcom,gpu-quirk-dp2clockgating-disable:
Disable RB sampler data path clock gating optimization
- qcom,gpu-quirk-lmloadkill-disable:
Use register setting to disable local memory(LM) feature
to avoid corner case error
- qcom,gpu-quirk-hfi-use-reg:
Use registers to replace DCVS HFI message to avoid GMU failure
to access system memory during IFPC
- qcom,gpu-quirk-limit-uche-gbif-rw:
Limit number of read and write transactions from UCHE block to
GBIF to avoid possible deadlock between GBIF, SMMU and MEMNOC.
- qcom,gpu-quirk-mmu-secure-cb-alt:
Select alternate secure context bank to generate SID1 for
secure playback.
KGSL Memory Pools:
- qcom,gpu-mempools: Container for sets of GPU mempools.Multiple sets
(pools) can be defined within qcom,gpu-mempools.
Each mempool defines a pool order, reserved pages,
allocation allowed.
Properties:
- compatible: Must be qcom,gpu-mempools.
- qcom,mempool-max-pages: Max pages for all mempools, If not defined there is no limit.
- qcom,gpu-mempool: Defines a set of mempools.
Properties:
- reg: Index of the pool (0 = lowest pool order).
- qcom,mempool-page-size: Size of page.
- qcom,mempool-reserved: Number of pages reserved at init time for a pool.
- qcom,mempool-allocate: Allocate memory from the system memory when the
reserved pool exhausted.
GPU model configuration:
- qcom,gpu-models:
Container of sets of GPU model names specified by qcom,gpu-models.
Properties:
- compatible:
Must be qcom,gpu-models.
- qcom,gpu-model:
Defines a GPU model name for specific GPU model ID.
Properties:
- compatible:
May also include "qcom,adreno-gpu-*" for few targets.
- qcom,gpu-model-id:
Identifier for the specific GPU hardware configuration - must match the value read
from the hardware.
- qcom,gpu-model:
GPU model name for a specific GPU hardware.
- qcom,vk-device-id:
Vulkan device id unique for specific GPU hardware model.
SOC Hardware revisions:
- qcom,soc-hw-revisions:
Container of sets of SOC hardware revisions specified by
qcom,soc-hw-revision.
Properties:
- compatible:
Must be qcom,soc-hw-revisions.
- qcom,soc-hw-revision:
Defines a SOC hardware revision.
Properties:
- qcom,soc-hw-revision:
Identifier for the hardware revision - must match the value read
from the hardware.
- qcom,chipid:
GPU Chip ID to be used for this hardware revision.
- qcom,gpu-quirk-*:
GPU quirks applicable for this hardware revision.
GPU LLC slice info:
- cache-slice-names: List of LLC cache slices for GPU transactions
and pagetable walk.
- cache-slices: phandle to the system LLC driver, cache slice index.
L3 Power levels:
- qcom,l3-pwrlevels: Container for sets of L3 power levels, the
L3 frequency is adjusted according to the
performance hint received from userspace.
Properties:
- compatible: Must be qcom,l3-pwrlevels
- qcom,l3-pwrlevel: A single L3 powerlevel
Properties:
- reg: Index of the L3 powerlevel
0 = powerlevel for no L3 vote
1 = powerlevel for medium L3 vote
2 = powerlevel for maximum L3 vote
- qcom,l3-freq: The L3 frequency for the powerlevel (in Hz)
GPU coresight info:
The following properties are optional as collecting data via coresight might
not be supported for every chipset. The documentation for coresight
properties can be found in:
Documentation/devicetree/bindings/coresight/coresight.txt
- qcom,gpu-coresights: Container for sets of GPU coresight sources.
- coresight-id: Unique integer identifier for the bus.
- coresight-name: Unique descriptive name of the bus.
- coresight-nr-inports: Number of input ports on the bus.
- coresight-outports: List of output port numbers on the bus.
- coresight-child-list: List of phandles pointing to the children of this
component.
- coresight-child-ports: List of input port numbers of the children.
- coresight-atid: The unique ATID value of the coresight device
Example of A330 GPU in MSM8916:
&soc {
msm_gpu: qcom,kgsl-3d0@1c00000 {
label = "kgsl-3d0";
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
reg = <0x1c00000 0x10000
0x1c20000 0x20000>;
reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";
interrupts = <0 33 0>;
interrupt-names = "kgsl_3d0_irq";
qcom,id = <0>;
qcom,chipid = <0x03000600>;
qcom,initial-pwrlevel = <1>;
/* Idle Timeout = HZ/12 */
qcom,idle-timeout = <8>;
qcom,strtstp-sleepwake;
clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,
<&clock_gcc clk_gcc_oxili_ahb_clk>,
<&clock_gcc clk_gcc_oxili_gmem_clk>,
<&clock_gcc clk_gcc_bimc_gfx_clk>,
<&clock_gcc clk_gcc_bimc_gpu_clk>;
clock-names = "core_clk", "iface_clk", "mem_clk",
"mem_iface_clk", "alt_mem_iface_clk";
/* Bus Scale Settings */
qcom, gpu-bus-table {
compatible="qcom,gpu-bus-table","qcom,gpu-bus-table-ddr7";
qcom,msm-bus,name = "grp3d";
qcom,msm-bus,num-cases = <4>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<26 512 0 0>,
<26 512 0 1600000>,
<26 512 0 3200000>,
<26 512 0 4264000>;
};
/* GDSC oxili regulators */
vdd-supply = <&gdsc_oxili_gx>;
nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_model_bin>;
nvmem-cell-names = "speed_bin", "gaming_bin","gpu_model";
/* IOMMU Data */
iommu = <&gfx_iommu>;
/* Trace bus */
coresight-id = <67>;
coresight-name = "coresight-gfx";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in0>;
coresight-child-ports = <5>;
/* Enable context aware freq. scaling */
qcom,enable-ca-jump;
/* Context aware jump busy penalty in us */
qcom,ca-busy-penalty = <12000>;
/* Context aware jump target power level */
qcom,ca-target-pwrlevel = <1>;
qcom,soc-hw-revisions {
#address-cells = <1>;
#size-cells = <0>;
compatible="qcom,soc-hw-revisions";
qcom,soc-hw-revision@0 {
reg = <0>;
qcom,chipid = <0x06010500>;
qcom,gpu-quirk-hfi-use-reg;
qcom,gpu-quirk-limit-uche-gbif-rw;
};
qcom,soc-hw-revision@1 {
reg = <1>;
qcom,chipid = <0x06010501>;
qcom,gpu-quirk-hfi-use-reg;
};
};
qcom,gpu-models {
#address-cells = <1>;
#size-cells = <0>;
compatible="qcom,gpu-models";
qcom,gpu-model@0 {
compatible="qcom,adreno-gpu-a642l";
qcom,gpu-model-id = <0>;
qcom,gpu-model = "Adreno642Lv1";
qcom,vk-device-id= <0x06030500>;
};
qcom,gpu-model@1 {
compatible="qcom,adreno-gpu-a645";
qcom,gpu-model-id = <190>;
qcom,gpu-model = "Adreno645";
qcom,vk-device-id= <0x06030500>;
};
}
/* GPU Mempools */
qcom,gpu-mempools {
#address-cells= <1>;
#size-cells = <0>;
compatible = "qcom,gpu-mempools";
/* 4K Page Pool configuration */
qcom,gpu-mempool@0 {
reg = <0>;
qcom,mempool-page-size = <4096>;
qcom,mempool-reserved = <2048>;
qcom,mempool-allocate;
};
/* 8K Page Pool configuration */
qcom,gpu-mempool@1 {
reg = <1>;
qcom,mempool-page-size = <8192>;
qcom,mempool-reserved = <1024>;
qcom,mempool-allocate;
};
/* 64K Page Pool configuration */
qcom,gpu-mempool@2 {
reg = <2>;
qcom,mempool-page-size = <65536>;
qcom,mempool-reserved = <256>;
};
/* 1M Page Pool configuration */
qcom,gpu-mempool@3 {
reg = <3>;
qcom,mempool-page-size = <1048576>;
qcom,mempool-reserved = <32>;
};
};
/* Power levels */
qcom,gpu-pwrlevels-bins {
#address-cells = <1>;
#size-cells = <0>;
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <0>;
qcom,ca-target-pwrlevel = <1>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <400000000>;
qcom,bus-freq = <3>;
qcom,io-fraction = <33>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <310000000>;
qcom,bus-freq = <2>;
qcom,io-fraction = <66>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <200000000>;
qcom,bus-freq = <1>;
qcom,io-fraction = <100>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <27000000>;
qcom,bus-freq = <0>;
qcom,io-fraction = <0>;
};
};
};
};
};

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%YAML 1.2
---
$id: http://devicetree.org/schemas/gunyah/virtio_backend.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Virtio backend device for Gunyah hypervisor
maintainers:
- Srivatsa Vaddagiri <svaddagi@qti.qualcomm.com>
- Sreenad Menon <sreemeno@qti.qualcomm.com>
description: |+
Configuration properties for Virtio backend device. This device is
specific to virtio support found in Gunyah hypervisor. The
device helps a virtio backend driver in one Virtual Machine
establish connection with its frontend counterpart in another Virtual
Machine, with both VMs running on Gunyah hypervisor.
properties:
compatible:
oneOf:
- const: qcom,virtio_backend
qcom,vm:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Handle to node that describes common properties of a VM to which this
device belongs.
qcom,label:
$ref: '/schemas/types.yaml#/definitions/uint32'
description:
Unique label associated with the device. This label is used to identify
the right device which is the target of ioctl() calls.
required:
- compatible
- qcom,vm
- qcom,label
example:
- |
trustedvm: trustedvm@0 {
reg = <0x0 0xdff00000 0x0 100000>;
vm_name = "trustedvm";
};
virtio_backend@0 {
compatible = "qcom,virtio_backend";
qcom,vm = <&trustedvm>;
qcom,label = <0x10200>;
};

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%YAML 1.2
---
$id: http://devicetree.org/schemas/gunyah/vm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Virtual Machine (VM) Configuration
maintainers:
- Venkata Narendra Kumar Gutta <vgutta@quicinc.com>
- Murali Nalajala <mnalajal@quicinc.com>
description: |+
Configuration properties for Virtual Machines. This configuration
is used by virtual machine manager and know about various
properties of VM before it launch the virtual machine
properties:
compatible:
oneOf:
- const: qcom,vm-1.0
vm-type:
description: type of virtual machine e.g aarch64, x86 etc
oneOf:
- const: aarch64-guest
boot-config:
oneOf:
- const: fdt,unified
os-type:
description: Type of the operating system being used in virtual machine
oneOf:
- const: linux
kernel-entry-segment:
$ref: /schemas/types.yaml#/definitions/string-array
kernel-entry-offset:
$ref: '/schemas/types.yaml#/definitions/uint64'
vendor:
$ref: /schemas/types.yaml#/definitions/string-array
image-name:
$ref: /schemas/types.yaml#/definitions/string-array
qcom,pasid:
$ref: '/schemas/types.yaml#/definitions/uint64'
memory:
properties:
"#address-cells":
const: 2
"#size-cells":
const: 2
base-address:
description: Base address of the memory for virtual machine
maxItems: 2
size-min:
description: Size of the memory that is being used by the virtual machine
maxItems: 2
segments:
properties:
kernel:
maxItems: 4
description: Load location offset of the kernel
dt:
maxItems: 4
description: Load location offset of devicetree
vcpus:
properties:
config
affinity
affinity-map
interrupts:
properties:
config
vdevices:
properties:
peer-default
required:
- compatible
- image_to_be_loaded

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%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/hwmon/qcom,amoled-ecm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. AMOLED ECM binding
maintainers:
- Shyam Kumar Thella <sthella@qti.qualcomm.com>
description: |
Qualcomm Technologies, Inc. AMOLED ECM supports measurement of OLED
display power/current consumption with a time granularity in sub-frame
or multiple frames of image data. A power measurement can be for a
shorter period or for a longer period.
properties:
compatible:
const: qcom,amoled-ecm
reg:
description: Base address of AMOLED AB module. Registers of
AMOLED ECM are part of AMOLED AB module.
maxItems: 1
nvmem-names:
minItems: 1
description: Array of one or more nvmem device name(s) for ECM
measurement.
items:
- const: amoled-ecm-sdam0
- const: amoled-ecm-sdam1
$ref: /schemas/types.yaml#/definitions/string-array
nvmem:
minItems: 1
description: Array of one or more phandles of the nvmem device(s)
for ECM measurement.
$ref: /schemas/nvmem/nvmem.yaml
interrupts:
description: Specifies the interrupts for nvmem devices used by
AMOLED ECM.
minItems: 1
$ref: /schemas/interrupts.yaml
interrupt-names:
description: Specifies the interrupt names for nvmem devices used
by AMOLED ECM.
minItems: 1
items:
- const: ecm-sdam0
- const: ecm-sdam1
$ref: /schemas/types.yaml#/definitions/string-array
display-panels:
minItems: 1
description: Array of one or more phandles of the display panel(s)
that sends the DRM blank/unblank notifications.
$ref: /schemas/types.yaml#/definitions/phandle-array
required:
- compatible
- reg
- nvmem-names
- nvmem
- interrupt-names
- interrupts
examples:
- |
qcom,amoled-ecm@f900 {
compatible = "qcom,amoled-ecm";
reg = <0xf900>;
nvmem-names = "amoled-ecm-sdam0", "amoled-ecm-sdam1";
nvmem = <&pmk8350_sdam_13>, <&pmk8350_sdam_14>;
interrupt-names = "ecm-sdam0", "ecm-sdam1";
interrupts = <0x0 0x7c 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x7d 0x1 IRQ_TYPE_EDGE_RISING>;
};

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GENI based Qualcomm Technologies Inc Universal Peripheral version 3 (QUPv3)
I2C controller
Required properties:
- compatible: Should be:
* "qcom,i2c-geni.
- reg: Should contain QUP register address and length.
- interrupts: Should contain I2C interrupt.
- clocks: Serial engine core clock, and AHB clocks needed by the device.
- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
should be "active" and "sleep" for the pin confuguration when core is active
or when entering sleep state.
- #address-cells: Should be <1> Address cells for i2c device address
- #size-cells: Should be <0> as i2c addresses have no size component
- qcom,wrapper-core: Wrapper QUPv3 core containing this I2C controller.
Optional property:
- qcom,clk-freq-out : Desired I2C bus clock frequency in Hz.
When missing default to 400000Hz.
- qcom,shared : Boolean flag to support multi-ee usecase, used in GSI mode.
Needs to be added by client driver node in case of multi-ee usecase.
- qcom,le-vm : Boolean flag to support I2C functionality in trusted VM.
Child nodes should conform to i2c bus binding.
Example:
i2c@a94000 {
compatible = "qcom,i2c-geni";
reg = <0xa94000 0x4000>;
interrupts = <GIC_SPI 358 0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qup_1_i2c_5_active>;
pinctrl-1 = <&qup_1_i2c_5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
qcom,wrapper-core = <&qupv3_0>;
qcom,clk-freq-out = <400000>;
};

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Qualcomm Technologies, Inc. GENI I3C master block
Generic bindings document for GENI I3C master controller driver.
Required properties:
- compatible: shall be "qcom,geni-i3c".
- clocks: shall reference the se clock.
- clock-names: shall contain clock name corresponding to the serial engine.
- interrupts: the interrupt line connected to this I3C master.
- reg: I3C master registers.
- qcom,wrapper-core: Wrapper QUPv3 core containing this I3C controller.
- qcom,ibi-ctrl-id: IBI controller instance number.
Optional properties:
- se-clock-frequency: Source serial clock frequency to use.
- dfs-index: Dynamic frequency scaling table index to use.
Mandatory properties defined by the generic binding (see
Documentation/devicetree/bindings/i3c/i3c.txt for more details):
- #address-cells: shall be set to 3.
- #size-cells: shall be set to 0.
Optional properties defined by the generic binding (see
Documentation/devicetree/bindings/i3c/i3c.txt for more details):
- i2c-scl-hz: frequency for i2c transfers.
- i3c-scl-hz: frequency for i3c transfers.
I3C device connected on the bus follow the generic description (see
Documentation/devicetree/bindings/i3c/i3c.txt for more details).
Example:
i3c0: i3c-master@980000 {
compatible = "qcom,geni-i3c";
reg = <0x980000 0x4000>,
<0xec30000 0x10000>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i3c_active>;
pinctrl-1 = <&qupv3_se0_i3c_sleep>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <0>;
qcom,wrapper-core = <&qupv3_0>;
qcom,ibi-ctrl-id = <0>;
};

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Qualcomm's SPMI PMIC ADC
- SPMI PMIC voltage ADC (VADC) provides interface to clients to read
voltage. The VADC is a 15-bit sigma-delta ADC.
- SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read
voltage. The VADC is a 16-bit sigma-delta ADC.
VADC node:
- compatible:
Usage: required
Value type: <string>
Definition: Should contain "qcom,spmi-vadc".
Should contain "qcom,spmi-adc7" for PMIC7 ADC driver.
Should contain "qcom,spmi-adc5" for PMIC5 ADC driver.
Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver.
Should contain "qcom,pms405-adc" for PMS405 PMIC
Should contain "qcom,spmi-adc5-lite" for PMIC5 ADC-lite driver.
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: VADC base address in the SPMI PMIC register map.
- #address-cells:
Usage: required
Value type: <u32>
Definition: Must be one. Child node 'reg' property should define ADC
channel number.
- #size-cells:
Usage: required
Value type: <u32>
Definition: Must be zero.
- #io-channel-cells:
Usage: required
Value type: <u32>
Definition: Must be one. For details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
- interrupts:
Usage: optional
Value type: <prop-encoded-array>
Definition: End of conversion interrupt.
Channel node properties:
- reg:
Usage: required
Value type: <u32>
Definition: ADC channel number.
See include/dt-bindings/iio/qcom,spmi-vadc.h
- label:
Usage: required for "qcom,spmi-adc5", "qcom,spmi-adc7" and "qcom,spmi-adc-rev2"
Value type: <empty>
Definition: ADC input of the platform as seen in the schematics.
For thermistor inputs connected to generic AMUX or GPIO inputs
these can vary across platform for the same pins. Hence select
the platform schematics name for this channel.
- qcom,decimation:
Usage: optional
Value type: <u32>
Definition: This parameter is used to decrease ADC sampling rate.
Quicker measurements can be made by reducing decimation ratio.
- For compatible property "qcom,spmi-vadc", valid values are
512, 1024, 2048, 4096. If property is not found, default value
of 512 will be used.
- For compatible property "qcom,spmi-adc5", valid values are
250, 420 and 840. If property is not found, default value of
840 is used.
- For compatible property "qcom,spmi-adc7", valid values are
85, 340 and 1360. If property is not found, default value of
1360 is used.
- For compatible property "qcom,spmi-adc-rev2", valid values are 256,
512 and 1024. If property is not present, default value is 1024.
- qcom,pre-scaling:
Usage: optional
Value type: <u32 array>
Definition: Used for scaling the channel input signal before the signal is
fed to VADC. The configuration for this node is to know the
pre-determined ratio and use it for post scaling. Select one from
the following options.
<1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10>, <1 16>,
<32 100>, <14, 100>, <28, 100>, <1000 305185>, <1000 610370>
If property is not found default value depending on chip will be used.
- qcom,ratiometric:
Usage: optional
Value type: <empty>
Definition: Channel calibration type.
- For compatible property "qcom,spmi-vadc", if this property is
specified VADC will use the VDD reference (1.8V) and GND for
channel calibration. If property is not found, channel will be
calibrated with 0.625V and 1.25V reference channels, also
known as absolute calibration.
- For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
"qcom,spmi-adc-rev2", if this property is specified VADC will
use the VDD reference (1.875V) and GND for channel calibration.
If property is not found, channel will be calibrated with 0V
and 1.25V reference channels, also known as absolute calibration.
- qcom,hw-settle-time:
Usage: optional
Value type: <u32>
Definition: Time between AMUX getting configured and the ADC starting
conversion. The 'hw_settle_time' is an index used from valid values
and programmed in hardware to achieve the hardware settling delay.
- For compatible property "qcom,spmi-vadc" and "qcom,spmi-adc-rev2",
Delay = 100us * (hw_settle_time) for hw_settle_time < 11,
and 2ms * (hw_settle_time - 10) otherwise.
Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800,
900 us and 1, 2, 4, 6, 8, 10 ms.
If property is not found, channel will use 0us.
- For compatible property "qcom,spmi-adc5", delay = 15us for
value 0, 100us * (value) for values < 11,
and 2ms * (value - 10) otherwise.
Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 800,
900 us and 1, 2, 4, 6, 8, 10 ms
Certain controller digital versions have valid values of
15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms
If property is not found, channel will use 15us.
- For compatible property "qcom,spmi-adc7", delay = 15us for
value 0, 100us * (value) for values < 8, 1ms for value 8
and 2ms * (value - 8) otherwise.
Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000,
4000, 8000, 16000, 32000, 64000, 128000 us.
If property is not found, channel will use 15us.
- qcom,avg-samples:
Usage: optional
Value type: <u32>
Definition: Number of samples to be used for measurement.
Averaging provides the option to obtain a single measurement
from the ADC that is an average of multiple samples. The value
selected is 2^(value).
- For compatible property "qcom,spmi-vadc", valid values
are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512
If property is not found, 1 sample will be used.
- For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7"
and "qcom,spmi-adc-rev2", valid values are: 1, 2, 4, 8, 16.
If property is not found, 1 sample will be used.
- qcom,scale-fn-type:
Usage: optional
Value type: <u32>
Definition: The index of the VADC scale function used to convert raw ADC
code to physical scaled units for the channel. Defined for compatible
properties "qcom,spmi-adc5" and "qcom,spmi-adc7".
See include/dt-bindings/iio/qcom,spmi-vadc.h.
NOTE:
For compatible property "qcom,spmi-vadc" following channels, also known as
reference point channels, are used for result calibration and their channel
configuration nodes should be defined:
VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV,
VADC_GND_REF and VADC_VDD_VADC.
Example:
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <linux/irq.h>
/* ... */
/* VADC node */
pmic_vadc: vadc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
io-channel-ranges;
/* Channel node */
adc-chan@VADC_LR_MUX10_USB_ID {
reg = <VADC_LR_MUX10_USB_ID>;
qcom,decimation = <512>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,avg-samples = <1>;
qcom,pre-scaling = <1 3>;
};
};
/* IIO client node */
usb {
io-channels = <&pmic_vadc VADC_LR_MUX10_USB_ID>;
io-channel-names = "vadc";
};

30
bindings/input/qcom,pm8941-pwrkey.txt
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@@ -8,11 +8,24 @@ PROPERTIES
Definition: must be one of:
"qcom,pm8941-pwrkey"
"qcom,pm8941-resin"
"qcom,pmk8350-pwrkey"
"qcom,pmk8350-resin"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: base address of registers for block
Definition: Specifies the SPMI base address for the PON (power-on)
peripheral. For PMICs that have PON peripheral (GEN3) split
into PON_HLOS and PON_PBS (e.g. PMK8350), this can hold
addresses of both PON_HLOS and PON_PBS peripherals.
In that case, the PON_PBS address needs to be specified
to facilitate software debouncing on some PMICs.
- reg-names:
Usage: optional
Value type: <stringlist>
Definition: For PON GEN1 and GEN2, it should be "pon". For PON GEN3, it
should include "pon_hlos" and optionally "pon_pbs".
- interrupts:
Usage: required
@@ -25,13 +38,16 @@ PROPERTIES
Usage: optional
Value type: <u32>
Definition: time in microseconds that key must be pressed or released
for state change interrupt to trigger.
for state change interrupt to trigger. Note that this
property isn't meaningful for PMK8350 or other PON GEN3
PMICs.
- bias-pull-up:
Usage: optional
Value type: <empty>
Definition: presence of this property indicates that the KPDPWR_N pin
should be configured for pull up.
should be configured for pull up. Note that this property
isn't meaningful for PMK8350 or other PON GEN3 PMICs.
- linux,code:
Usage: optional
@@ -51,3 +67,11 @@ EXAMPLE
bias-pull-up;
linux,code = <KEY_POWER>;
};
pwrkey@1300 {
compatible = "qcom,pmk8350-pwrkey";
reg = <0x1300>, <0x800>;
reg-names = "pon_hlos", "pon_pbs";
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
};

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Qualcomm Technologies, Inc. High-Voltage Haptics
The High-Voltage Haptics module in QTI PMICs can support either ERM or
LRA actuators with drive voltage up to 10 V. It also has five different
pattern sources (DIRECT_PLAY, PATTERN1, PATTERN2, FIFO, SWR) which can
be used for playing different vibration effects. This binding document
describes the properties for this PMIC module.
This haptics device supports 2 levels of nodes. The main node defines
the hardware configuration based on the actuator used in the platform.
Child nodes define the configurations for different haptics effects
that can be supported.
Properties:
- compatible:
Usage: required
Value type: <string>
Definition: It can be one of following:
"qcom,hv-haptics",
"qcom,pm8350b-haptics".
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Register base for following haptics modules: HAPTICS_CFG,
HAPTICS_PATTERN, HAPTICS_BOOST.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: Peripheral interrupt specifier.
- interrupt-names:
Usage: required
Value type: <string>
Definition: Interrupt names. This string list must match up 1-to-1 with
the interrupts specified in the 'interrupts' property.
The following interrupt is required: "fifo-empty".
- qcom,vmax-mv:
Usage: optional
Value type: <u32>
Definition: Specifies the maximum allowed output voltage in millivolts
for the actuator. The value specified here will be rounded
off to the closest multiple of 50 mV. Allowed values: 0 to
11000. If this is not specified, 5000 mV will be used by
default.
- qcom,brake-mode:
Usage: optional
Value type: <u32>
Definition: Specifies vibration brake mode. Please refer to:
include/dt-bindings/input/qcom,hv-haptics.h.
If this is not defined, "auto" brake mode will be used
by default.
- qcom,brake-disable:
Usage: optional
Value type: <bool>
Definition: Specifies if vibation brake is disabled.
- qcom,brake-pattern:
Usage: optional
Value type: <prop-encoded-array>
Definition: Specifies the brake pattern in a byte array which is less
than 8 elements. The array needs to be specified as 8-bit
using '/bits/ 8' parameter. The pattern will be played at the
end of the playing waveform if manual brake mode (either
open-loop or close-loop) is selected. If this is not defined,
or if it's defined as an array with all zeros, then manual
brake is disabled.
- qcom,fifo-empty-threshold:
Usage: optional
Value type: <u32>
Definition: Specifies the FIFO empty threshold. The "fifo-empty" IRQ will be
triggered when the number of the samples in the FIFO is less
than the threshold. For PM8350B v1, allowed value is 1 - 103
and the default value is 48. For PM8350B v2, allowed value is
1 - 639 and the default value is 280.
- qcom,use-erm:
Usage: optional
Value type: <bool>
Definition: Specifies if the hardware is driving an ERM actuator. If it's
not defined, then LRA actuator is used.
- nvmem-cell-names:
Usage: optional
Value type: <string>
Definition: The nvmem cell name of the SDAM module where the closed-loop
brake calibration settings can be stored. It must be
"hap_cl_brake".
- nvmem-cells:
Usage: optional
Value type: <phandle>
Definition: Phandle of the nvmem cell to store the closed-loop brake
calibration settings. Please refer to nvmem bindings as
described in bindings/nvmem/nvmem.txt.
- nvmem-names:
Usage: optional
Value type: <string>
Definition: The nvmem device name of the SDAM module used for haptics
configuration. It must be "hap_cfg_sdam".
- nvmem:
Usage: optional
Value type: <phandle>
Definition: Phandle of the nvmem device used for haptics configuration.
Please refer to nvmem bindings as described in bindings/nvmem/nvmem.txt.
- qcom,pbs-client:
Usage: optional
Value type: <phandle>
Definition: Phandle of the PBS client used for triggering PBS to configure
haptics ISC (short circuit current) config during LRA impedance
detection.
The following properties are only required when LRA actuator is used:
- qcom,lra-period-us:
Usage: required
Value type: <u32>
Definition: Specifies the initial resonance period in microseconds for
LRA actuator. It has to be specified if an LRA actuator is
used. Allowed values: 5 to 20475.
- qcom,drv-sig-shape:
Usage: optional
Value type: <u32>
Definition: Specifies the drive signal shape for LRA. Please refer to:
include/dt-bindings/input/qcom,hv-haptics.h.
The "sine" drive signal is used by default if this property
is not defined.
- qcom,brake-sig-shape:
Usage: optional
Value type: <u32>
Definition: Specifies the reverse brake signal shape. Please refer to:
include/dt-bindings/input/qcom,hv-haptics.h.
The "sine" brake signal is used by default if this property
is not defined.
- qcom,brake-sine-gain:
Usage: optional
Value type: <u32>
Definition: Specifies the brake signal gain when sine brake signal shape
is selected. Please refer to:
include/dt-bindings/input/qcom,hv-haptics.h.
A child node named "qcom,hap-swr-slave-reg" can be defined to export a regulator
device which is used for swr-haptics module to control the online status of SWR
slave. The child node should have following property for this regulator device:
- regulator-name: Please refer to: bindings/regulator/regulator.txt.
The following properties should be specified in child nodes for defining
different vibration effects:
- qcom,effect-id:
Usage: required
Value type: <u32>
Definition: Specifies the effect ID that a client can request to play
the corresponding effect definition in this child node. The ID
is normaly defined and sent from userspace for certain user
notification event.
- qcom,wf-vmax-mv:
Usage: optional
Value type: <u32>
Definition: Specifies maximum allowed output voltage in millivolts for
this effect. Value specified here will be rounded off to
the closest multiple of 50 mV. Allowed values: 0 to 11000. If
this is not specified, the value of "qcom,vmax-mv" which is
defined in the parent node will be used.
- qcom,wf-pattern-data:
Usage: required
Value type: <prop-encoded-array>
Definition: Defines an array of 8 3-tuples in which each tuple specifies
the 3-element pattern data that will be played in PATTERN1
source mode by default. The 3 elements of each tuple are:
[0] => 9-bit pattern amplitude.
[1] => play period for this pattern amplitude. See
include/dt-bindings/input/qcom,hv-haptics.h
[2] => a 0/1 flag to indicate if the frequency of the LRA
drive signal will be doubled when playing this pattern.
- qcom,wf-pattern-preload:
Usage: optional
Value type: <bool>
Definition: Specifies if the effect pattern should be preloaded into
PATTERN2 source during boot up and it won't be changed when
device is alive. For the effect that has this property
specified, register configurations are done already for
achieving low latency response. This can be specified only for
one effect.
- qcom,wf-pattern-period-us:
Usage: optional
Value type: <u32>
Definition: Specifies the play period in microseconds for each pattern
entry defined in "qcom,wf-pattern-data". Allowed values:
5 to 20475.
- qcom,wf-fifo-data:
Usage: optional
Value type: <prop-encoded-array>
Definition: Defines a byte array of patterns which will be filled into
the FIFO memory and played when FIFO mode is selected.
The array needs to be specified as 8-bit using '/bits/ 8'
parameter, or using '[]' instead of '<>'.
Either "qcom,wf-pattern-data" or "qcom,wf-fifo-data"
need to be defined in one effect child node. If both are
defined, then the FIFO data defined in this property will be
ignored.
- qcom,wf-fifo-period:
Usage: optional
Value type: <u32>
Definition: Specifies the play period definition for the FIFO data defined
in "qcom,wf-fifo-data".
See definition at: include/dt-bindings/input/qcom,hv-haptics.h
- qcom,wf-brake-mode:
Usage: optional
Value type: <u32>
Definition: Specifies the brake mode for this effect. Please refer to:
include/dt-bindings/input/qcom,hv-haptics.h.
If this is not defined, the brake mode defined in
"qcom,brake-mode" will be used for this effect.
- qcom,wf-brake-pattern:
Usage: optional
Value type: <prop-encoded-array>
Definition: Specifies manual brake pattern for this effect. The array needs
to be specified as 8-bit using '/bits/ 8' parameter.
If it's not defined, the brake pattern defined in
"qcom,brake-pattern" will be used for this effect.
- qcom,wf-brake-disable:
Usage: optional
Value type: <bool>
Definition: Specifies if the vibration brake is disabled for this effect.
- qcom,wf-brake-sine-gain:
Usage: optional
Value type: <u32>
Definition: Specifies the brake sine signal gain for this effect when sine
brake signal shape is selected. Please refer to:
include/dt-bindings/input/qcom,hv-haptics.h.
- qcom,wf-auto-res-disable:
Usage: optional
value type: <bool>
Definition: Specifies if the effect will be played with LRA auto resonance
feature disabled.
Example:
qcom,hv-haptics@f000 {
compatible = "qcom,hv-haptics";
reg = <0xf000>, <0xf100>, <0xf200>;
interrupts = <0x3 0xf0 0x1 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "fifo-empty";
nvmem-cell-names = "hap_cl_brake";
nvmem-cells = <&hap_cl_brake>;
nvmem-names = "hap_cfg_sdam";
nvmem = <&pmk8350_sdam_46>;
qcom,pbs-client = <&pm8350b_pbs2>;
qcom,vmax-mv = <900>;
qcom,brake-mode = <BRAKE_CLOSE_LOOP>;
qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>;
qcom,lra-period-us = <5880>;
qcom,drv-sig-shape = <WF_SINE>;
qcom,brake-sig-shape = <WF_SINE>;
qcom,hap-swr-slave-reg {
regulator-name = "hap-swr-slave-reg";
};
effect_0 {
/* CLICK effect */
qcom,effect-id = <0>;
qcom,wf-vmax-mv = <8000>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <5000>;
qcom,wf-brake-pattern = /bits/ 8 <0xff 0x7f 0x3f>;
qcom,wf-pattern-preload;
qcom,wf-auto-res-disable;
};
effect_1 {
/* DOUBLE_CLICK effect */
qcom,effect-id = <1>;
qcom,wf-vmax-mv = <5000>;
qcom,wf-fifo-data = /bits/ 8 <0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff>;
qcom,wf-fifo-period = <S_PERIOD_F_8KHZ>;
qcom,wf-brake-pattern = /bits/ 8 <0x7f 0x5f 0x3f>;
qcom,wf-auto-res-disable;
};
};

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Qualcomm Technologies, Inc. QPNP Power-on PMIC Peripheral Device Tree Bindings
qpnp-power-on devices support the power-on (PON) peripheral found on
Qualcomm Technologies, Inc. PMICs. The supported functionality includes power
on/off reason, key press/release detection, PMIC reset configurations and other
PON specific features. The PON module supports multiple physical power-on
(KPDPWR_N, CBLPWR) and reset (KPDPWR_N, RESIN, KPDPWR+RESIN) sources. This
peripheral is connected to the host processor via the SPMI interface.
Required properties:
- compatible: Must be "qcom,qpnp-power-on"
- reg: Specifies the SPMI base address for this PON
(power-on) peripheral.
Optional properties:
- interrupts: Specifies the interrupts associated with PON.
- interrupt-names: Specifies the interrupt names associated with
the interrupts property. Must be a subset of
"kpdpwr", "kpdpwr-bark", "resin", "resin-bark",
"cblpwr", "kpdpwr-resin-bark", and
"pmic-wd-bark". Bark interrupts are associated
with system reset configuration to allow default
reset configuration to be activated. If system
reset configuration is not supported then bark
interrupts are nops. Additionally, the
"pmic-wd-bark" interrupt can be added if the
system needs to handle PMIC watchdog barks.
- qcom,pon-dbc-delay: The debounce delay for the power-key interrupt
specified in us.
Possible values for GEN1 PON are:
15625, 31250, 62500, 125000, 250000, 500000,
1000000 and 2000000.
Possible values for GEN2 PON are:
62, 123, 245, 489, 977, 1954, 3907, 7813,
15625, 31250, 62500, 125000 and 250000.
Intermediate value is rounded down to the
nearest valid value.
- qcom,system-reset: Boolean which specifies that this PON peripheral
can be used to reset the system. This property
can only be used by one device on the system. It
is an error to include it more than once.
- qcom,modem-reset: Boolean which specifies that this PON peripheral
can be used to reset the attached modem chip.
This property can only be used by one PON device
on the system. qcom,modem-reset and
qcom,system-reset cannot be specified for the
same PON device.
- qcom,s3-debounce: The debounce delay for stage 3 reset trigger in
secs. The values range from 0 to 128.
- qcom,s3-src: The source for stage 3 reset. It can be one of
"kpdpwr", "resin", "kpdpwr-or-resin" or
"kpdpwr-and-resin".
- qcom,uvlo-panic: Boolean indicating that the device should
trigger a controlled panic shutdown if a restart
was caused by under voltage lock-out (UVLO).
- qcom,clear-warm-reset: Boolean which specifies that the WARM_RESET
reason registers need to be cleared for this
target. The property is used for the targets
which have a hardware feature to catch resets
which aren't triggered by the application
processor. In such cases clearing WARM_REASON
registers across processor resets keeps the
registers in a useful state.
- qcom,secondary-pon-reset: Boolean property which indicates that the PON
peripheral is a secondary PON device which
needs to be configured during reset in addition
to the primary PON device that is configured
for system reset through qcom,system-reset
property.
This should not be defined along with the
qcom,system-reset or qcom,modem-reset property.
- qcom,store-hard-reset-reason: Boolean property which if set will store the
hardware reset reason to SOFT_RB_SPARE register
of the core PMIC PON peripheral.
- qcom,warm-reset-poweroff-type: Poweroff type required to be configured
on PS_HOLD reset control register when the
system goes for warm reset. If this property is
not specified, then the default type, warm reset
will be configured to PS_HOLD reset control
register.
Supported values: PON_POWER_OFF_TYPE_* found in
include/dt-bindings/input/qcom,qpnp-power-on.h
- qcom,hard-reset-poweroff-type: Same description as
qcom,warm-reset-poweroff-type but this applies
for the system hard reset case.
- qcom,shutdown-poweroff-type: Same description as qcom,warm-reset-poweroff-
type but this applies for the system shutdown
case.
- qcom,kpdpwr-sw-debounce: Boolean property to enable the debounce logic
on the KPDPWR_N rising edge.
- qcom,resin-pon-reset: Boolean property which indicates that resin
needs to be configured during reset in addition
to the primary PON device that is configured
for system reset through qcom,system-reset
property.
- qcom,resin-warm-reset-type: Poweroff type required to be configured on
RESIN reset control register when the system
initiates warm reset. If this property is not
specified, then the default type, warm reset
will be configured to RESIN reset control
register. This property is effective only if
qcom,resin-pon-reset is defined.
Supported values: PON_POWER_OFF_TYPE_* found in
include/dt-bindings/input/qcom,qpnp-power-on.h
- qcom,resin-hard-reset-type: Same description as qcom,resin-warm-reset-type
but this applies for the system hard reset case.
- qcom,resin-shutdown-type: Same description as qcom,resin-warm-reset-type
but this applies for the system shutdown case.
- qcom,resin-shutdown-disable: Boolean property to disable RESIN power off
trigger during system shutdown case.
This property is effective only if
qcom,resin-pon-reset is defined.
- qcom,resin-hard-reset-disable: Boolean property to disable RESIN power
off trigger during system hard reset case.
This property is effective only if
qcom,resin-pon-reset is defined.
- qcom,ps-hold-shutdown-disable: Boolean property to disable PS_HOLD
power off trigger during system shutdown case.
- qcom,ps-hold-hard-reset-disable: Boolean property to disable PS_HOLD
power off trigger during system hard reset case.
Optional Sub-nodes:
- qcom,pon_1 ... qcom,pon_n: These PON child nodes correspond to features
supported by the PON peripheral including reset
configurations, pushbutton keys, and regulators.
Sub-node properties:
Sub-nodes (if defined) should belong to either a PON configuration or a
regulator configuration.
Regulator sub-node required properties:
- regulator-name: Regulator name for the PON regulator that is
being configured.
- qcom,pon-spare-reg-addr: Register offset from the base address of the
PON peripheral that needs to be configured for
the regulator being controlled.
- qcom,pon-spare-reg-bit: Bit position in the specified register that
needs to be configured for the regulator being
controlled.
PON sub-node required properties:
- qcom,pon-type: The type of PON/RESET source. Supported values:
0 = KPDPWR
1 = RESIN
2 = CBLPWR
3 = KPDPWR_RESIN
These values are PON_POWER_ON_TYPE_* found in
include/dt-bindings/input/qcom,qpnp-power-on.h
PON sub-node optional properties:
- qcom,pull-up: Boolean flag indicating if a pull-up resistor
should be enabled for the input.
- qcom,support-reset: Indicates if this PON source supports
reset functionality.
0 = Not supported
1 = Supported
If this property is not defined, then default S2
reset configurations should not be modified.
- qcom,use-bark: Specify if this PON type needs to handle a bark
interrupt.
- linux,code: The input key-code associated with the reset
source. The reset source in its default
configuration can be used to support standard
keys.
The below mentioned properties are required only when qcom,support-reset DT
property is defined and is set to 1.
- qcom,s1-timer: The debounce timer for the BARK interrupt for
the reset source. Value is specified in ms.
Supported values are:
0, 32, 56, 80, 128, 184, 272, 408, 608, 904,
1352, 2048, 3072, 4480, 6720, 10256
- qcom,s2-timer: The debounce timer for the S2 reset specified
in ms. On the expiry of this timer, the PMIC
executes the reset sequence.
Supported values are:
0, 10, 50, 100, 250, 500, 1000, 2000
- qcom,s2-type: The type of reset associated with this source.
Supported values:
0 = SOFT_RESET (legacy)
1 = WARM_RESET
4 = SHUTDOWN
5 = DVDD_SHUTDOWN
7 = HARD_RESET
8 = DVDD_HARD_RESET
These values are PON_POWER_OFF_TYPE_* found in
include/dt-bindings/input/qcom,qpnp-power-on.h
Examples:
qcom,power-on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x8 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x8 0x5 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "kpdpwr", "resin", "resin-bark",
"kpdpwr-resin-bark";
qcom,pon-dbc-delay = <15625>;
qcom,system-reset;
qcom,s3-debounce = <32>;
qcom,s3-src = "resin";
qcom,clear-warm-reset;
qcom,store-hard-reset-reason;
qcom,pon_1 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
qcom,pull-up;
linux,code = <KEY_POWER>;
};
qcom,pon_2 {
qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
qcom,support-reset = <1>;
qcom,pull-up;
qcom,s1-timer = <0>;
qcom,s2-timer = <2000>;
qcom,s2-type = <PON_POWER_OFF_TYPE_WARM_RESET>;
linux,code = <KEY_VOLUMEDOWN>;
qcom,use-bark;
};
qcom,pon_3 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR_RESIN>;
qcom,support-reset = <1>;
qcom,s1-timer = <6720>;
qcom,s2-timer = <2000>;
qcom,s2-type = <PON_POWER_OFF_TYPE_HARD_RESET>;
qcom,pull-up;
qcom,use-bark;
};
};
qcom,power-on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
qcom,secondary-pon-reset;
qcom,hard-reset-poweroff-type = <PON_POWER_OFF_TYPE_SHUTDOWN>;
pon_perph_reg: qcom,pon_perph_reg {
regulator-name = "pon_spare_reg";
qcom,pon-spare-reg-addr = <0x8c>;
qcom,pon-spare-reg-bit = <1>;
};
};

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FocalTech touch controller
The focaltech controller is connected to host processor via i2c. The controller generates interrupts when the user touches the panel. The host controller is expected to read the touch coordinates over i2c and pass the coordinates to the rest of the system.
Required properties:
- compatible : should be "focaltech,fts_ts"
- reg : i2c slave address of the device, should be <0x38>; For spi interface, means cs number, always be 0
- interrupt-parent : parent of interrupt
- interrupts : irq gpio, "0x02" stands for that the irq triggered by falling edge.
- focaltech,irq-gpio : irq gpio, same as "interrupts" node.
- focaltech,reset-gpio : reset gpio
- focaltech,num-max-touches : maximum number of touches support
- focaltech,display-coords : display resolution in pixels. A four tuple consisting of minX, minY, maxX and maxY.
Optional properties:
- focaltech,have-key : specify if virtual keys are supported
- focaltech,key-number : number of keys
- focaltech,keys : virtual key codes mapping to the coords
- focaltech,key-x-coords : constant x coordinates of keys, depends on the x resolution
- focaltech,key-y-coords : constant y coordinates of keys, depends on the y resolution
Example:
I2C Interface:
i2c@f9927000 {
focaltech@38{
compatible = "focaltech,fts_ts";
reg = <0x38>;
interrupt-parent = <&msm_gpio>;
interrupts = <13 0x02>;
focaltech,reset-gpio = <&msm_gpio 12 0x01>;
focaltech,irq-gpio = <&msm_gpio 13 0x02>;
focaltech,max-touch-number = <10>;
focaltech,display-coords = <0 0 1080 1920>;
pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
/*
focaltech,have-key;
focaltech,key-number = <3>;
focaltech,keys = <139 102 158>;
focaltech,key-x-coords = <200 600 800>;
focaltech,key-y-coords = <2000 2000 2000>;
*/
};
};
SPI Interface:
spi@78b9000 {
focaltech@0 {
compatible = "focaltech,fts_ts";
reg = <0x0>;
spi-max-frequency = <6000000>;
interrupt-parent = <&msm_gpio>;
interrupts = <13 0x2>;
focaltech,reset-gpio = <&msm_gpio 12 0x01>;
focaltech,irq-gpio = <&msm_gpio 13 0x02>;
focaltech,max-touch-number = <10>;
focaltech,display-coords = <0 0 1080 1920>;
pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
};
};

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Synaptics DSXV27 touch controller
Please add this description here: The Synaptics Touch controller is connected to the
host processor via I2C. The controller generates interrupts when the user touches
the panel. The host controller is expected to read the touch coordinates over I2C and
pass the coordinates to the rest of the system.
Required properties:
- compatible : should be "synaptics,dsx-i2c".
- reg : i2c slave address of the device.
- interrupt-parent : parent of interrupt.
- synaptics,irq-gpio : irq gpio.
- synaptics,reset-gpio : reset gpio.
- vdd_supply : digital voltage power supply needed to power device.
- avdd_supply : analog voltage power supply needed to power device.
- synaptics,pwr-reg-name : power reg name of digital voltage.
- synaptics,bus-reg-name : bus reg name of analog voltage.
Optional property:
- synaptics,ub-i2c-addr : addr of ub-i2c.
- synaptics,irq-on-state : status of irq gpio.
- synaptics,cap-button-codes : virtual key code mappings to be used.
- synaptics,vir-button-codes : virtual key code and the response region on panel.
- synaptics,x-flip : modify orientation of the x axis.
- synaptics,y-flip : modify orientation of the y axis.
- synaptics,reset-delay-ms : reset delay for controller (ms), default 100.
- synaptics,power-delay-ms : power delay for controller (ms), default 100.
- synaptics,reset-active-ms : reset active time for controller (ms), default 20.
- synaptics,max-y-for-2d : maximal y value of the panel.
- clock-names : Clock names used for secure touch. They are: "iface_clk", "core_clk"
- clocks : Defined if 'clock-names' DT property is defined. These clocks
are associated with the underlying I2C bus.
Example:
i2c@78b7000 {
status = "ok";
synaptics@4b {
compatible = "synaptics,dsx-i2c";
reg = <0x4b>;
interrupt-parent = <&tlmm>;
interrupts = <65 0x2008>;
vdd_supply = <&pmtitanium_l17>;
avdd_supply = <&pmtitanium_l6>;
synaptics,pwr-reg-name = "vdd";
synaptics,bus-reg-name = "avdd";
synaptics,ub-i2c-addr = <0x2c>;
synaptics,irq-gpio = <&tlmm 65 0x2008>;
synaptics,reset-gpio = <&tlmm 99 0x2008>;
synaptics,irq-on-state = <0>;
synaptics,power-delay-ms = <200>;
synaptics,reset-delay-ms = <200>;
synaptics,reset-active-ms = <20>;
synaptics,max-y-for-2d = <1919>; /* remove if no virtual buttons */
synaptics,cap-button-codes = <139 172 158>;
synaptics,vir-button-codes = <139 180 2000 320 160 172 540 2000 320 160 158 900 2000 320 160>;
/* Underlying clocks used by secure touch */
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;
};
};

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Qualcomm Technologies, Inc. Waipio Network-On-Chip interconnect driver binding
-----------------------------------------------------------
Waipio interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
Required properties :
- compatible : shall contain only one of the following:
"qcom,waipio-aggre1_noc",
"qcom,waipio-aggre2_noc",
"qcom,waipio-clk_virt",
"qcom,waipio-config_noc",
"qcom,waipio-gem_noc",
"qcom,waipio-lpass_ag_noc",
"qcom,waipio-mc_virt",
"qcom,waipio-mmss_noc",
"qcom,waipio-nsp_noc",
"qcom,waipio-system_noc",
"qcom,waipio-pcie_anoc",
- #interconnect-cells : should contain 1
Examples:
system_noc: interconnect@1680000 {
compatible = "qcom,waipio-system_noc";
interconnect-cells = <1>;
};

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%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/leds/leds-qti-flash.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Flash LED binding.
maintainers:
- Shyam Kumar Thella <sthella@qti.qualcomm.com>
description: |
Qualcomm Technologies, Inc. Flash LED supports camera flash with
multiple LED channels (HW dependent) that can be used for multiple
camera devices which can be configured for pre-flash(torch) and
flash modes.
Flash LED device has two level of nodes. The main node represents
flash LED peripheral and sub node represents the type of device
that uses flash LED channel. It can be a torch, flash or switch.
properties:
compatible:
items:
- const: qcom,pm8350c-flash-led
reg:
description: Base address of flash LED module.
maxItems: 1
interrupts:
description: Specifies the interrupts associated with this device.
interrupt-names:
items:
- const: led-fault-irq
- const: all-ramp-down-irq
- const: all-ramp-up-irq
qcom,thermal-derate-current:
description: Array of current limits for different level of thermal
mitigation.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
qcom,hw-strobe-gpios:
description: Array of one or more phandles to specify GPIOs to use
for strobing flash/torch devices with HW strobe option.
qcom,strobe-sel for flash/torch should be 1 if phandle is specified.
$ref: /schemas/types.yaml#/definitions/phandle-array
patternProperties:
'^qcom,flash_[0-9]$':
type: object
properties:
label:
description: Specifies type of LED that will be used.
allOf:
- $ref: /schemas/types.yaml#/definitions/string-array
items:
- const: flash
qcom,led-name:
description: Specifies the name of flash device.
$ref: /schemas/types.yaml#/definitions/string
qcom,id:
description: Specifies the LED channel number for flash device.
It depends on hardware and starts with an index 0.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1, 2, 3 ]
qcom,default-led-trigger:
description: Trigger for camera flash device.
$ref: /schemas/types.yaml#/definitions/string
qcom,max-current-ma:
description: Maximum current allowed for flash LED device.
Unit is mA.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1600
default: 1600
qcom,duration-ms:
description: Default time duration for flash LED device.
Unit is ms.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
minimum: 10
maximum: 1280
default: 1000
qcom,ires-ua:
description: Current resolution for flash LED device. Unit is uA.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
items:
- const: 5000
- const: 12500
qcom,strobe-sel:
description: Strobe type selection for flash LED device. 0 for
SW strobe and 1 for HW strobe. If not specified, SW strobe is
used.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
qcom,strobe-config:
description: Strobe input selection for flash LED device. Each
flash LED device has independently connected HW strobe inputs
(GPIO1, GPIO2, GPIO3, GPIO4). This is applicable only when HW
strobe is selected.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1, 2, 3 ]
required:
- label
- qcom,led-name
- qcom,default-led-trigger
- qcom,id
- qcom,max-current-ma
'^qcom,torch_[0-9]$':
type: object
properties:
label:
description: Specifies type of LED that will be used.
allOf:
- $ref: /schemas/types.yaml#/definitions/string-array
items:
- const: torch
qcom,led-name:
description: Specifies the name of the torch device.
$ref: /schemas/types.yaml#/definitions/string
qcom,id:
description: Specifies the LED channel number for torch device.
It depends on hardware and starts with an index 0.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1, 2, 3 ]
qcom,default-led-trigger:
description: Trigger for torch device.
$ref: /schemas/types.yaml#/definitions/string
qcom,max-current-ma:
description: Maximum current allowed for torch device.
Unit is mA.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 500
default: 500
qcom,ires-ua:
description: Current resolution for torch device. Unit is uA.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
items:
- const: 5000
- const: 12500
qcom,strobe-sel:
description: Strobe type selection for torch device. 0 for SW
strobe and 1 for HW strobe. If not specified, SW strobe is
used.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
qcom,strobe-config:
description: Strobe input selection for torch device. Each
torch device has independently connected HW strobe inputs
(GPIO1, GPIO2, GPIO3, GPIO4). This is applicable only when
HW strobe is selected.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1, 2, 3 ]
required:
- label
- qcom,led-name
- qcom,default-led-trigger
- qcom,id
- qcom,max-current-ma
'^qcom,switch_[0-9]$':
type: object
properties:
label:
description: Specifies type of LED that will be used.
allOf:
- $ref: /schemas/types.yaml#/definitions/string-array
items:
- const: torch
qcom,led-name:
description: Specifies the name of the switch device.
$ref: /schemas/types.yaml#/definitions/string
qcom,id:
description: Specifies the number of switch device.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1, ]
qcom,default-led-trigger:
description: Trigger for switch device.
$ref: /schemas/types.yaml#/definitions/string
qcom,led-mask:
description: Bit mask indicating group of LEDs that are controlled
by the switch device. It depends on the number of LED channels
present on the LED peripheral.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,symmetry-en:
description: Specify if the flash LEDs under a switch device are
controlled symmetrically. This is specified if a group of LED
channels are connected to single LED.
type: boolean
required:
- label
- qcom,led-name
- qcom,default-led-trigger
- qcom,id
- qcom,led-mask
required:
- compatible
- reg
- qcom,thermal-derate-current
- label
- qcom,led-name
- qcom,default-led-trigger
- qcom,id
- qcom,max-current-ma
- qcom,led-mask
examples:
- |
qcom,leds@ee00 {
compatible = "qcom,pm8350c-flash-led";
reg = <0xee00>;
interrupts = <0x2 0xee 0x0 IRQ_TYPE_EDGE_RISING>,
<0x2 0xee 0x3 IRQ_TYPE_EDGE_RISING>,
<0x2 0xee 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "led-fault-irq",
"all-ramp-down-done-irq",
"all-ramp-up-done-irq";
qcom,thermal-derate-current = <200 500>;
qcom,hw-strobe-gpios = <&pm8350c_gpios 1 0>;
pm8350c_flash0: qcom,flash_0 {
label = "flash";
qcom,led-name = "led:flash_0";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash0_trigger";
qcom,id = <0>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,strobe-sel = <1>;
qcom,strobe-config = <0>;
};
pm8350c_flash1: qcom,flash_1 {
label = "flash";
qcom,led-name = "led:flash_1";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash1_trigger";
qcom,id = <1>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8350c_flash2: qcom,flash_2 {
label = "flash";
qcom,led-name = "led:flash_2";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash2_trigger";
qcom,id = <2>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8350c_flash3: qcom,flash_3 {
label = "flash";
qcom,led-name = "led:flash_3";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash3_trigger";
qcom,id = <3>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8350_torch0: qcom,torch_0 {
label = "torch";
qcom,led-name = "led:torch_0";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch0_trigger";
qcom,id = <0>;
qcom,ires-ua = <12500>;
qcom,strobe-sel = <1>;
qcom,strobe-config = <0>;
};
pm8350_torch1: qcom,torch_1 {
label = "torch";
qcom,led-name = "led:torch_1";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch1_trigger";
qcom,id = <1>;
qcom,ires-ua = <12500>;
};
pm8350_torch2: qcom,torch_2 {
label = "torch";
qcom,led-name = "led:torch_2";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch2_trigger";
qcom,id = <2>;
qcom,ires-ua = <12500>;
};
pm8350_torch3: qcom,torch_3 {
label = "torch";
qcom,led-name = "led:torch_3";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch3_trigger";
qcom,id = <3>;
qcom,ires-ua = <12500>;
};
pm8350_switch0: qcom,led_switch_0 {
label = "switch";
qcom,led-name = "led:switch_0";
qcom,led-mask = <9>; /* Channels 1 & 4 */
qcom,default-led-trigger = "switch0_trigger";
qcom,symmetry-en;
};
pm8350_switch1: qcom,led_switch_1 {
label = "switch";
qcom,led-name = "led:switch_1";
qcom,led-mask = <6>; /* Channels 2 & 3 */
qcom,default-led-trigger = "switch1_trigger";
qcom,symmetry-en;
};
};
...

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Qualcomm Technologies, Inc. TRI_LED driver specific bindings
This binding document describes the properties of TRI_LED module in
Qualcomm Technologies, Inc. PMIC chips.
- compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,tri-led".
- reg:
Usage: required
Value type: <u32>
Definition: Register base of the TRI_LED module.
- nvmem-names:
Usage: optional
Value type: <string>
Definition: Nvmem device name for SDAM to do PBS trigger. It must be
defined as "pbs_sdam". This is required only for HR_LEDs.
- nvmem:
Usage: optional
Value type: <phandle>
Definition: Phandle of the nvmem device name to access SDAM to do PBS
trigger. This is required only for HR_LEDs.
Properties for child nodes:
- pwms:
Usage: required
Value type: <prop-encoded-array>
Definition: The PWM device (phandle) used for controlling LED.
- led-sources:
Usage: required
Value type: <prop-encoded-array>
Definition: see Documentation/devicetree/bindings/leds/common.txt;
Device current output identifiers are: 0 - LED1_EN,
1 - LED2_EN, 2 - LED3_EN.
- label:
Usage: optional
Value type: <string>
Definition: see Documentation/devicetree/bindings/leds/common.txt;
- linux,default-trigger:
Usage: optional
Value_type: <string>
Definition: see Documentation/devicetree/bindings/leds/common.txt;
Example:
pmi8998_rgb: tri-led@d000{
compatible = "qcom,tri-led";
reg = <0xd000>;
red {
label = "red";
pwms = <&pmi8998_lpg 4 1000000>;
led-sources = <0>;
};
green {
label = "green";
pwms = <&pmi8998_lpg 3 1000000>;
led-sources = <1>;
};
blue {
label = "blue";
pwms = <&pmi8998_lpg 2 1000000>;
led-sources = <2>;
};
};

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* Qualcomm Technologies, Inc. MSM CVP
[Root level node]
cvp
=====
Required properties:
- compatible : one of:
- "qcom,msm-cvp"
- "qcom,shima-cvp" : Invokes driver specific data for shima.
- "qcom,lahaina-cvp" : Invokes driver specific data for Lahaina.
- "qcom,kona-cvp" : Invokes driver specific data for kona.
Optional properties:
- reg : offset and length of the CSR register set for the device.
- interrupts : should contain the cvp interrupt.
- qcom,reg-presets : list of offset-value pairs for registers to be written.
The offsets are from the base offset specified in 'reg'. This is mainly
used for QoS, VBIF, etc. presets for video.
- qcom,qdss-presets : list of physical address and memory allocation size pairs.
when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware messages will be
written to QDSS memory.
- *-supply: A phandle pointing to the appropriate regulator. Number of
regulators vary across targets.
- clock-names: an array of clocks that the driver is supposed to be
manipulating. The clocks names here correspond to the clock names used in
clk_get(<name>).
- qcom,clock-configs = an array of bitmaps of clocks' configurations. The index
of the bitmap corresponds to the clock at the same index in qcom,clock-names.
The bitmaps describes the actions that the device needs to take regarding the
clock (i.e. scale it based on load).
The bitmap is defined as:
scalable = 0x1 (if the driver should vary the clock's frequency based on load)
- qcom,allowed-clock-rates = an array of supported clock rates by the chipset.
- qcom,use-non-secure-pil = A bool indicating which type of pil to use to load
the fw.
- qcom,fw-bias = The address at which cvp fw is loaded (manually).
[Second level nodes]
Context Banks
=============
Required properties:
- compatible : one of:
- "qcom,msm-cvp,context-bank"
- iommus : A phandle parsed by smmu driver. Number of entries will vary
across targets.
Optional properties:
- label - string describing iommu domain usage.
- buffer-types : bitmap of buffer types that can be mapped into the current
IOMMU domain.
- Buffer types are defined as the following:
input = 0x1
output = 0x2
output2 = 0x4
extradata input = 0x8
extradata output = 0x10
extradata output2 = 0x20
internal scratch = 0x40
internal scratch1 = 0x80
internal scratch2 = 0x100
internal persist = 0x200
internal persist1 = 0x400
internal cmd queue = 0x800
- virtual-addr-pool : offset and length of virtual address pool.
- qcom,fw-context-bank : bool indicating firmware context bank.
- qcom,secure-context-bank : bool indicating secure context bank.
Buses
=====
Required properties:
- compatible : one of:
- "qcom,msm-cvp,bus"
- label : an arbitrary name
- qcom,bus-master : an integer descriptor of the bus master. Refer to arch/arm/\
boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable masters
- qcom,bus-slave : an integer descriptor of the bus slave. Refer to arch/arm/\
boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable slaves
Optional properties:
- qcom,bus-governor : governor to use when scaling bus, generally any commonly
found devfreq governor might be used. In addition to those governors, the
custom Venus governors, "msm-vidc-ddr" or "msm-vidc-llcc" are also
acceptable values.
In the absence of this property the "performance" governor is used.
- qcom,bus-rage-kbps : an array of two items (<min max>) that indicate the
minimum and maximum acceptable votes for the bus.
In the absence of this property <0 INT_MAX> is used.
- qcom,ubwc-10bit : UBWC 10 bit content has different bus requirements,
this tag will be used to pick the appropriate bus as per the session profile
as shown below in example.
Memory Heaps
============
Required properties:
- compatible : one of:
- "qcom,msm-vidc,mem-cdsp"
- memory-region : phandle to the memory heap/region.
Example:
msm_cvp: qcom,cvp@ab00000 {
compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
status = "ok";
reg = <0xab00000 0x100000>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
/* FIXME: LLCC Info */
/* cache-slice-names = "vidsc0", "vidsc1"; */
/* cache-slices = <&llcc 2>, <&llcc 3>; */
/* Supply */
cvp-supply = <&mvs1_gdsc>;
/* Clocks */
clock-names = "gcc_video_axi0",
"gcc_video_axi1", "cvp_clk";
clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
<&clock_gcc GCC_VIDEO_AXI1_CLK>,
<&clock_videocc VIDEO_CC_MVS1_CLK>;
qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
"cvp_clk";
qcom,clock-configs = <0x0 0x0 0x1>;
qcom,allowed-clock-rates = <403000000 520000000
549000000 666000000 800000000>;
/* Buses */
bus_cnoc {
compatible = "qcom,msm-cvp,bus";
label = "cnoc";
qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
qcom,bus-governor = "performance";
qcom,bus-range-kbps = <1000 1000>;
};
/* MMUs */
non_secure_cb {
compatible = "qcom,msm-cvp,context-bank";
label = "cvp_hlos";
iommus =
<&apps_smmu 0x2120 0x400>;
qcom,iommu-dma = "disabled";
buffer-types = <0xfff>;
virtual-addr-pool = <0x4b000000 0xe0000000>;
};
/* Memory Heaps */
qcom,msm-cvp,mem_cdsp {
compatible = "qcom,msm-cvp,mem-cdsp";
memory-region = <&cdsp_mem>;
};
};

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* Qualcomm Technologies, Inc. MSM CVP
[Root level node]
cvp
=====
Required properties:
- compatible : one of:
- "qcom,msm-cvp"
- "qcom,waipio-cvp" : Invokes driver specific data for waipio
- "qcom,lahaina-cvp" : Invokes driver specific data for Lahaina.
- "qcom,kona-cvp" : Invokes driver specific data for kona.
Optional properties:
- reg : offset and length of the CSR register set for the device.
- interrupts : should contain the cvp interrupt.
- qcom,reg-presets : list of offset-value pairs for registers to be written.
The offsets are from the base offset specified in 'reg'. This is mainly
used for QoS, VBIF, etc. presets for video.
- qcom,qdss-presets : list of physical address and memory allocation size pairs.
when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware messages will be
written to QDSS memory.
- *-supply: A phandle pointing to the appropriate regulator. Number of
regulators vary across targets.
- clock-names: an array of clocks that the driver is supposed to be
manipulating. The clocks names here correspond to the clock names used in
clk_get(<name>).
- qcom,clock-configs = an array of bitmaps of clocks' configurations. The index
of the bitmap corresponds to the clock at the same index in qcom,clock-names.
The bitmaps describes the actions that the device needs to take regarding the
clock (i.e. scale it based on load).
The bitmap is defined as:
scalable = 0x1 (if the driver should vary the clock's frequency based on load)
- qcom,allowed-clock-rates = an array of supported clock rates by the chipset.
- qcom,use-non-secure-pil = A bool indicating which type of pil to use to load
the fw.
- qcom,fw-bias = The address at which cvp fw is loaded (manually).
[Second level nodes]
Context Banks
=============
Required properties:
- compatible : one of:
- "qcom,msm-cvp,context-bank"
- iommus : A phandle parsed by smmu driver. Number of entries will vary
across targets.
Optional properties:
- label - string describing iommu domain usage.
- buffer-types : bitmap of buffer types that can be mapped into the current
IOMMU domain.
- Buffer types are defined as the following:
input = 0x1
output = 0x2
output2 = 0x4
extradata input = 0x8
extradata output = 0x10
extradata output2 = 0x20
internal scratch = 0x40
internal scratch1 = 0x80
internal scratch2 = 0x100
internal persist = 0x200
internal persist1 = 0x400
internal cmd queue = 0x800
- virtual-addr-pool : offset and length of virtual address pool.
- qcom,fw-context-bank : bool indicating firmware context bank.
- qcom,secure-context-bank : bool indicating secure context bank.
Buses
=====
Required properties:
- compatible : one of:
- "qcom,msm-cvp,bus"
- label : an arbitrary name
- qcom,bus-master : an integer descriptor of the bus master. Refer to arch/arm/\
boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable masters
- qcom,bus-slave : an integer descriptor of the bus slave. Refer to arch/arm/\
boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable slaves
Optional properties:
- qcom,bus-governor : governor to use when scaling bus, generally any commonly
found devfreq governor might be used. In addition to those governors, the
custom Venus governors, "msm-vidc-ddr" or "msm-vidc-llcc" are also
acceptable values.
In the absence of this property the "performance" governor is used.
- qcom,bus-rage-kbps : an array of two items (<min max>) that indicate the
minimum and maximum acceptable votes for the bus.
In the absence of this property <0 INT_MAX> is used.
- qcom,ubwc-10bit : UBWC 10 bit content has different bus requirements,
this tag will be used to pick the appropriate bus as per the session profile
as shown below in example.
Memory Heaps
============
Required properties:
- compatible : one of:
- "qcom,msm-vidc,mem-cdsp"
- memory-region : phandle to the memory heap/region.
Example:
msm_cvp: qcom,cvp@ab00000 {
compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
status = "ok";
reg = <0xab00000 0x100000>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
/* FIXME: LLCC Info */
/* cache-slice-names = "vidsc0", "vidsc1"; */
/* cache-slices = <&llcc 2>, <&llcc 3>; */
/* Supply */
cvp-supply = <&mvs1_gdsc>;
/* Clocks */
clock-names = "gcc_video_axi0",
"gcc_video_axi1", "cvp_clk";
clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
<&clock_gcc GCC_VIDEO_AXI1_CLK>,
<&clock_videocc VIDEO_CC_MVS1_CLK>;
qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
"cvp_clk";
qcom,clock-configs = <0x0 0x0 0x1>;
qcom,allowed-clock-rates = <403000000 520000000
549000000 666000000 800000000>;
/* Buses */
bus_cnoc {
compatible = "qcom,msm-cvp,bus";
label = "cnoc";
qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
qcom,bus-governor = "performance";
qcom,bus-range-kbps = <1000 1000>;
};
/* MMUs */
non_secure_cb {
compatible = "qcom,msm-cvp,context-bank";
label = "cvp_hlos";
iommus =
<&apps_smmu 0x2120 0x400>;
qcom,iommu-dma = "disabled";
buffer-types = <0xfff>;
virtual-addr-pool = <0x4b000000 0xe0000000>;
};
/* Memory Heaps */
qcom,msm-cvp,mem_cdsp {
compatible = "qcom,msm-cvp,mem-cdsp";
memory-region = <&cdsp_mem>;
};
};

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Qualcomm Technologies, Inc. I2C PMIC Interrupt Controller
Platform Independent Bindings
The I2C PMIC Controller is used by multi-function PMIC devices which communicate
over the I2C bus. An I2C PMIC controller node typically contains one or more
child nodes representing the device's peripherals. Each of the peripherals
typically has its own driver on the platform bus and will be enumerated by this
controller. The controller exposes a regmap to the peripherals to communicate
over the I2C bus.
The controller also controls interrupts for all of the peripherals on the bus.
The controller takes a summary interrupt, deciphers which peripheral triggered
the interrupt, and which of the peripheral's interrupts were triggered. Finally,
it calls the handlers for each of the virtual interrupts that were registered.
This document describes the common platform independent bindings that apply
to all I2C PMIC interrupt controllers.
========================================
First Level Nodes - I2C PMIC Controllers
========================================
Platform independent properties:
- compatible
Usage: required
Value type: <string>
Definition: Must be "qcom,i2c-pmic".
- reg
Usage: required
Value type: <u32>
Definition: 7-bit I2C address of the device.
- interrupt-parent
Usage: optional
Value type: <phandle>
Definition: phandle of the interrupt controller which services the
summary interrupt.
- interrupts
Usage: optional
Value type: <prop-encoded-array>
Definition: Summary interrupt specifier.
- interrupt-controller
Usage: optional
Value type: <empty>
Definition: Boolean flag which indicates this device node is an
interrupt controller.
- #interrupt-cells
Usage: optional
Value type: <u32>
Definition: Number of cells to encode an interrupt source.
- qcom,periph-map
Usage: optional
Value type: <prop-encoded-array>
Definition: A list of u32 arrays. This provides a mapping between the
summary status register bits and peripheral addresses.
The number of arrays should match the number of summary
registers with up to 8 elements each. One element per bit
of the summary status register in order from the least
sigificant bit to the most significant bit.
- pinctrl-names
Usage: optional
Value type: <string-list>
Definition: Should be "default".
Please refer to pinctrl-bindings.txt
- pinctrl-0
Usage: optional
Value type: <phandle-list>
Definition: phandle of the pin configuration.
Please refer to pinctrl-bindings.txt
=======
Example
=======
&i2c_3 {
status = "ok";
qcom,smb138x@8 {
compatible = "qcom,i2c-pmic";
reg = <0x8>;
interrupt-parent = <&tlmm_pinmux>;
interrupts = <83 0>;
interrupt-controller;
#interrupt-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&smb_stat_active>;
#address-cells = <1>;
#size-cells = <0>;
qcom,periph-map = <0x10 0x11 0x12 0x13 0x14 0x16 0x36>;
};
};

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Qualcomm PM8xxx PMIC multi-function devices
The PM8xxx family of Power Management ICs are used to provide regulated
voltages and other various functionality to Qualcomm SoCs.
= PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,pm8058"
"qcom,pm8821"
"qcom,pm8921"
- #address-cells:
Usage: required
Value type: <u32>
Definition: must be 1
- #size-cells:
Usage: required
Value type: <u32>
Definition: must be 0
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: specifies the interrupt that indicates a subdevice
has generated an interrupt (summary interrupt). The
format of the specifier is defined by the binding document
describing the node's interrupt parent.
- #interrupt-cells:
Usage: required
Value type : <u32>
Definition: must be 2. Specifies the number of cells needed to encode
an interrupt source. The 1st cell contains the interrupt
number. The 2nd cell is the trigger type and level flags
encoded as follows:
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
- interrupt-controller:
Usage: required
Value type: <empty>
Definition: identifies this node as an interrupt controller
= SUBCOMPONENTS
The PMIC contains multiple independent functions, each described in a subnode.
The below bindings specify the set of valid subnodes.
== Real-Time Clock
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,pm8058-rtc"
"qcom,pm8921-rtc"
"qcom,pm8941-rtc"
"qcom,pm8018-rtc"
"qcom,pmk8350-rtc"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: single entry specifying the base address of the RTC registers
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: single entry specifying the RTC's alarm interrupt
- allow-set-time:
Usage: optional
Value type: <empty>
Definition: indicates that the setting of RTC time is allowed by
the host CPU
= EXAMPLE
pmicintc: pmic@0 {
compatible = "qcom,pm8921";
interrupts = <104 8>;
#interrupt-cells = <2>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
rtc@11d {
compatible = "qcom,pm8921-rtc";
reg = <0x11d>;
interrupts = <0x27 0>;
};
};

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%YAML 1.2
---
$id: "http://devicetree.org/schemas/neuron.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: QRTR Gunyah Transport Configuration
maintainers:
- Chris Lew <clew@quicinc.com>
description: |
Configuration properties for the qrtr Gunyah Transport. This configuration is
to instantiate a transport for IPC Router protocol communication between
virtual machines on top of the Gunyah hypervisor.
properties:
compatible:
const: qcom,qrtr-gunyah
qcom,master:
description: Specify if this device is on the primary virtual machine.
gunyah-label:
$ref: '/schemas/types.yaml#/definitions/u32'
maxItems: 1
description: The label qrtr should request interrupts with from the gunyah
doorbell driver.
shared-buffer:
$ref: '/schemas/types.yaml#/definitions/phandle'
maxItems: 1
description: phandle reference to a reserved memory region for sharing
between vms
required:
-compatible
-gunyah-label
-shared-buffer
examples:
- |
qrtr_shbuf: qrtr-shmem {
no-map;
reg = <0x0 0xd7ef7000 0x0 0x9000>;
};
qrtr-gunyah {
compatible = "qcom,qrtr-gunyah";
qcom,master;
gunyah-label = <0>;
shared-buffer = <&qrtr_shbuf>;
};

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QTI QRTR MHI transport binding
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,qrtr-mhi"
- qcom,dev-id:
Usage: optional
Value type: <u32>
Definition: indicates the dev-id that this transport is for. Should be
passed into the qrtr core logic to determine to match with the
dev-id used by the mhi controller.
- qcom,net-id:
Usage: optional
Value type: <u32>
Definition: indicates what subnet this transport belongs to. If the dev-id
passed above matches the one passed into qrtr logic by mhi core,
then this net-id is passed into the qrtr core logic to determin
if forwarding is needed on this endpoint.
- qcom,low-latency:
Usage: optional
Value type: <bool>
Definition: indicates whether this transport receiving thread needs to
be set to realtime priority for enhanced performance.
= EXAMPLE
The following example represents the qrtr mhi transport node on a device
configured as a pcie endpoint and needs to forward data from the host to a
slpi co-processor.
mhi_qrtr_cnss {
compatible = "qcom,qrtr-mhi";
qcom,dev-id = <0x1103>;
qcom,net-id = <0>;
qcom,low-latency;
};

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Qualcomm Technologies, Inc SNxxx NFC NCI device
Near Field Communication (NFC) device is based on NFC Controller Interface (NCI)
Required properties:
- compatible: "qcom,sn-nci"
- reg: NCI I2C slave address.
- qcom,sn-ven: specific gpio for hardware reset.
- qcom,sn-irq: specific gpio for read interrupt.
- qcom,sn-firm: gpio for firmware download
- qcom,sn-clkreq: gpio for clock
- interrupt-parent: Should be phandle for the interrupt controller
that services interrupts for this device.
- interrupts: Nfc read interrupt,gpio-clk-req interrupt
Recommended properties:
- interrupt-names: names of interrupts, should include "nfc_irq", used for reference
Optional properties:
- pinctrl-names, pinctrl-0, pincntrl-1: references to our pincntrl settings
- clocks, clock-names: must contain the SNxxx's core clock.
- qcom,clk-src: NFC clock for antenna
Example:
sn-nci@2b {
compatible = "qcom,sn-nci";
reg = <0x2b>;
qcom,sn-irq = <&tlmm 87 0x00>;
qcom,sn-ven = <&tlmm 62 0x00>;
qcom,sn-firm = <&tlmm 86 0x00>;
qcom,sn-clkreq = <&tlmm 63 0x00>;
qcom,clk-src = "BBCLK2";
interrupt-parent = <&tlmm>;
interrupts = <29 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "default","sleep";
pinctrl-0 = <&nfc_enable_active &nfc_fwdl_active
&nfc_clk_req_active &nfc_int_active>;
pinctrl-1 = <&nfc_enable_suspend &nfc_fwdl_suspend
&nfc_clk_req_suspend &nfc_int_suspend>;
clocks = <&clock_rpm clk_bb_clk2_pin>;
clock-names = "ref_clk";
status = "ok";
};

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* MSM PCIe MSI controller
=========
Main node
=========
- compatible:
Usage: required
Value type: <stringlist>
Definition: Value to identify this is a MSM PCIe MSI controller
- msi-controller:
Usage: required
Value type: <bool>
Definition: Indicates that this is a MSM PCIe MSI controller node
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Physical QGIC address (0x17a00040), MSI message address
- interrupt-parent:
Usage: required
Value type: <phandle>
Definition: Phandle of the interrupt controller that services
interrupts for this device
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: Array of tuples which describe interrupt lines for PCIe MSI
-qcom,snps:
Usage: optional
Value type: <bool>
Definition: Set if interrupt controller is Synopsys instead of QGIC
=======
Example
=======
pcie0_msi: qcom,pcie0_msi {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0x17a10040 0x0 0x0 0x0 0xff>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 832 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 833 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 834 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 835 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 836 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 837 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 838 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 839 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 840 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 841 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 842 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 843 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 844 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 845 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 846 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 847 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 848 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 849 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 850 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 857 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 858 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 859 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 862 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 863 IRQ_TYPE_EDGE_RISING>;
};

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* MSM PCI express root complex
=========
Main node
=========
- compatible:
Usage: required
Value type: <stringlist>
Definition: Should be "qcom,pci-msm"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Register ranges as listed in the reg-names property
- reg-names:
Usage: required
Value type: <stringlist>
Definition: Should contain:
- "parf" MSM specific registers
- "phy" PCIe PHY registers
- "dbi" DesignWare PCIe registers
- "elbi" External local bus interface registers
- "iatu" Internal translation unit registers
- "config" PCIe device configuration space
- "io" PCIe device I/O registers
- "bars" PCIe device base address registers
- "tcsr" (opt) PCIe clock scheme register
- "rumi" (opt) PCIe RUMI register
- cell-index:
Usage: required
Value type: <u32>
Definition: defines root complex ID.
- linux,pci-domain:
Usage: required
Value type: <u32>
Definition: As specified in pci.txt
- #address-cells:
Usage: required
Value type: <u32>
Definition: Should be 3. As specified in designware-pcie.txt
- #size-cells:
Usage: required
Value type: <u32>
Definition: Should be 2. As specified in designware-pcie.txt
- ranges:
Usage: required
Value type: <prop-encoded-array>
Definition: As specified in designware-pcie.txt
- interrupt-parent:
Usage: required
Value type: <phandle>
Definition: Phandle of the interrupt controller that services
interrupts for this device
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: PCIe root complex related interrupts
- interrupt-names:
Usage: required
Value type: <stringlist>
Definition: Should contain
- "int_global_int"
- "int_a"
- "int_b"
- "int_c"
- "int_d",
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: Should be 1. As specified in designware-pcie.txt
- interrupt-map-mask:
Usage: required
Value type: <prop-encoded-array>
Definition: As specified in designware-pcie.txt
- interrupt-map:
Usage: required
Value type: <prop-encoded-array>
Definition: As specified in designware-pcie.txt
- msi-parent:
Usage: required
Value type: <phandle>
Definition: As specified in pci-msi.txt
- <name>-gpio:
Usage: required
Value type: <prop-encoded-array>
Definition: List of phandle and GPIO specifier pairs. Should contain:
- "perst-gpio" PCIe reset signal line
- "wake-gpio" PCIe wake signal line
- "qcom,ep-gpio" (opt) PCIe endpoint specific signal line
- pinctrl-names:
Usage: required
Value type: <stringlist>
Definition: Name of pin configuration groups. Should contain:
- "default"
- "sleep" (opt)
- pinctrl-<num>:
Usage: required
Value type: <prop-encoded-array>
Definition: As specified in pinctrl-bindings.txt
- <supply-name>-supply:
Usage: required
Value type: <phandle>
Definition: Phandle to PCIe core and PHY power supply. Should contain:
- "gdsc-vdd-supply" PCIe power domain control
- "vreg-1.8-supply" power supply for PCIe PHY
- "vreg-0.9-supply" power supply for PCIe PHY
- "vreg-cx-supply" power supply for PCIe core
- "vreg-3.3-supply" (opt) power supply for PCIe endpoint
- qcom,<supply-name>-voltage-level:
Usage: required
Value type: <prop-encoded-array>
Definition: List of max/min voltage(uV) and optimal current(uA) tuple
for power supply
- qcom,bw-scale:
Usage: optional
Value type: <prop-encoded-array>
Definition: List of CX voltage corner and rate change clock frequency
pair for each PCIe GEN speed
interconnect-names:
Usage: optional
Value type: <stringlist>
Definition: As specified in interconnect.txt
interconnects:
Usage: required
Value type: <prop-encoded-array>
Definition: As specified in interconnect.txt
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: List of phandle and clock specifier pairs as listed
in clock-names property
- clock-names:
Usage: required
Value type: <stringlist>
Definition: List of clock names that corresponds with listed "clocks"
- max-clock-frequency-hz:
Usage: optional
Value type: <u32 array>
Definition: List of clock frequencies for each PCIe clock. Only need to
specify the ones that needs to be changed
- resets:
Usage: required
Value type: <prop-encoded-array>
Definition: List of phandle and reset specifier pairs as listed
in reset-names property
- reset-names:
Usage: required
Value type: <stringlist>
Definition: Should contain:
- "pcie_<num>_core_reset" Core reset
- "pcie_<num>_phy_reset" PHY reset
- qcom,smmu-sid-base:
Usage: optional
Value: <u32>
Definition: Base SID for PCIe
- iommu-map:
Usage: optional. Required if qcom,smmu-sid-base is defined
Value type: <prop-encoded-array>
Definition: As defined in pci-iommu.txt. Should contain:
- <BDF, iommu phandle, SID, 0x1>
- qcom,target-link-speed:
Usage: optional
Value type: <u32>
Definition: Override maximum GEN speed. Options:
- 0x1 GEN 1
- 0x2 GEN 2
- 0x3 GEN 3
- qcom,link-check-max-count
Usage: optional
Value type: <u32>
Definition: Max number of retries for link training. Delay between each
check is 5ms
- qcom,boot-option:
Usage: optional
Value type: <u32>
Definition: Controls PCIe bus driver boot sequence. Options:
- BIT(0) PCIe bus driver will not start enumeration
during its probe. Clients will control when
PCIe bus driver should do enumeration
- BIT(1) PCIe bus driver will not start enumeration if it
receives a WAKE interrupt
- qcom,drv-supported:
Usage: optional
Value type: <bool>
Definition: Direct resource vote (DRV) is supported. APPS PCIe
root complex driver can hand off PCIe resources to another
subsystem. This will allow APPS to enter lower power modes
while keeping PCIe core, PHY, and link funtional. In addition,
the system can enter CX power collapse once the DRV subsystem
removes its PCIe votes.
- qcom,drv-l1ss-timeout-us:
Usage: optional depends on qcom,drv-supported
Value type: <u32>
Definition: This timeout determines when DRV subsystem will put the
link into l1ss sleep while idle in l1ss. If this is omitted,
the default timeout is 100ms.
- qcom,use-19p2mhz-aux-clk:
Usage: optional
Value type: <bool>
Definition: Set PCIe AUX clock frequency to 19.2MHz
- qcom,common-clk-en:
Usage: optional
Value type: <bool>
Definition: Support common clock configuration
- qcom,clk-power-manage-en:
Usage: optional
Value type: <bool>
Definition: Support clock power management
- qcom,n-fts:
Usage: optional
Value type: <u32>
Definition: Number of fast training sequences sent when the link
transitions from L0s to L0
- qcom,no-l0s-supported:
Usage: optional
Value type: <bool>
Definition: L0s is not supported
- qcom,no-l1-supported:
Usage: optional
Value type: <bool>
Definition: L1 is not supported
- qcom,no-l1ss-supported:
Usage: optional
Value type: <bool>
Definition: L1 sub-state (L1ss) is not supported
- qcom,no-aux-clk-sync:
Usage: optional
Value type: <bool>
Definition: The AUX clock is not synchronous to the Core clock to
support L1ss
- qcom,l1-2-th-scale:
Usage: optional
Value type: <u32>
Definition: Determines the multiplier for L1.2 LTR threshold value
- 0 1ns
- 1 32ns
- 2 1us
- 3 32us
- 4 1ms
- 5 32ms
- qcom,l1-2-th-value:
Usage: optional
Value type: <u32>
Definition: L1.2 LTR threshold value to be multipled with scale to
define L1.2 latency tolerance reporting (LTR)
- qcom,slv-addr-space-size:
Usage: required
Value type: <u32>
Definition: Memory block size dedicated to PCIe root complex
- qcom,wr-halt-size:
Usage: optional
Value type: <u32>
Definition: Exponent (base 2) that determines the data size(bytes) that
PCIe core will halt for each write
- qcom,tlp-rd-size:
Usage: optional
Value type: <u32>
Definition: Determines the maximum read request size(bytes). Options:
- 0 128
- 1 256
- 2 512
- 3 1K
- 4 2K
- 5 4K
- qcom,cpl-timeout:
Usage: optional
Value type: <u32>
Definition: Determines the timeout range PCIe root complex will send
out a completion packet if no ACK is seen for TLP. Options:
- BIT(0) 50us to 10ms
- BIT(1) 10ms to 250ms
- BIT(2) 250ms to 4s
- BIT(3) 4s to 64s
- qcom,perst-delay-us-min:
Usage: optional
Value type: <u32>
Definition: Minimum allowed time(us) to sleep after asserting or
de-asserting PERST GPI.
- qcom,perst-delay-us-max:
Usage: optional
Value type: <u32>
Definition: Maximum allowed time(us) to sleep after asserting or
de-asserting PERST GPIO
- qcom,ep-latency:
Usage: optional
Value type: <u32>
Definition: The latency(ms) between when PCIe PHY is up and PERST is
de-asserted. This guarantees the 100MHz clock is available for
the PCIe devices
- qcom,switch-latency:
Usage: optional
Definition: The latency(ms) between when PCIe link is up and before
any device over the switch is accessed
- qcom,core-preset:
Usage: optional
Definition: Determines how aggressive the PCIe PHY equalization is for
Gen3 cores. The following are recommended settings:
- short channels: 0x55555555 (default)
- long channels: 0x77777777
- qcom,pcie-phy-ver:
Usage: required
Value type: <u32>
Definition: States the PCIe PHY version
- qcom,phy-status-offset:
Usage: required
Value type: <u32>
Definition: Offset from PCIe PHY base to check if PCIe PHY status
- qcom,phy-status-bit:
Usage: required
Value type: <u32>
Definition: BIT to check PCIe PHY status
- qcom,phy-power-down-offset:
Usage: required
Value type: <u32>
Definition: Offset from PCIe PHY base to control PHY power state
- qcom,phy-sequence:
Usage: required
Value type: <prop-encoded array>
Definition: PCIe PHY initialization sequence
==============
Root port node
==============
Root port are defined as subnodes of the PCIe controller node
- reg:
Usage: required
Value type: <prop-encoded array>
Definition: First cell is devfn, which is determined by pci bus
topology. Assign the other cells 0 since they are not used
- qcom,iommu-cfg:
Usage: optional
Value type: <u32>
Definition: Defines PCIe root port SMMU configuration. Options:
- BIT(0) Indicates if SMMU is present
- BIT(1) Set IOMMU attribute S1_BYPASS
- BIT(2) Set IOMMU attribute FAST
- BIT(3) Set IOMMU attribute ATOMIC
- BIT(4) Set IOMMU attribute FORCE COHERENT
- qcom,iommu-range:
Usage: optional
Value type: Array of <u64>
Definition: Pair of values describing iova base and size to allocate
=======
Example
=======
pcie0: qcom,pcie@1c00000 {
compatible = "qcom,pci-msm";
reg = <0x1c00000 0x4000>,
<0x1c04000 0x1000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>,
<0x60200000 0x100000>,
<0x60300000 0x3d00000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
"io", "bars", "tcsr", "rumi";
cell-index = <0>;
device_type = "pci";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
interrupt-parent = <&pcie0>;
interrupts = <0 1 2 3 4 5>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d",
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc 0 140 0
0 0 0 1 &intc 0 149 0
0 0 0 2 &intc 0 150 0
0 0 0 3 &intc 0 151 0
0 0 0 4 &intc 0 152 0>;
msi-parent = <&pcie0_msi>;
perst-gpio = <&tlmm 35 0>;
wake-gpio = <&tlmm 37 0>;
qcom,ep-gpio = <&tlmm 94 0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_clkreq_default
&pcie0_perst_default
&pcie0_wake_default>;
pinctrl-1 = <&pcie0_clkreq_sleep
&pcie0_perst_sleep
&pcie0_wake_sleep>;
gdsc-vdd-supply = <&pcie_0_gdsc>;
vreg-1.8-supply = <&pm8150l_l3>;
vreg-0.9-supply = <&pm8150_l5>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
vreg-3.3-supply = <&pm8150_l1>;
qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
qcom,vreg-0.9-voltage-level = <950000 950000 24000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
interconnect-names = "icc_path";
interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_PCIE_0_AUX_CLK>,
<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&clock_gcc GCC_PCIE_0_CLKREF_CLK>,
<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>,
<&clock_gcc GCC_PCIE_PHY_AUX_CLK>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
"pcie_tbu_clk", "pcie_phy_refgen_clk",
"pcie_phy_aux_clk";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>;
resets = <&clock_gcc GCC_PCIE_0_BCR>,
<&clock_gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset";
qcom,smmu-sid-base = <0x1e00>;
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
<0x100 &apps_smmu 0x1e01 0x1>;
qcom,target-link-speed = <0x2>;
qcom,link-check-max-count = <40> /* 200ms */
qcom,boot-option = <0x1>;
qcom,drv-supported;
qcom,use-19p2mhz-aux-clk;
qcom,common-clk-en;
qcom,clk-power-manage-en;
qcom,n-fts = <0x50>;
qcom,no-l0s-supported;
qcom,no-l1-supported;
qcom,no-l1ss-supported;
qcom,no-aux-clk-sync;
qcom,slv-addr-space-size = <0x1000000>; /* 16MB */
qcom,wr-halt-size = <0xa>; /* 1KB */
qcom,tlp-rd-size = <0x5>; /* 4KB */
qcom,cpl-timeout = <0x2>; /* 10ms to 250ms */
qcom,perst-delay-us-min = <10>;
qcom,perst-delay-us-max = <15>;
qcom,ep-latency = <20>;
qcom,switch-latency = <25>;
qcom,core-preset = <0x55555555> /* short channel */
qcom,pcie-phy-ver = <0x2101>; /* v2 version 1.01 */
qcom,phy-status-offset = <0x814>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x840>;
qcom,phy-sequence = <0x0840 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
0x016c 0x08 0x0
0x0058 0x0f 0x0
0x00a4 0x42 0x0
0x0110 0x24 0x0
0x0800 0x00 0x0
0x0844 0x03 0x0>;
pcie0_rp: pcie0_rp {
reg = <0x0 0x0 0x0 0x0 0x0>;
qcom,iommu-cfg = <0x3> /* SMMU PRESENT. SET S1 BYPASS */
qcom,iommu-range = <0x0 0x10000000 0x0 0x40000000>;
};

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* QCOM LLCC PMU Bindings
This represents the miss counters located in the LLCC hardware counters.
Only one event is supported:
0x1000 - LLCC misses
The follow section describes the LLCC PMU DT node binding.
Required properties:
- compatible : Shall be "qcom,llcc-pmu-ver1" or "qcom,llcc-pmu-ver2"
- reg : There shall be one resource, a pair of the form
< base_address total_size > representing the DDR_LAGG
region.
- reg-names : Shall be "lagg-base".
Example:
llcc_pmu: llcc-pmu {
compatible = "qcom,qcom-llcc-pmu";
reg = < 0x090CC000 0x300 >;
reg-names = "lagg-base";
};

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bindings/pil/subsys-pil-tz.yaml Normal file
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%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/pil/subsys-pil-tz.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic Subsystem Peripheral Image Loader
maintainers:
- Raghavendra Rao Ananta <rananta@quicinc.com>
description: |+
subsys-pil-tz is a generic peripheral image loader (PIL) driver. It is
used for loading the firmware images of the subsystems into memory and
preparing the subsystem's processor to execute code. It's also responsible
for shutting down the processor when it's not needed.
properties:
compatible:
oneOf:
- const: qcom,pil-tz-generic
description:
For implementations specific to subsystem PIL nodes. Could be more
than one.
- const: qcom,pil-tz-scm-pas
description:
For specifically registering with the interconnect framework, in
order to satisfy the bandwidth requirements between the DDR and
the crypto engine. This is so that the secure world can validate
the PIL images. Only one node per device-tree is required.
qcom,firmware-name:
description: Base name of the firmware image.
reg:
description:
Pairs of physical base addresses and region sizes of memory mapped
registers.
reg-names:
description:
Names of the bases for the above registers. Not required for PIL usage.
For example, "wrapper_base", "vbif_base".
interrupts:
description: Subsystem to Apps watchdog bite interrupt.
vdd_'reg'-supply:
description:
Reference to the regulator that supplies the corresponding 'reg' domain.
qcom,proxy-reg-names:
description:
Names of the regulators that need to be turned on/off during proxy
voting/unvoting.
qcom,active-reg-names:
description:
Names of the regulators that need to be turned on for the subsystem to
run. Turned off when the subsystem is shutdown.
qcom,vdd_'reg'-uV-uA:
description: Voltage and current values for the 'reg' regulator.
qcom,proxy-clock-names:
description:
Names of the clocks that need to be turned on/off during proxy
voting/unvoting.
qcom,active-clock-names:
description:
Names of the clocks that need to be turned on for the subsystem to run.
Turned off when the subsystem is shutdown.
clock-names:
description: Names of all the clocks that are accessed by the subsystem.
qcom,<clock-name>-freq:
description:
Frequency to be set for that clock in Hz. If the property isn't added
for a clock, then the default clock frequency would be set to 19200000 Hz.
qcom,pas-id:
description: pas_id of the subsystem.
qcom,proxy-timeout-ms:
description: Proxy vote timeout value for the subsystem.
qcom,smem-id:
description: ID of the SMEM item for the subsystem.
qcom,is-not-loadable:
description:
Present if the subsystem's firmware image does not need be loaded.
type: boolean
qcom,pil-no-auth:
description:
Present if the subsystem is not authenticated and brought out of reset
by using the PIL ops.
type: boolean
qcom,mem-protect-id:
description:
Virtual ID used by PIL to call into TZ/HYP to protect/unprotect subsystem
related memory.
qcom,gpio-err-fatal:
description: GPIO used by the subsystem to indicate error fatal to the apps.
qcom,gpio-err-ready:
description: GPIO used by the subsystem to indicate error ready to the apps.
qcom,gpio-proxy-unvote:
description:
GPIO used by the subsystem to trigger proxy unvoting in the apps.
qcom,gpio-force-stop:
description: GPIO used by the apps to force the subsystem to shutdown.
qcom,gpio-stop-ack:
description:
GPIO used by the subsystem to ack force stop or a graceful stop to the
apps.
qcom,restart-group:
description: List of subsystems that will need to restart together.
qcom,keep-proxy-regs-on:
description:
Present if during proxy unvoting, PIL needs to leave the regulators
enabled after removing the voltage/current votes.
type: boolean
qcom,edge:
description: GLINK logical name of the remote subsystem
qcom,ssctl-instance-id:
description:
Instance id used by the subsystem to connect with the SSCTL service.
qcom,sysmon-id:
description: Platform device id that sysmon is probed with for the subsystem.
qcom,pil-force-shutdown:
description:
If set, the SSR framework will not trigger graceful shutdown on behalf of
the subsystem driver.
type: boolean
qcom,pil-generic-irq-handler:
description:
Generic interrupt handler used for communication with subsytem based on
bit values in scsr registers.
qcom,spss-scsr-bits:
description:
Array of bit positions into the scsr registers used in generic handler.
qcom,complete-ramdump:
description:
If set, complete ramdump i.e. region between start address of first segment
to end address of last segment will be collected without leaving any hole
in between.
type: boolean
qcom,boot-enabled:
description:
Set this property if subsystem is brought out of reset
during bootloader stage. subsystem-pil-tz driver checks the
crash status of subsystems when initial subsystem request is made.
type: boolean
qcom,ignore-ssr-failure:
description: If set, SSR failures are not considered fatal.
type: boolean
qcom,signal-aop:
description:
If set, when subsystem is brought up, pil will send a notification to AOP
through qmp mailbox driver.
type: boolean
qcom,minidump-id:
description:
ID that is used to index into the global minidump table of contents to
access a subsystem's minidump table of contents.
qcom,aux-minidump-ids:
description:
List of IDs that index into the global minidump table of contents to access
the table of contents for additional minidump entries that should be
collected along with the subsystem's minidump.
interconnects:
description:
Specifies the interconnect bus-master and bus-slave for bandwidth voting
during proxy vote/unvote.
required:
- compatible
- qcom,firmware-name
examples:
- |
pil_scm_pas {
compatible = "qcom,pil-tz-scm-pas";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
};
qcom,venus@fdce0000 {
compatible = "qcom,pil-tz-generic";
reg = <0xfdce0000 0x4000>,
<0xfdc80000 0x400>;
vdd-supply = <&gdsc_venus>;
qcom,proxy-reg-names = "vdd";
clock-names = "core_clk", "iface_clk", "bus_clk", "mem_clk",
"scm_core_clk", "scm_iface_clk", "scm_bus_clk",
"scm_core_clk_src";
qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk",
"mem_clk", "scm_core_clk",
"scm_iface_clk", "scm_bus_clk",
"scm_core_clk_src";
qcom,scm_core_clk_src-freq = <50000000>;
interconnects = <&qnm_video0 MASTER_VIDEO_P0 &mc_virt SLAVE_EBI1>;
qcom,pas-id = <9>;
qcom,proxy-timeout-ms = <2000>;
qcom,firmware-name = "venus";
};
qcom,lpass@fe200000 {
compatible = "qcom,pil-tz-generic";
reg = <0xfe200000 0x00100>,
<0xfd485100 0x00010>,
<0xfc4016c0 0x00004>;
interrupts = <0 162 1>;
vdd_cx-supply = <&pm8841_s2_corner>;
qcom,proxy-reg-names = "vdd_cx";
qcom,vdd_cx-uV-uA = <7 100000>;
clock-names = "bus_clk", "xo", "scm_core_clk", "scm_iface_clk",
"scm_bus_clk", "scm_core_clk_src";
qcom,active-clock-names = "bus_clk";
qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
"scm_bus_clk", "scm_core_clk_src";
qcom,scm_core_clk_src-freq = <50000000>;
qcom,smem-id = <423>;
qcom,pas-id = <1>;
qcom,proxy-timeout-ms = <10000>;
qcom,firmware-name = "adsp";
qcom,edge = "lpass";
/* GPIO inputs from lpass */
qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
/* GPIO output to lpass */
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
qcom,ssctl-instance-id = <14>;
qcom,sysmon-id = <1>;
};

1
bindings/pinctrl/qcom,pmic-gpio.txt
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@@ -37,6 +37,7 @@ PMIC's from Qualcomm.
"qcom,pm6150l-gpio"
"qcom,pm8008-gpio"
"qcom,pmx55-gpio"
"qcom,pm8450-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively

35
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%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/arm/msm/qcom,tlmm-vm-irq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. TLMM VM Irqchip driver binding
maintainers:
description: |+
The driver acts as a parent interrupt controller for tlmm driver for VMs.
properties:
compatible:
const: qcom,tlmm-vm-irq
reg:
items:
- description: Base address of TLMM register space
- description: Size of TLMM register space
interrupt-controller: true
'#interrupt-cells':
const: 2
example:
- |
vm-tlmm-irq@0 {
compatible = "qcom,tlmm-vm-irq";
reg = <0x0 0x0>;
interrupt-controller;
#interrupt-cells = <2>;
};
...

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%YAML 1.2
--
$id: http://devicetree.org/schemas/bindings/arm/msm/qcom,tlmm-vm-mem-access.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. TLMM VM memory access driver binding
maintainers:
description: |+
The driver facilitates initial memory access to TLMM VM driver.
properties:
compatible:
const: qcom,tlmm-vm-mem-access
qcom,master:
description: Specify if this device is on the primary virtual machine.
tlmm-vm-gpio-list:
description: Array of shared gpio numbers in global space.
example:
- |
tlmm-vm-mem-access {
compatible = "qcom,tlmm-vm-mem-access";
qcom,master;
tlmm-vm-gpio-list = <0>;
};
...

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%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,waipio-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. WAIPIO TLMM block
maintainers:
- Elliot Berman <eberman@quicinc.com>
description: |
This binding describes the Top Level Mode Multiplexer block.
properties:
compatible:
const: qcom,waipio-pinctrl
reg:
items:
- description: Base address of TLMM register space
- description: Size of TLMM register space
interrupts:
minItems: 0
maxItems: 1
items:
- const: TLMM summary IRQ
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
wakeup-parent:
maxItems: 1
description:
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
qcom,gpios-reserved:
description:
A list of reserved gpios that should not be used by the kernel drivers.
# PIN CONFIGURATION NODES
patternPropetries:
'^.*$':
if:
type: object
then:
properties:
pins:
description:
List of gpio pins affected by the properties specified in
this subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
enum: [gpio, aon_cam, atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
atest_usb0, atest_usb00, atest_usb01, atest_usb02, atest_usb03, audio_ref, cam_mclk,
cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, coex_uart2, cri_trng, cri_trng0,
cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1,
gcc_gp2, gcc_gp3, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s2_data0, mi2s2_data1,
mi2s2_sck, mi2s2_ws, mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, mss_grfc8, mss_grfc9,
nav_0, nav_1, nav_2, pcie0_clkreqn, pcie1_clkreqn, phase_flag0, phase_flag1,
phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,
phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,
phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,
phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,
phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, pll_bist,
pll_clk, pri_mi2s, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, qlink1_enable,
qlink1_request, qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15,
qup16, qup17, qup18, qup19, qup2, qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8,
qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd,
sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, usb_phy, vfr_0,
vfr_1, vsense_trigger]
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
examples:
- |
tlmm: pinctrl@03000000 {
compatible = "qcom,waipio-pinctrl";
reg = <0x03000000 0xdc2000>;
interrupts = <0 208 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
};

127
bindings/pinctrl/qcom,waipio-vm-pinctrl.yml Normal file
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@@ -0,0 +1,127 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,waipio-vm-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. WAIPIO VM TLMM block
maintainers:
description: |
This binding describes the Top Level Mode Multiplexer block for VM.
properties:
compatible:
const: qcom,waipio-vm-pinctrl
reg:
items:
- description: Base address of TLMM register space
- description: Size of TLMM register space
interrupts-extended:
Value type: <prop-encoded-array>
Definition: reference to the interrupts that match interrupt-names
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpios:
description: array of gpio pin number required by VM TLMM clients
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
# PIN CONFIGURATION NODES
patternPropetries:
'^.*$':
if:
type: object
then:
properties:
pins:
description:
List of gpio pins affected by the properties specified in
this subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
enum: [gpio, aon_cam, atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
atest_usb0, atest_usb00, atest_usb01, atest_usb02, atest_usb03, audio_ref, cam_mclk,
cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, coex_uart2, cri_trng, cri_trng0,
cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1,
gcc_gp2, gcc_gp3, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s2_data0, mi2s2_data1,
mi2s2_sck, mi2s2_ws, mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, mss_grfc8, mss_grfc9,
nav_0, nav_1, nav_2, pcie0_clkreqn, pcie1_clkreqn, phase_flag0, phase_flag1,
phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,
phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,
phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,
phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,
phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, pll_bist,
pll_clk, pri_mi2s, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, qlink1_enable,
qlink1_request, qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15,
qup16, qup17, qup18, qup19, qup2, qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8,
qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd,
sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, usb_phy, vfr_0,
vfr_1, vsense_trigger]
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
examples:
- |
tlmm: pinctrl@03000000 {
compatible = "qcom,waipio-vm-pinctrl";
reg = <0x03000000 0xdc2000>;
interrupts-extended = <0 208 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpios = /bits/ 16 <0 1>;
};

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Qualcomm technologies inc. Internet Packet Accelerator
Internet Packet Accelerator (IPA) is a programmable protocol
processor HW block. It is designed to support generic HW processing
of UL/DL IP packets for various use cases independent of radio technology.
Required properties:
IPA node:
- compatible : "qcom,ipa"
- reg: Specifies the base physical addresses and the sizes of the IPA
registers.
- reg-names: "ipa-base" - string to identify the IPA CORE base registers.
"bam-base" - string to identify the IPA BAM base registers.
"a2-bam-base" - string to identify the A2 BAM base registers.
- pas-ids: specify the image ids of the FW images that needs to be loaded.
- firmware-names:- String name of the FW images that need to be loaded.
- memory-regions:- Carved memory regions of the FW images.
- interrupts: Specifies the interrupt associated with IPA.
- interrupt-names: "ipa-irq" - string to identify the IPA core interrupt.
"bam-irq" - string to identify the IPA BAM interrupt.
"a2-bam-irq" - string to identify the A2 BAM interrupt.
"msi-irq-rmnet-ctl" - string to identify QMAP MSI interrupt
"msi-irq-rmnet-ll" - string to identify LL MSI interrupt
- qcom,ipa-hw-ver: Specifies the IPA hardware version.
- qcom,ipa-ram-mmap: An array of unsigned integers representing addresses and
sizes which are used by the driver to access IPA RAM.
Optional:
- qcom,tx-poll: Enable performing TX completions in polling mode.
- qcom,tx-wrapper-cache-max-size: Define the tx warpper cache pool max size,
if set to zero then the feature is disabled.
- qcom,tx-napi: Enable usage of NAPI in the TX data path.
- qcom,lan-rx-napi: Enable NAPI in the LAN RX data path.
- qcom,ipa-uc-holb-monitor: Enable uC HOLB monitor feature.
- qcom,ipa-holb-monitor-poll-period: Poll period for HOLB monitor feature.
- qcom,holb-monitor-max-cnt-wlan: Max stuck count for HOLB on WLAN channel.
- qcom,holb-monitor-max-cnt-usb: Max stuck count for HOLB on USB channel.
- qcom,holb-monitor-max-cnt-11ad: Max stuck count for HOLB on 11AD channel.
- qcom,wan-rx-ring-size: size of WAN rx ring, default is 192
- qcom,lan-rx-ring-size: size of LAN rx ring, default is 192
- qcom,arm-smmu: SMMU is present and ARM SMMU driver is used
- qcom,msm-smmu: SMMU is present and QSMMU driver is used
- qcom,smmu-fast-map: Boolean context flag to set SMMU to fastpath mode
- ipa_smmu_ap: AP general purpose SMMU device
compatible "qcom,ipa-smmu-ap-cb"
- ipa_smmu_wlan: WDI SMMU device
compatible "qcom,ipa-smmu-wlan-cb"
- ipa_smmu_uc: uc SMMU device
compatible "qcom,ipa-smmu-uc-cb"
- ipa_smmu_11ad: 11AD SMMU device
compatible "qcom,ipa-smmu-11ad-cb"
- qcom,use-a2-service: determine if A2 service will be used
- qcom,use-ipa-tethering-bridge: determine if tethering bridge will be used
- qcom,use-ipa-in-mhi-mode: Boolean context flag to indicate whether
device booting in MHI config or not.
- qcom,use-ipa-bamdma-a2-bridge: determine if a2/ipa hw bridge will be used
- qcom,ee: which EE is assigned to (non-secure) APPS from IPA-BAM POV. This
is a number
- qcom,ipa-hw-mode: IPA hardware mode - Normal, Virtual memory allocation,
memory allocation over a PCIe bridge
-qcom,platform-type: MDM platform, MSM platform or APQ platform
- qcom,msm-bus,name: String representing the client-name
- qcom,msm-bus,num-cases: Total number of usecases
- qcom,msm-bus,active-only: Boolean context flag for requests in active or
dual (active & sleep) contex
- qcom,msm-bus,num-paths: Total number of master-slave pairs
- qcom,msm-bus,vectors-KBps: Arrays of unsigned integers representing:
master-id, slave-id, arbitrated bandwidth
in KBps, instantaneous bandwidth in KBps
- qcom,ipa-bam-remote-mode: Boolean context flag to determine if ipa bam
is in remote mode.
- qcom,modem-cfg-emb-pipe-flt: Boolean context flag to determine if modem
configures embedded pipe filtering rules
- qcom,skip-uc-pipe-reset: Boolean context flag to indicate whether
a pipe reset via the IPA uC is required
- qcom,ipa-wdi2: Boolean context flag to indicate whether
using wdi-2.0 or not
- qcom,ipa-wdi3-over-gsi: Boolean context flag to indicate whether
using wdi-3.0 or not
- qcom,bandwidth-vote-for-ipa: Boolean context flag to indicate whether
ipa clock voting is done by bandwidth
voting via msm-bus-scale driver or not
- qcom,use-64-bit-dma-mask: Boolean context flag to indicate whether
using 64bit dma mask or not
- qcom,use-dma-zone: Boolean context flag to indicate whether memory
allocations controlled by IPA driver that do not
specify a struct device * should use GFP_DMA to
workaround IPA HW limitations
- qcom,use-rg10-limitation-mitigation: Boolean context flag to activate
the mitigation to register group 10
AP access limitation
- qcom,do-not-use-ch-gsi-20: Boolean context flag to activate
software workaround for IPA limitation
to not use GSI physical channel 20
- qcom,tethered-flow-control: Boolean context flag to indicate whether
apps based flow control is needed for tethered
call.
- qcom,rx-polling-sleep-ms: Receive Polling Timeout in millisecond,
default is 1 millisecond.
- qcom,ipa-polling-iteration: IPA Polling Iteration Count,default is 40.
- qcom,mhi-event-ring-id-limits: Two elements property. Start and End limits
for MHI event rings ids.
- qcom,ipa-tz-unlock-reg: Register start addresses and ranges which
need to be unlocked by TZ.
- qcom,ipa-uc-monitor-holb: Boolean context flag to indicate whether
monitoring of holb via IPA uc is required.
-qcom,ipa-fltrt-not-hashable: Boolean context flag to indicate filter/route rules
hashing not supported.
- qcom,wlan-ce-db-over-pcie: Boolean context flag to represent WLAN CE DB
over pcie bus or not.
- qcom,ipa-wdi2_over_gsi: Boolean context flag to indicate WDI2 offload over GSI
supported or not.
- qcom,register-collection-on-crash: Boolean that controls IPA/GSI register
collection upon system crash (i.e. SSR).
- qcom,testbus-collection-on-crash: Boolean that controls testbus register
collection upon system crash.
- qcom,non-tn-collection-on-crash: Boolean to control a certain subset of IPA/GSI
register collection relative to an SSR. Accessing
these registers can cause stalling, hence this
control.
- qcom,entire-ipa-block-size: Complete size of the ipa block in which all
registers, collected upon crash, reside.
- qcom,ipa-endp-delay-wa: Boolean context flag to indicate end point delay work around
supported or not.
- qcom,secure-debug-check-action: Drives secure memory debug check. Three values allowed:
0 (use scm call),
1 (override scm call as though it returned true), and
2 (override scm call as though it returned false)
- qcom,ipa-gpi-event-rp-ddr: Boolean context flag to control whether GPI and GCI event
rings read pointer should be read from the ddr.
- qcom,rmnet-ll-enable: Flag to indicate low latency data channels should be supported
for the target
- qcom,gsi-msi-addr: APSS_GICA_SETSPI_NSR register address for IPA firmware to write
the MSI IRQ number to get the ISR triggered
- qcom,gsi-msi-clear-addr: APSS_GICA_CLRSPI_NSR register address for IPA driver to write
the MSI IRQ number to clear the respective interrupt
- qcom,gsi-rmnet-ctl-evt-ring-intvec: Integer vector value for the QMAP flow control pipe
- qcom,gsi-rmnet-ll-evt-ring-intvec: Integer vector value for the low lat data pipe
IPA pipe sub nodes (A2 static pipes configurations):
-label: two labels are supported, a2-to-ipa and ipa-to-a2 which
supply static configuration for A2-IPA connection.
-qcom,src-bam-physical-address: The physical address of the source BAM
-qcom,ipa-bam-mem-type:The memory type:
0(Pipe memory), 1(Private memory), 2(System memory)
-qcom,src-bam-pipe-index: Source pipe index
-qcom,dst-bam-physical-address: The physical address of the
destination BAM
-qcom,dst-bam-pipe-index: Destination pipe index
-qcom,data-fifo-offset: Data fifo base offset
-qcom,data-fifo-size: Data fifo size (bytes)
-qcom,descriptor-fifo-offset: Descriptor fifo base offset
-qcom,descriptor-fifo-size: Descriptor fifo size (bytes)
Optional properties:
-qcom,ipa-pipe-mem: Specifies the base physical address and the
size of the IPA pipe memory region.
Pipe memory is a feature which may be supported by the
target (HW platform). The Driver support using pipe
memory instead of system memory. In case this property
will not appear in the IPA DTS entry, the driver will
use system memory.
- clocks: This property shall provide a list of entries each of which
contains a phandle to clock controller device and a macro that is
the clock's name in hardware.This should be "clock_rpm" as clock
controller phandle and "clk_ipa_clk" as macro for "iface_clk"
- clock-names: This property shall contain the clock input names used
by driver in same order as the clocks property.This should be "iface_clk"
- emulator-bar0-offset: Specifies the offset, within PCIe BAR0, where
IPA/GSI programmable registers reside. This property is used only
with the IPA/GSI emulation system, which is connected to and
communicated with via PCIe.
IPA SMMU sub nodes
-compatible: "qcom,ipa-smmu-ap-cb" - represents the AP context bank.
-compatible: "qcom,ipa-smmu-wlan-cb" - represents IPA WLAN context bank.
-compatible: "qcom,ipa-smmu-uc-cb" - represents IPA uC context bank (for uC
offload scenarios).
- qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass.
- dma-coherent: Indicate using dma-coherent or not in SMMU block
- iommus : the phandle and stream IDs for the SMMU used by this root
- qcom,iova-mapping: specifies the start address and size of iova space.
- qcom,additional-mapping: specifies any addtional mapping needed for this
context bank. The format is <iova pa size>
IPA SMP2P sub nodes
-compatible: "qcom,smp2p-map-ipa-1-out" - represents the out smp2p from
ipa driver to modem.
-compatible: "qcom,smp2p-map-ipa-1-in" - represents the in smp2p to
ipa driver from modem.
Example:
qcom,ipa@fd4c0000 {
compatible = "qcom,ipa";
reg = <0xfd4c0000 0x26000>,
<0xfd4c4000 0x14818>;
<0xfc834000 0x7000>;
reg-names = "ipa-base", "bam-base"; "a2-bam-base";
interrupts = <0 252 0>,
<0 253 0>;
<0 29 1>;
interrupt-names = "ipa-irq", "bam-irq"; "a2-bam-irq";
qcom,ipa-hw-ver = <1>;
clocks = <&clock_rpm clk_ipa_clk>;
clock-names = "iface_clk";
qcom,msm-bus,name = "ipa";
qcom,msm-bus,num-cases = <3>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
<90 512 0 0>, <90 585 0 0>, /* No vote */
<90 512 100000 800000>, <90 585 100000 800000>, /* SVS */
<90 512 100000 1200000>, <90 585 100000 1200000>; /* PERF */
qcom,bus-vector-names = "MIN", "SVS", "PERF";
qcom,pipe1 {
label = "a2-to-ipa";
qcom,src-bam-physical-address = <0xfc834000>;
qcom,ipa-bam-mem-type = <0>;
qcom,src-bam-pipe-index = <1>;
qcom,dst-bam-physical-address = <0xfd4c0000>;
qcom,dst-bam-pipe-index = <6>;
qcom,data-fifo-offset = <0x1000>;
qcom,data-fifo-size = <0xd00>;
qcom,descriptor-fifo-offset = <0x1d00>;
qcom,descriptor-fifo-size = <0x300>;
};
qcom,pipe2 {
label = "ipa-to-a2";
qcom,src-bam-physical-address = <0xfd4c0000>;
qcom,ipa-bam-mem-type = <0>;
qcom,src-bam-pipe-index = <7>;
qcom,dst-bam-physical-address = <0xfc834000>;
qcom,dst-bam-pipe-index = <0>;
qcom,data-fifo-offset = <0x00>;
qcom,data-fifo-size = <0xd00>;
qcom,descriptor-fifo-offset = <0xd00>;
qcom,descriptor-fifo-size = <0x300>;
};
/* smp2p information */
qcom,smp2p_map_ipa_1_out {
compatible = "qcom,smp2p-map-ipa-1-out";
};
qcom,smp2p_map_ipa_1_in {
compatible = "qcom,smp2p-map-ipa-1-in";
};
ipa_smmu_ap: ipa_smmu_ap {
compatible = "qcom,ipa-smmu-ap-cb";
iommus = <&apps_smmu 0x720>;
qcom,iova-mapping = <0x20000000 0x40000000>;
qcom,additional-mapping =
/* modem tables in IMEM */
<0x146bd000 0x146bd000 0x2000>;
};
ipa_smmu_wlan: ipa_smmu_wlan {
compatible = "qcom,ipa-smmu-wlan-cb";
iommus = <&apps_smmu 0x721>;
qcom,additional-mapping =
/* ipa-uc ram */
<0x1e60000 0x1e60000 0x80000>;
};
ipa_smmu_uc: ipa_smmu_uc {
compatible = "qcom,ipa-smmu-uc-cb";
iommus = <&apps_smmu 0x722>;
qcom,iova-mapping = <0x40000000 0x20000000>;
};
ipa_smmu_11ad: ipa_smmu_11ad {
compatible = "qcom,ipa-smmu-11ad-cb";
iommus = <&apps_smmu 0x5C3 0x0>;
dma-coherent;
qcom,shared-cb;
qcom,iommu-group = <&wil6210_pci_iommu_group>;
};
};

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* Qualcomm Technologies, Inc. IPA MHI Prime Manager driver module
This module enables IPA Modem to IPA APQ communication using
MHI Prime.
Required properties:
- compatible: Must be "qcom,ipa-mpm"
- qcom,mhi-chdb-base: MHI channel doorbell base address in MMIO space.
- qcom,mhi-erdb-base: MHI event doorbell base address in MMIO space.
Optional:
- qcom,iova-mapping: Start address and size of the carved IOVA space
dedicated for MHI control structures
(such as transfer rings, event rings, doorbells).
If not present, SMMU S1 is considered to be in bypass mode.
Example:
ipa_mpm: qcom,ipa-mpm {
compatible = "qcom,ipa-mpm";
qcom,mhi-chdb-base = <0x40300300>;
qcom,mhi-erdb-base = <0x40300700>;
qcom,iova-mapping = <0x10000000 0x1FFFFFFF>;
}

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* Qualcomm Technologies, Inc. GSI driver module
GSI is a HW accelerator that supports Generic SW Interfaces (GSI) which are
peripheral specific (IPA in this case).
GSI translates SW transfer elements (TRE) into TLV transactions which are
then processed by the peripheral.
This Driver configures and communicates with GSI HW.
Required properties:
- compatible: Must be "qcom,msm_gsi"
Example:
qcom,msm-gsi {
compatible = "qcom,msm_gsi";
}

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Qualcomm Technologies, Inc. GENI Serial Engine Driver
GENI Serial Engine Driver is used to configure and read the configuration
from the Serial Engines on Qualcomm Technologies, Inc. Universal Peripheral
(QUPv3) core. It is also used to enable the stage1 IOMMU translation and
manage resources associated with the QUPv3 core.
Required properties:
- compatible: Must be "qcom,qupv3-geni-se".
- reg: Must contain QUPv3 register address and length.
- qcom,bus-mas-id: Master Endpoint ID for bus driver.
- qcom,bus-slv-id: Slave Endpoint ID for bus driver.
Optional properties:
- qcom,iommu-s1-bypass: Boolean flag to bypass IOMMU stage 1 translation.
- qcom,msm-bus,num-paths: Number of paths to put vote for.
- qcom,msm-bus,vectors-bus-ids: Master and slave Endpoint IDs for DDR
and Corex/2x paths.
- interconnect-names: "qup-core" for the qup master to slave path
"snoc-llcc" middle path from SNOC to GEMNOC
"qup-ddr" for the qup master to DDR path
This way ensure the path from aggre1_noc ->
system_noc -> gem_noc -> mc_virt is complete.
- interconnects: Master to Slave endpoint nodes for the required paths.
Optional subnodes:
qcom,iommu_qupv3_geni_se_cb: Child node representing the QUPV3 context
bank.
Subnode Required properties:
- compatible : Must be "qcom,qupv3-geni-se-cb";
- iommus: A list of phandle and IOMMU specifier pairs that
describe the IOMMU master interfaces of the device.
Example:
qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0x8c0000 0x6000>;
qcom,bus-mas-id = <100>;
qcom,bus-slv-id = <300>;
iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {
compatible = "qcom,qupv3-geni-se-cb";
iommus = <&apps_smmu 0x1 0x0>;
};
}

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QPNP-REVID
QPNP-REVID provides a way to read the PMIC part number and revision.
Required properties:
- compatible : should be "qcom,qpnp-revid"
- reg : offset and length of the PMIC peripheral register map.
Optional property:
- qcom,fab-id-valid: Use this property when support to read Fab
identification from REV ID peripheral is available.
- qcom,tp-rev-valid: Use this property when support to read TP
revision identification from REV ID peripheral.
Example:
qcom,revid@100 {
compatible = "qcom,qpnp-revid";
reg = <0x100 0x100>;
};

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* Qualcomm Technologies, Inc. RmNet IPA driver module
This module enables embedded data calls using IPA v3 HW.
Required properties:
- compatible: Must be "qcom,rmnet-ipa3"
Optional:
- qcom,rmnet-ipa-ssr: determine if modem SSR is supported
- qcom,ipa-platform-type-msm: indicates the platform type is msm or not
- qcom,ipa-advertise-sg-support: determine how to respond to a query
regarding scatter-gather capability
- qcom,ipa-napi-enable: Boolean context flag to indicate whether
to enable napi framework or not
- qcom,wan-rx-desc-size: size of WAN rx desc fifo ring, default is 256
Example:
qcom,rmnet-ipa3 {
compatible = "qcom,rmnet-ipa3";
qcom,wan-rx-desc-size = <256>;
}

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MSM USB Bus Access Manager (BAM)
This describes the device used to interface the USB controller
with the Smart Peripheral Subsystem (SPS). The BAM serves to
connect USB directly with other peer peripherals in the system
and is statically configured with a number of unidirectional pipes.
Required properties:
- compatible: should be "qcom,usb-bam-msm"
- reg : pair of physical base addresses and region size of BAM device
- interrupts: IRQ line for BAM device
- qcom,usb-bam-num-pipes: max number of pipes that can be used
Optional properties:
- qcom,usb-bam-fifo-baseaddr: base address for bam pipe's data and descriptor
fifos. This can be on chip memory (ocimem). This
property is required if sub-node's mem-type is ocimem or usb private mem.
- qcom,disable-clk-gating: If present then disable BAM clock gating.
- qcom,usb-bam-override-threshold: If present then the default 512 byte threshold
is overridden. This threshold configures the threshold value for Read/Write
event generation by the BAM towards another BAM.
- qcom,usb-bam-max-mbps-highspeed: max mbps in high speed connection
for either rx or tx direction.
- qcom,usb-bam-max-mbps-superspeed: max mbps in super speed connection
for either rx or tx direction.
- qcom,reset-bam-on-connect: If present then BAM is RESET before connecting
pipe. This may be required if BAM peripheral is also reset before connect.
- qcom,reset-bam-on-disconnect: If present then BAM is RESET after disconnecting pipes.
A number of USB BAM pipe parameters are represented as sub-nodes:
Subnode Required:
- label: a string describing uniquely the usb bam pipe. The string can be
constracted as follows: <core>-<peer>-<direction>-<pipe num>.
core options: hsusb, ssusb/dwc3, hsic
peer options: qdss, ipa
direction options: in (from peer to usb), out (from usb to peer)
pipe num options: 0..127
- qcom,usb-bam-mem-type: Type of memory used by this PIPE. Can be one of
0 - Uses SPS's dedicated pipe memory
1 - System RAM allocated by driver
2 - OCI memory residing @ 'qcom,usb-bam-fifo-baseaddr'
- qcom,dir: pipe direction
0 - from usb (out)
1 - to usb (in)
- qcom,pipe-num: pipe number
- qcom,peer-bam: peer BAM can be one of
0 - QDSS_P_BAM
1 - IPA_P_BAM
- qcom,data-fifo-size: data fifo size
- qcom,descriptor-fifo-size: descriptor fifo size
Optional Properties for Subnode:
- qcom,peer-bam-physical-address: peer BAM's physical address.
Not specified for IPA and used only for qdss connection
- qcom,dst-bam-pipe-index: destination BAM pipe index
- qcom,src-bam-pipe-index: source BAM pipe index
- qcom,data-fifo-offset: data fifo offset address
- qcom,descriptor-fifo-offset: descriptor fifo offset address
- qcom,pipe-connection-type: type of pipe connection. Can be one of
0 - BAM2BAM (default if not specified)
1 - SYS2BAM (only supported on UL)
Example USB BAM controller device node:
qcom,usbbam@f9a44000 {
compatible = "qcom,usb-bam-msm";
reg = <0xf9a44000 0x11000>;
interrupts = <0 135 0>;
qcom,usb-bam-num-pipes = <16>;
qcom,ignore-core-reset-ack;
qcom,disable-clk-gating;
qcom,usb-bam-max-mbps-highspeed = <400>;
qcom,usb-bam-max-mbps-superspeed = <3600>;
qcom,bam-type = <1>;
qcom,bam-mode = <0>;
qcom,pipe0 {
label = "hsusb-ipa-out-0";
qcom,usb-bam-mem-type = <0>;
qcom,dir = <0>;
qcom,pipe-num = <0>;
qcom,peer-bam = <2>;
qcom,src-bam-pipe-index = <1>;
qcom,data-fifo-offset = <0x2200>;
qcom,data-fifo-size = <0x1e00>;
qcom,descriptor-fifo-offset = <0x2100>;
qcom,descriptor-fifo-size = <0x100>;
};
qcom,pipe1 {
label = "hsusb-ipa-in-0";
qcom,usb-bam-mem-type = <0>;
qcom,dir = <1>;
qcom,pipe-num = <0>;
qcom,peer-bam = <2>;
qcom,dst-bam-pipe-index = <0>;
qcom,data-fifo-offset = <0x300>;
qcom,data-fifo-size = <0x1e00>;
qcom,descriptor-fifo-offset = <0>;
qcom,descriptor-fifo-size = <0x300>;
};
};

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%YAML 1.2
---
$id: "http://devicetree.org/schemas/power/reset/qcom-reboot-reason.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Technologies, Inc. reboot reason binding
maintainers:
- Elliot Berman <eberman@quicinc.com>
description: |
Qualcomm Technologies, Inc. SoCs support booting to special download
modes after a restart. These modes could be a normal restart,
restarting into a ramdump collection mode (CrashDump), or restarting
into "emergency download mode".
properties:
compatible:
items:
- const: qcom,reboot-mode
allOf:
- $ref: /schemas/nvmem/nvmem-consumer.yaml#/properties
- items:
nvmem-cell-names:
items:
- const: restart_reason
required:
- compatible
- nvmem-cells-names
dependencies:
allOf:
- $ref: /schemas/nvmem/nvmem-consumer.yaml#/dependencies
examples:
- |
reboot-reason {
compatible = "qcom,reboot-reason";
nvmem-cells = <&restart_reason>;
nvmem-cell-names = "restart_reason";
};

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* RNG (Random Number Generator)
Required properties:
- compatible : Should be "qcom,msm-rng"
- reg : Offset and length of the register set for the device
Optional property:
- qcom,msm-rng-iface-clk : If the device uses iface-clk.
- qcom,no-qrng-config : Flag to decide whether the driver do the hardware configuration or not.
Example:
qcom,msm-rng@f9bff000 {
compatible = "qcom,msm-rng";
reg = <0xf9bff000 0x200>;
qcom,msm-rng-iface-clk;
qcom,no-qrng-config;
};

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Qualcomm Technologies, Inc. LPG driver specific bindings
This binding document describes the properties of LPG (Light Pulse Generator)
device module in Qualcomm Technologies, Inc. PMIC chips.
- compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,pwm-lpg".
- reg:
Usage: required
Value type: <u32>
Definition: Register base for LPG and LUT modules.
- reg-names:
Usage: required
Value type: <string>
Definition: The name of the register defined in the reg property.
It must have "lpg-base", "lut-base" is optional but
it's required if any LPG channels support LUT mode
with a LUT module.
- #pwm-cells:
Usage: required
Value type: <u32>
Definition: The number of cells in "pwms" property specified in
PWM user nodes. It should be 2. The first cell is
the PWM channel ID indexed from 0, and the second
cell is the PWM default period in nanoseconds.
- qcom,num-lpg-channels:
Usage: required
Value type: <u32>
Definition: The number of the consecutive LPG/PWM channels in the chip.
- qcom,pfm-chan-ids:
Usage: optional
Value type: <u32 array>
Definition: 1-indexed channel numbers that support Pulse Frequency
Modulation (PFM) in which duty cycle is fixed at 50% and
only the period/frequency can be changed. PFM mode will
be enabled only if the HW supports it.
- nvmem-names:
Usage: optional
Value type: <stringlist>
Definition: The nvmem device name(s) for the SDAM module(s) where the
LUT pattern data is stored. This property is required
only when LUT mode is supported with a SDAM module
instead of a LUT module. It can take the following
mutually exclusive sets of values:
(a) "ppg_sdam":
LUT pattern data and per-channel data are stored in a
single SDAM module.
(b) "lut_sdam", "lpg_chan_sdam":
LUT pattern data and per-channel data are stored in
two different SDAM modules.
- nvmem:
Usage: optional
Value type: <phandle-list>
Definition: Phandle(s) of the nvmem device(s) to access the LUT stored
in the SDAM module(s). This property is required only when
LUT mode is supported and the LUT pattern is stored in
SDAM modules instead of a LUT module.
- qcom,pbs-client
Usage: optional
Value type: <phandle>
Definition: Phandle of the PBS client used for sending the PBS
trigger. This property is required when LUT mode is
supported and the LUT pattern is stored in a single SDAM
module (not two) instead of a LUT module.
- qcom,lut-sdam-base:
Usage: optional
Value type: <u32>
Definition: The register base of the LUT entries stored in SDAM. This
property is required only when LUT mode is supported and
the LUT pattern is stored in a SDAM module instead of a
LUT module.
- qcom,lut-patterns:
Usage: optional
Value type: <prop-encoded-array>
Definition: Duty ratios in percentages for LPG working at LUT mode.
These duty ratios will be translated into PWM values
and stored in LUT or SDAM module shared for all LPG
channels. The LUT module has resource to store 47 PWM
values at max while SDAM module can store upto 64 PWM
values. This property is required if any LPG channels
support LUT mode.
- qcom,sync-channel-ids:
Usage: optional
Value type: <prop-encoded-array>
Definition: The hardware IDs of the LPG channel that required be
grouped together. These channels will share the same LUT
ramping configuration so that they will be enabled with a
synchronized pattern. If the LUT ramping configuration
differs for the channels grouped for synchronization,
configuration of the first channel will be applied for
all others.
Subnode is optional if LUT mode is not required, it's required if any LPG
channels expected to be supported in LUT mode.
Subnode properties:
Subnodes for each LPG channel (lpg@X) can be defined if any of the following
parameters needs to be configured for that channel. These properties cannot be
specified for a channel that is configured as PFM enabled using the
`qcom,pfm-chan-ids` property.
- qcom,lpg-chan-id:
Usage: required
Value type: <u32>
Definition: The LPG channel's hardware ID indexed from 1. Allowed
range is 1 - 8. Maximum value depends on the number of
channels supported on PMIC. Cannot specify this property
for a channel that is PFM enabled.
- qcom,lpg-sdam-base:
Usage: optional
Value type: <u32>
Definition: Register base address for LPG configuration in SDAM for
the LPG channel specified under "qcom,lpg-chan-id".
This property is required if LUT mode is supported with
a SDAM module.
- qcom,ramp-step-ms:
Usage: required
Value type: <u32>
Definition: The step duration in milliseconds for LPG staying at each
duty specified in the LUT pattern. Allowed range:
1 - 511 when LUT module is used, and 8 - 2000 when SDAM
is used.
- qcom,tick-duration-us:
Usage: optional
Value type: <u32>
Definition: The tick duration in microseconds for PPG. If this property
is not specified, a default value of 7800 will be used.
- qcom,ramp-high-index:
Usage: required
Value type: <u32>
Definition: The high index of the LUT pattern where LPG ends up
ramping to. Allowed range: 1 - 47 when LUT module
is used, and 1 - 64 when SDAM module is used.
- qcom,ramp-low-index:
Usage: required
Value type: <u32>
Definition: The low index of the LUT pattern from where LPG begins
ramping from. The ramp-low-index should be always less
than ramp-high-index when SDAM module is used. Allowed
range: 0 - 46 when LUT module is used, and 0 - 63 when
SDAM module is used.
- qcom,ramp-pattern-repeat:
Usage: optional
Value type: <empty>
Definition: The flag to specify if LPG would be ramping with the LUT
pattern repeatedly.
- qcom,ramp-pause-hi-count:
Usage: optional
Value type: <u32>
Definition: The number of step counts for which the LPG will continue
to hold the output after it has ramped up to the high
index of the LUT. Allowed range: 0 - 254 if SDAM is used.
- qcom,ramp-pause-lo-count:
Usage: optional
Value type: <u32>
Definition: The number of step counts for which the LPG will continue
to hold the output after it has ramped down to the low
index of the LUT. Allowed range: 0 - 254 if SDAM is used.
- qcom,ramp-from-low-to-high:
Usage: optional
Value type: <empty>
Definition: The flag to specify the LPG ramping direction. The ramping
direction is from low index to high index of the LUT
pattern if it's specified. This property is not required
when SDAM module is used.
- qcom,ramp-toggle:
Usage: optional
Value type: <empty>
Definition: The flag to specify if LPG would toggle the LUT pattern
in ramping. If toggling enabled, LPG would return to the
low index when high index is reached, or return to the high
index when low index is reached. This property is not
required when SDAM module is used.
Example when LUT pattern is stored in a LUT module:
pm8150l_lpg: lpg@b100 {
compatible = "qcom,pwm-lpg";
reg = <0xb100>, <0xb000>;
reg-names = "lpg-base", "lut-base";
qcom,num-lpg-channels = <6>;
#pwm-cells = <2>;
qcom,lut-patterns = <0 14 28 42 56 70 84 100
100 84 70 56 42 28 14 0>;
lpg@1 {
qcom,lpg-chan-id = <1>;
qcom,ramp-step-ms = <200>;
qcom,ramp-pause-hi-count = <10>;
qcom,ramp-pause-lo-count = <10>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <15>;
qcom,ramp-from-low-to-high;
qcom,ramp-pattern-repeat;
};
lpg@2 {
qcom,lpg-chan-id = <2>;
qcom,ramp-step-ms = <200>;
qcom,ramp-pause-hi-count = <10>;
qcom,ramp-pause-lo-count = <10>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <15>;
qcom,ramp-from-low-to-high;
qcom,ramp-pattern-repeat;
};
lpg@3 {
qcom,lpg-chan-id = <3>;
qcom,ramp-step-ms = <200>;
qcom,ramp-pause-hi-count = <10>;
qcom,ramp-pause-lo-count = <10>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <15>;
qcom,ramp-from-low-to-high;
qcom,ramp-pattern-repeat;
};
};
Example when LUT pattern is stored in a SDAM module:
pmi632_lpg: lpg@b100 {
compatible = "qcom,pwm-lpg";
reg = <0xb100>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <3>;
#pwm-cells = <2>;
nvmem-names = "ppg_sdam";
nvmem = <&sdam7>;
qcom,pbs-client = <&pbs_client_3>;
qcom,lut-sdam-base = <0x80>;
qcom,lut-patterns = <0 14 28 42 56 70 84 100
100 84 70 56 42 28 14 0>;
lpg@1 {
qcom,lpg-sdam-base = <0x48>:
qcom,lpg-chan-id = <1>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <15>;
qcom,ramp-pause-hi-count = <10>;
qcom,ramp-pause-lo-count = <10>;
qcom,ramp-pattern-repeat;
};
lpg@2 {
qcom,lpg-sdam-base = <0x56>;
qcom,lpg-chan-id = <2>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <15>;
qcom,ramp-pause-hi-count = <10>;
qcom,ramp-pause-lo-count = <10>;
qcom,ramp-pattern-repeat;
};
lpg@3 {
qcom,lpg-sdam-base = <0x64>;
qcom,lpg-chan-id = <3>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <15>;
qcom,ramp-pause-hi-count = <10>;
qcom,ramp-pause-lo-count = <10>;
qcom,ramp-pattern-repeat;
};
};
Example when LUT pattern is stored in two SDAM modules:
pm8350c_pwm_1: pwms@e800 {
compatible = "qcom,pwm-lpg";
reg = <0xe800>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <3>;
nvmem = <&pmk8350_sdam_21 &pmk8350_sdam_22>;
nvmem-names = "lpg_chan_sdam", "lut_sdam";
qcom,lut-sdam-base = <0x45>;
qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
90 80 70 60 50 40 30 20 10 0>;
lpg@1 {
qcom,lpg-sdam-base = <0x48>;
qcom,lpg-chan-id = <1>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pause-hi-count = <10>;
qcom,ramp-pause-lo-count = <10>;
qcom,ramp-pattern-repeat;
};
lpg@2 {
qcom,lpg-sdam-base = <0x56>;
qcom,lpg-chan-id = <2>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pause-hi-count = <10>;
qcom,ramp-pause-lo-count = <10>;
qcom,ramp-pattern-repeat;
};
lpg@3 {
qcom,lpg-sdam-base = <0x64>;
qcom,lpg-chan-id = <3>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pause-hi-count = <10>;
qcom,ramp-pause-lo-count = <10>;
qcom,ramp-pattern-repeat;
};
};

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Qualcomm Technologies, Inc. QBT_HANDLER Specific Bindings
QBT is a fingerprint sensor ASIC capable of performing fingerprint image scans
and detecting finger presence on the sensor using programmable firmware.
=======================
Required Node Structure
=======================
- compatible
Usage: required
Value type: <string>
Definition: "qcom,qbt-handler".
- qcom,ipc-gpio
Usage: required
Value type: <phandle>
Definition: phandle for GPIO to be used for IPC.
- qcom,finger-detect-gpio
Usage: required
Value type: <phandle>
Definition: phandle for GPIO to be used for finger detect.
=======
Example
=======
qcom,qbt_handler {
compatible = "qcom,qbt-handler";
qcom,ipc-gpio = <&tlmm 38 0>;
qcom,finger-detect-gpio = <&tlmm 39 0>;
};

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Qualcomm Technologies, Inc. SSC Driver
msm-ssc-sensors driver implements the mechanism that allows to load SLPI firmware images.
Required properties:
- compatible: This must be "qcom,msm-ssc-sensors".
Optional properties:
- qcom,firmware-name: SLPI firmware name, must be "slpi" or "slpi_v1" or "slpi_v2"
Firmware name is not required, if sensors driver is sharing processor for execution.
Example:
The following for sdm845.
qcom,msm-ssc-sensors {
compatible = "qcom,msm-ssc-sensors";
qcom,firmware-name = "slpi";
};

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* QSEECOM (QTI Secure Execution Environment Communicator)
Required properties:
- compatible : Should be "qcom,qseecom"
- reg : should contain memory region address reserved for loading secure apps.
- qcom,disk-encrypt-pipe-pair : indicates what CE HW pipe pair is used for disk encryption
- qcom,file-encrypt-pipe-pair : indicates what CE HW pipe pair is used for file encryption
- qcom,support-multiple-ce-hw-instance : indicates if multicore CE support is supported.
- qcom,hlos-num-ce-hw-instances : indicates number of CE HW instances hlos can use.
- qcom,hlos-ce-hw-instance : indicates what CE HW is used by HLOS crypto driver
- qcom,qsee-ce-hw-instance : indicates what CE HW is used by secure domain (TZ) crypto driver
- qcom, msm_bus,name: Should be "qseecom-noc"
- qcom, msm_bus,num_cases: Depends on the use cases for bus scaling
- qcom, msm_bus,num_paths: The paths for source and destination ports
- qcom, msm_bus,vectors: Vectors for bus topology.
- qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target.
- qcom,full-disk-encrypt-info : Vectors defining full disk encryption unit, crypto engine, pipe pair configuration in <unit#, ce#, pipe-pair#>
- qcom,per-file-encrypt-info : Vectors defining per file encryption unit, crypto engine, pipe pair configuration in <unit#, ce#, pipe-pair#>
Optional properties:
- qcom,support-bus-scaling : indicates if driver support scaling the bus for crypto operation.
- qcom,support-fde : indicates if driver support key managing for full disk encryption feature.
- qcom,support-pfe : indicates if driver support key managing for per file encryption feature.
- qcom,no-clock-support : indicates clocks are not handled by qseecom (could be handled by RPM)
- qcom,appsbl-qseecom-support : indicates if there is qseecom support in appsbootloader
- vdd-hba-supply : handle for fixed power regulator
- qcom,qsee-reentrancy-support: indicates the qsee reentrancy phase supported by the target
- qcom,commonlib64-loaded-by-uefi: indicates commonlib64 is loaded by uefi already
- qcom,fde-key-size: indicates which FDE key size is used in device.
Example:
qcom,qseecom@7f00000 {
compatible = "qcom,qseecom";
reg = <0x7f00000 0x500000>;
reg-names = "secapp-region";
qcom,disk-encrypt-pipe-pair = <2>;
qcom,file-encrypt-pipe-pair = <0>;
qcom,support-multiple-ce-hw-instance;
qcom,hlos-num-ce-hw-instances = <2>;
qcom,hlos-ce-hw-instance = <1 2>;
qcom,qsee-ce-hw-instance = <0>;
qcom,support-fde;
qcom,support-pfe;
qcom,msm_bus,name = "qseecom-noc";
qcom,msm_bus,num_cases = <4>;
qcom,msm_bus,active_only = <0>;
qcom,msm_bus,num_paths = <1>;
qcom,no-clock-support;
qcom,appsbl-qseecom-support;
qcom,fde-key-size;
qcom,msm_bus,vectors =
<55 512 0 0>,
<55 512 3936000000 393600000>,
<55 512 3936000000 393600000>,
<55 512 3936000000 393600000>;
qcom,ce-opp-freq = <100000000>;
vdd-hba-supply = <&gdsc_ufs>;
};
Example: The following dts setup is the same as the example above.
qcom,qseecom@7f00000 {
compatible = "qcom,qseecom";
reg = <0x7f00000 0x500000>;
reg-names = "secapp-region";
qcom,support-fde;
qcom,full-disk-encrypt-info = <0 1 2>, <0 2 2>;
qcom,support-pfe;
qcom,per-file-encrypt-info = <0 1 0>, <0 2 0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,msm_bus,name = "qseecom-noc";
qcom,msm_bus,num_cases = <4>;
qcom,msm_bus,active_only = <0>;
qcom,msm_bus,num_paths = <1>;
qcom,no-clock-support;
qcom,appsbl-qseecom-support;
qcom,fde-key-size;
qcom,msm_bus,vectors =
<55 512 0 0>,
<55 512 3936000000 393600000>,
<55 512 3936000000 393600000>,
<55 512 3936000000 393600000>;
qcom,ce-opp-freq = <100000000>;
vdd-hba-supply = <&gdsc_ufs>;
};

4
bindings/remoteproc/qcom,adsp.txt
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@@ -29,6 +29,10 @@ on the Qualcomm ADSP Hexagon core.
"qcom,sm8350-cdsp-pas"
"qcom,sm8350-slpi-pas"
"qcom,sm8350-mpss-pas"
"qcom,waipio-adsp-pas"
"qcom,waipio-cdsp-pas"
"qcom,waipio-slpi-pas"
"qcom,waipio-modem-pas"
- interrupts-extended:
Usage: required

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Qualcomm Technologies, Inc. SPSS Peripheral Image Loader
This document defines the binding for a component that loads and boots firmware
on the QTI Secure Processor.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,waipio-spss-pas"
- reg:
Usage: required
Value type: <prop-encoded>
Definition: pairs of physical base addresses and region sizes of memory
mapped registers
- reg-names:
Usage: required
Value type: <stringlist>
Definition: names of the registers defined by the 'reg' property above
- interrupts:
Usage: required
Value type: <prop-encoded>
Definition: generic interrupt
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the xo clock and optionally aggre2 clock to be
held on behalf of the booting Hexagon core
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "xo" and optionally include "aggre2"
- cx-supply:
Usage: required
Value type: <phandle>
Definition: reference to the regulator to be held on behalf of the
booting Hexagon core
- px-supply:
Usage: required
Value type: <phandle>
Definition: reference to the px regulator to be held on behalf of the
booting Hexagon core
- memory-region:
Usage: required
Value type: <phandle>
Definition: reference to the reserved-memory for the ADSP
= SUBNODES
The adsp node may have an subnode named "glink-edge" that describes the
communication edge, channels and devices related to the SPSS.

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* MSM Serial UART for GENI based cores.
The MSM serial UART driver supports low speed and high speed use-cases.
This is meant only for QUPv3 GENI based cores and isn't backwards compatible.
There is support for console usecases and for higher speed usecases that need
DMA.
Required properties:
- compatible: should contain "qcom,msm-geni-uart, qcom,msm-geni-console"
for UART console usecases, "qcom,msm-geni-uart, qcom,msm-geni-serial-hs"
for High Speed (HS) usecases.
- reg: Should contain UART register location and length.
- interrupts: Should contain UART core interrupts.
- clocks: clocks needed for UART, includes the core and AHB clock.
- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
Should be "active" and "sleep" for the pin confuguration when core is active
or when entering sleep state.
- qcom,wrapper-core: Wrapper QUPv3 core containing this UART controller.
Optional properties:
- qcom,wakeup-byte: Byte to be injected in the tty layer during wakeup isr.
- qcom,change-sampling-rate: This is a boolean parameter and use this to decide
the samping rate at which sequencer engine runs.
Example:
qupv3_uart11: qcom,qup_uart@0xa88000 {
compatible = "qcom,msm-geni-uart";
reg = <0xa88000 0x7000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qup_1_uart_3_active>;
pinctrl-1 = <&qup_1_uart_3_sleep>;
interrupts = <0 355 0>;
qcom,wrapper-core = <&qupv3_0>;
qcom,change-sampling-rate;
qcom,wakeup-byte = <0xFF>;
};

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* SMCInvoke driver to provide transport between TZ and Linux
Required properties:
- compatible : Should be "qcom,smcinvoke"
Example:
qcom_smcinvoke: smcinvoke@87900000 {
compatible = "qcom,smcinvoke";
};

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Qualcomm Technologies, Inc. CDSP Request Manager driver
CDSP Request Manager driver implements an rpmsg interface with
CDSP subsystem to serve L3 frequency and CPU QoS requests from CDSP.
It also interacts with NPU, Camera modules for Cx iPeak mitigations and
thermal module via CDSP/HVX cooling devices for thermal mitigation of
CDSP core. It sends VTCM partitioning information on supported chipsets
to CDSP.
Required properties:
- compatible: Must be "qcom,msm-cdsprm-rpmsg"
- qcom,glink-channels: Glink channel for communication with CDSP
- qcom,intents: A list of <number of intents, size of each intent>
- qcom,msm-cdsp-rm: A sub-device node to define CDSPM RM, Cx iPeak mitigation
driver, CDSP core thermal cooling device and CDSP VTCM partitioning
Required properties:
- compatible: Must be "qcom,msm-cdsp-rm"
- qcom,qos-latency-us: pm_qos latency vote to be applied on CDSP request in
micro seconds
- qcom,qos-maxhold-ms: Maximum hold time for pm_qos latency vote from CDSP
in milli seconds
Optional properties:
Cx iPeak limit management:
- qcom,compute-cx-limit-en: To enable CX ipeak limit management for compute
subsystem
- qcom,compute-priority-mode: when Cx iPeak mitigation is enabled,
this field sets desired compute priority mode
for AIX and HVX concurrency cases based on
following values, where in HVX and NPU cores,
if required, are throttled in concurrency based
on the selected priority mode
1 : HVX_MAX - Allows HVX to run at maximum possible
frequency during concurrency with NPU
2 : AIX_MAX - Allows NPU to run at maximum possible
frequency during concurrency with HVX
3 : HVX_OVER_AIX - Allows HVX to run at a higher
frequency than NPU during concurrency
4 : AIX_OVER_HVX - Allows NPU to run at a higher
frequency than HVX during concurrency
VTCM partitioning:
- qcom,vtcm-paritions: Number of VTCM partitions (maximum 16)
- qcom,vtcm-partition-info: Specifies the partitions, their sizes and
flags. Most importantly flags can be used to
set some partitions as privileged,
i.e. only available to privileged clients.
Currently VTCM_FLAG_PRIMARY(0x1), VTCM_FLAG_SECONDARY (0x2)and
VTCM_FLAG_PRIVILEGED(0x4) are the supported flags per partition
(only one per partition).
Size of each partition should be a multiple of 256KB.
Given 256KB is the minimum VTCM allocation size,
256K, 1M, 4M are supported page sizes.
Specifying a 3MB partition will allow maximum of 1MB page (3x).
Similarly, a 512KB partition will be of 256KB pages (2x).
PRIMARY and SECONDARY partitions are available to all the clients while
the PRIMARY partition is used by default. Partition selection is
controlled by the vtcm-partition-map information.
There must be only one PRIMARY partition.
Partitions must be defined with a linear partition index
starting with 0 till (Number of VTCM partitions - 1).
VTCM memory will be partitioned in the order provided
(0 being the first partition).
- qcom,vtcm-partition-map: Maps application type identifiers to
partitions. Clients use application type IDs to
request non-default partitions.
Application identifier is specified as a value [0 – 31]
in the device tree. The default application identifier
will be 0. Application identifier must be unique for each
partition map. Any unassigned application identifier
in the set of [0 – 31] will be mapped to the PRIMARY partition
and will return failure if there is no
PRIMARY partition configured.
Thermal cooling device:
- #cooling-cells: Number of cooling cells for CDSP cooling device based on
CDSP Q6 core clock throttling
- qcom,msm-hvx-rm: A sub-device node to define HVX based thermal cooling device
Required properties:
- compatible: Must be "qcom,msm-hvx-rm"
- #cooling-cells: Number of cooling cells for CDSP cooling device based on
HVX hardware throttling
- qcom,cdsp-l3: A sub-device node to define CDSP L3 target device for L3
clock voting
Required properties:
- compatible: Must be "qcom,cdsp-l3"
- qcom,target-dev: The DT device that corresponds to the CDSP L3
devfreq-simple-dev
Example:
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
qcom,intents = <0x14 64>;
qcom,cdsp-l3 {
compatible = "qcom,cdsp-l3";
qcom,target-dev = <&cdsp-cdsp-l3-lat>;
};
qcom,msm_cdsp_rm {
compatible = "qcom,msm-cdsp-rm";
qcom,qos-latency-us = <100>;
qcom,qos-maxhold-ms = <20>;
qcom,compute-cx-limit-en;
qcom,compute-priority-mode = <2>;
#cooling-cells = <2>;
qcom,vtcm-paritions = <4>;
qcom,vtcm-partition-info = < 0 2048 0x1 >,
< 1 1024 0x2 >,
< 2 512 0x4 >,
< 3 512 0x4 >;
qcom,vtcm-partition-map = < 0 0 >,
< 1 0 >,
< 2 1 >,
< 30 2 >,
< 31 3 >;
};
msm_hvx_rm: qcom,msm_hvx_rm {
compatible = "qcom,msm-hvx-rm";
#cooling-cells = <2>;
};
};

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%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/cpuss_sleep_stats.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Technologies, Inc. cpuss sleep stats bindings
maintainers:
- Tushar Nimkar <tnimkar@qti.qualcomm.com>
description:
The low power mode counts and residency in the low power mode is maintained in
the hardware. The cpu sleep stats allows to read this configuration and display
the same.
This driver creates debugfs entry for all enabled lpm and provide LPM count and
Residency.
properties:
compatible:
enum:
- cpuss-sleep-stats
reg:
maxItems: 10
reguired:
- compatible
- reg
- reg-names
- num-cpus
example:
- |
cpuss-sleep-stats@18000054 {
compatible = "qcom,cpuss-sleep-stats";
reg = <0x18000054 0x4>, <0x18010054 0x4>, <0x18020054 0x4>,
<0x18030054 0x4>, <0x18040054 0x4>, <0x18050054 0x4>,
<0x18060054 0x4>, <0x18070054 0x4>, <0x18080098 0x4>,
<0x180C0000 0x10000>;
reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
"seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
"seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
"seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7",
"l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
num-cpus = <8>;
};

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* Data Capture and Compare (DCC)
DCC (Data Capture and Compare) is a DMA engine, which is used to save
configuration data or system memory contents during catastrophic failure or
SW trigger.
It can also perform CRC over the same configuration or memory space.
Required properties:
- compatible : name of the component used for driver matching, should be
"qcom,dcc" or "qcom,dcc-v2"
- reg : physical base address and length of the register set(s), SRAM and XPU
of the component.
- reg-names : names corresponding to each reg property value.
dcc-base: Base address for DCC configuration reg
dcc-ram-base: Start of HLOS address space in SRAM
dcc-xpu-base: Base address for XPU configuration reg
- dcc-ram-offset: Address offset from the start of the SRAM address space.
Optional properties:
- clocks: phandle reference to the parent clock.
- clock-names: Name of the clock that needs to be enabled for the HW to run.
Turned off when the subsystem is disabled.
- qcom,save-reg: boolean, To save dcc registers state in memory after dcc
enable and disable
- link-list subnode: Each link-list subnode represents a link-list configured by default.
It supports configure multiple link-list nodes.
link-list subnode properties:
- qcom,data-sink: string, To specify default data sink for dcc, should be one
of the following:
"atb" : To send captured data over ATB to a trace sink
"sram" : To save captured data in dcc internal SRAM.
- qcom,curr-link-list: int, To specify the link list to use for the default list.
- qcom,link-list: The values to be programmed into the default link list.
The enum values for DCC operations is defined in dt-bindings/soc/qcom,dcc_v2.h
The following gives basic structure to be used for each operation:
<DCC_operation addr val apb_bus>
val is to be interpreted based on what operation is to be performed.
Example:
dcc: dcc@4b3000 {
compatible = "qcom,dcc";
reg = <0x4b3000 0x1000>,
<0x4b4000 0x2000>,
<0x4b0000 0x1>;
reg-names = "dcc-base", "dcc-ram-base", "dcc-xpu-base";
clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>;
clock-names = "dcc_clk";
qcom,save-reg;
link_list_0 {
qcom,curr-link-list = <2>;
qcom,data-sink = "sram";
qcom,link-list = <DCC_READ 0x1740300 6 0>,
<DCC_READ 0x1620500 4 0>,
<DCC_READ 0x7840000 1 0>,
<DCC_READ 0x7841010 12 0>,
<DCC_READ 0x7842000 16 0>,
<DCC_READ 0x7842500 2 0>;
};
link_list_2 {
qcom,curr-link-list = <3>;
qcom,data-sink = "atb";
qcom,link-list = <DCC_READ 0x18220d14 3 0>,
<DCC_READ 0x18220d30 4 0>,
<DCC_READ 0x18220d44 4 0>,
<DCC_READ 0x18220d58 4 0>,
<DCC_READ 0x18220fb4 3 0>,
<DCC_READ 0x18220fd0 4 0>;
};
};

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Qualcomm Technologies, Inc.
Fairchild FSA4480 Device
This device is used for switching orientation of USB-C analog
and for display. It uses I2C communication to set the registers
to configure the switches inside the FSA4480 chip to change
orientation and also to set SBU1/SBU2 connections of USB-C.
Required properties:
- compatible: Should be "qcom,fsa4480-i2c".
- reg: I2C device address of the device
Example:
fsa4480: fsa4480@43 {
compatible = "qcom,fsa4480-i2c";
reg = <0x43>;
};

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* QTI Type-C Alternate Mode over GLINK bindings
The Qualcomm Technologies, Inc. Type-C Alternate (alt) Mode GLINK device
provides an interface for Type-C alternate mode clients to receive data such as
Pin Assignment Notifications from the Type-C stack running on a remote
subsystem (e.g. DSP) via the PMIC GLINK interface.
Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.txt
for information on the "qcom,pmic_glink" device used in the example below.
REQUIRED PROPERTIES:
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,altmode-glink"
- #altmode-cells:
Usage: required
Value type: <u32>
Definition: must be <1>
EXAMPLE of altmode node definition:
&soc {
qcom,pmic_glink {
...
altmode: qcom,altmode {
compatible = "qcom,altmode-glink";
#altmode-cells = <1>;
};
...
};
};
Altmode client bindings:
REQUIRED PROPERTIES:
- qcom,altmode-dev:
Usage: required
Value type: <phandle>
Definition: must be <phandle_to_altmode_node, N> where N is port index
EXAMPLE of altmode client node definition:
altmode-client {
...
qcom,altmode-dev = <&altmode 0>;
...
}

1
bindings/soc/qcom/qcom,aoss-qmp.txt
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@@ -22,6 +22,7 @@ power-domains.
"qcom,sm8150-aoss-qmp"
"qcom,sm8250-aoss-qmp"
"qcom,sm8350-aoss-qmp"
"qcom,waipio-aoss-qmp"
- reg:
Usage: required

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QTI battery glink debug binding
This binding describes the Qualcomm Technologies, Inc. battery glink debug
device. QTI battery glink debug device helps to get logs and debug information
by communicating with charger firmware running on the remote subsystem
(e.g. DSP) over PMIC Glink.
Refer to Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.txt for
information on "qcom,pmic_glink_log" device which is used in the example below.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,battery-debug"
= EXAMPLE
&soc {
qcom,pmic_glink_log {
...
qcom,battery_debug {
compatible = "qcom,battery-debug";
};
...
};
};

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QTI BWMON Driver
The QTI BWMON Driver monitors bandwidth counters that represent the read/write
traffic through various interconnects in the system and uses this data to vote
for DCVS HW (memory) frequencies. Each device represents a separate bandwidth
monitor present on the Qualcomm Technologies, Inc. (QTI) chipset. This driver
is a refactor of the bimc-bwmon driver that was previously developed.
Required properties:
- compatible: Must be "qcom,bwmon", "qcom,bwmon2", "qcom,bwmon3"
"qcom,bwmon4", or "qcom,bwmon5"
- reg: Pairs of physical base addresses and region sizes of
memory mapped registers.
- reg-names: Names of the bases for the above registers. Expected
bases are: "base", "global_base"
- interrupts: Lists the threshold IRQ.
- qcom,mport: The hardware master port that this device can monitor
- qcom,target-dev: A phandle to the QTI DCVS HW device node that this
node will be using for voting in the SLOW path.
- qcom,hw-timer-hz: Hardware sampling rate in Hz. This field must be
specified for "qcom,bwmon4"
Optional properties:
- qcom,byte-mid-match: Byte count MID match value
- qcom,byte-mid-mask: Byte count MID mask value
- qcom,count-unit: Number of bytes monitor counts in
Example:
bwmon_llcc: qcom,bwmon-llcc@90b6400 {
compatible = "qcom,bwmon4";
reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
};

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QTI charger ulog glink binding
This binding describes the Qualcomm Technologies, Inc. charger ulog glink
device. QTI charger ulog glink device helps to get ulogs from charging and
gauging stack by communicating with charger firmware running on the remote
subsystem (e.g. DSP) over PMIC Glink.
Refer to Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.txt for
information on "qcom,pmic_glink_log" device which is used in the example below.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,charger-ulog-glink"
= EXAMPLE
&soc {
qcom,pmic_glink_log {
...
qcom,battery_debug {
compatible = "qcom,charger-ulog-glink";
};
...
};
};

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QTI DCVS Fast Path Interface
The QTI DCVS Fast Path Interface utilizes the fast-path TCS hardware interface
provided by RPMH RSC. As such, this driver is a child node and client of an
RPMH RSC device that has a fast path TCS. The driver is intended to be used by
the QTI DCVS framework for DCVS_FAST_PATH voting on DDR and LLCC HW.
Required properties:
- compatible: Must be "qcom,dcvs-fp"
- qcom,ddr-bcm-name: DDR BCM name
- qcom,llcc-bcm-name: LLCC BCM name
Example:
apps_rsc: rsc@18200000 {
compatible = "qcom,rpmh-rsc";
dcvs_fp: qcom,dcvs-fp {
compatible = "qcom,dcvs-fp";
qcom,ddr-bcm-name = "MC3";
qcom,llcc-bcm-name = "SH8";
};
};

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QTI DCVS Driver
The QTI DCVS Driver manages several DCVS hardware types (e.g. DDR) and their
voting interfaces/paths (e.g. DCVS Fast Path) that are supported on various
Qualcomm Technologies, Inc. (QTI) chipsets.
Required structure:
An instance of qcom-dcvs must be described in three levels of device nodes.
The first level describes the parent node of the system, and the second level
describes a particular DCVS HW type that is supported while the third level
describes the various paths (i.e. voting interfaces) that this particular
DCVS HW type supports.
[First Level Nodes]
Required properties:
- compatible: Must be "qcom,dcvs"
[Second Level Nodes]
Required properties:
- compatible: Must be "qcom,dcvs-hw"
- qcom,dcvs-hw-type: DCVS HW type which should be DCVS_DDR, DCVS_LLCC,
DCVS_L3, or DCVS_DDRQOS depending on which dcvs hw
block this node is describing.
- qcom,bus-width: Bus width of hardware interface (in Bytes).
- qcom,freq-tbl: Array of frequencies or phandle to an array of
frequencies in units of kHz that this hardware
device supports. A phandle must be used in conjunction
with the optional "qcom,ddr-type" property to support
multiple DDR types. Required for all devices except
DCVS_L3.
- reg: Physical base address and region size of the memory
mapped registers containing the device's base address
for voting registers and frequency table. Required for
DCVS_L3 devices.
- reg-names: Name used for the above registers. Expected names are
"l3-base" and "l3tbl-base" respectively. Required for
DCVS_L3 devices.
Optional properties:
- qcom,ddr-type: Specifies the DDR type supported by the corresponding
"qcom,freq-tbl" property.
[Third Level Nodes]
Required properties:
- compatible: Must be "qcom,dcvs-path"
- qcom,dcvs-path-type: DCVS path type which should be DCVS_SLOW_PATH,
DCVS_FAST_PATH, or DCVS_PERCPU_PATH. The slow path
supports multiple clients and is not atomic context
friendly. The fast path is a single client lockless
path that utilizes the dcvs-fp interface. The percpu
path is a single client per-cpu lockless path that
utilizes per-cpu hardware voting registers.
- qcom,shared-offset: Physical address offset to the base address described in
the second level hw node that is used to configure the
vote for the DCVS_SLOW_PATH. Only required for DCVS_L3
child nodes that are using the DCVS_SLOW_PATH.
- qcom,percpu-offset: Array of physical address offsets to the base address
described in the second level hw node that is used to
configure the per-cpu votes for the DCVS_PERCPU_PATH.
The number of offsets must match the number of CPUs.
Only required for DCVS_L3 child nodes that are using the
DCVS_PERCPU_PATH.
- interconnects: Pairs of phandles and interconnect provider specificers
to denote the edge source and destination ports of the
desired interconnect path. Only required for DCVS_DDR
and DCVS_LLCC child nodes that are using the
DCVS_SLOW_PATH.
- qcom,fp-voter: A phandle to the QTI DCVS FP node which is used for
"fast path" LLCC and DDR voting. Only required for
DCVS_DDR and DCVS_LLCC child nodes that are using the
DCVS_FAST_PATH.
Example:
apps_rsc: rsc@18200000 {
compatible = "qcom,rpmh-rsc";
dcvs_fp: qcom,dcvs-fp {
compatible = "qcom,dcvs-fp";
qcom,ddr-bcm-name = "MC3";
qcom,llcc-bcm-name = "SH8";
};
};
ddr_freq_table: ddr-freq-table {
ddr4 {
qcom,ddr-type = <7>;
qcom,freq-tbl =
< 200000 >,
< 451000 >,
< 547000 >,
< 681000 >,
< 768000 >,
< 1017000 >,
< 1555000 >,
< 1708000 >,
< 2092000 >,
};
ddr5 {
qcom,ddr-type = <8>;
qcom,freq-tbl =
< 200000 >,
< 451000 >,
< 547000 >,
< 681000 >,
< 768000 >,
< 1017000 >,
< 1555000 >,
< 1708000 >,
< 2092000 >,
< 2736000 >,
< 3196000 >;
}
};
qcom_dcvs: qcom,dcvs {
compatible = "qcom,dcvs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <DCVS_DDR>;
qcom,bus-width = <4>;
qcom,freq-tbl = <&ddr_freq_table>;
ddr_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <DCVS_SLOW_PATH>;
interconnects = <&mc_virt MASTER_LLCC
&mc_virt SLAVE_EBI1>;
};
ddr_dcvs_fp: fp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <DCVS_FAST_PATH>;
qcom,fp-voter = <&dcvs_fp>;
};
};
qcom_l3_dcvs_hw: l3 {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <DCVS_L3>;
qcom,bus-width = <32>;
reg = <0x18590000 0x4000>, <0x18590100 0xa0>;
reg-names = "l3-base", "l3tbl-base";
l3_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <DCVS_SLOW_PATH>;
qcom,shared-offset = <0x0090>;
};
l3_dcvs_percpu: percpu {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <DCVS_PERCPU_PATH>;
qcom,percpu-offsets =
< 0x1090 >,
< 0x1094 >,
< 0x1098 >,
< 0x109C >,
< 0x2090 >,
< 0x2094 >,
< 0x2098 >,
< 0x3090 >;
};
};
};

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Qualcomm Technologies, Inc. G-Link Packet Driver (glinkpkt)
[Root level node]
Required properties:
-compatible : should be "qcom,glinkpkt"
[Second level nodes]
qcom,glinkpkt-channel-names
Required properties:
-qcom,glinkpkt-transport : the glinkpkt transport layer
-qcom,glinkpkt-edge : the remote subsystem name
-qcom,glinkpkt-ch-name : the glink channel name
-qcom,glinkpkt-dev-name : the glinkpkt device name
Example:
qcom,glink_pkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-transport = "smd_trans";
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-loopback-cntl {
qcom,glinkpkt-transport = "lloop";
qcom,glinkpkt-edge = "local";
qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
};
qcom,glinkpkt-loopback-data {
qcom,glinkpkt-transport = "lloop";
qcom,glinkpkt-edge = "local";
qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
qcom,glinkpkt-dev-name = "glink_pkt_loopback";
};
};

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%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/msm/guestvm-loaderpsci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Guest VM Loader
maintainers:
- Prakruthi Deepak Heragu <pheragu@quicinc.com>
- Murali Nalajala <mnalajal@quicinc.com>
properties:
compatible:
const: qcom,guestvm-loader
image_to_be_loaded:
$ref: /schemas/types.yaml#/definitions/string
required:
- compatible
- image_to_be_loaded
examples:
- |+
qcom,guestvm_loader {
compatible = "qcom,guestvm-loader";
image_to_be_loaded = "trustedvm";
};
...

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%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/soc/qcom/qcom,ipcc-self-ping-test.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: The document describes the device tree binding for testing the IPCC
maintainers:
- Raghavendra Rao Ananta <rananta@quicinc.com>
description: |+
For details on the IPCC driver, please see qcom,ipcc.txt
properties:
compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,ipcc-self-ping"
interrupts-extended:
Usage: required
Value type: <prop-encoded-array>
Definition: One entry specifying the phandle to the IPCC protocol, the APPS'
client-id, signal-id and IRQ type.
mboxes:
Usage: required
Value type: <prop-encoded-array>
Definition: One entry specifying the phandle to the IPCC protocol, the APPS'
client-id and the signal-id (same as interrupts-extended).
example:
- |
ipcc_self_ping: ipcc-self-ping {
compatible = "qcom,ipcc-self-ping";
interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS
IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>;
};

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%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,logbuf_vendor_hooks.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Technologies, Inc. Logbuf Vendor Hooks Binding
description: |
Logbuf Vendor Hook driver is used to register logbuf specific vendor hooks
with core kernel to copy initial kernel log to a separate buffer even though
kernel log gets overflowed.
properties:
compatible:
items:
- const: qcom,logbuf-vendor-hooks
required:
- compatible
examples:
- |
logbuf: qcom,logbuf-vendor-hooks {
compatible = "qcom,logbuf-vendor-hooks";
};

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QTI Memlat Driver
The QTI Memlat Driver monitors CPU performance counters to identify memory
latency bound workloads and votes for DCVS HW (memory) frequencies based on
the workload characteristics. This driver is a refactor of the arm-memlat-mon
driver that was previously developed.
Required structure:
An instance of qcom-memlat must be described in three levels of device nodes.
The first level describes the parent node. The second level describes a memlat
group which manages voting for a particular DCVS HW device (e.g. DDR). The third
level describes a memlat monitor ("mon") which comprises of a list of CPUs whose
configured performance counters are used to vote for a DCVS HW frequency for the
memlat group that it is part of.
[First Level Nodes]
Required properties:
- compatible: Must be "qcom,memlat"
Optional properties:
- qcom,cyc-ev: The cycle count event that this driver monitors.
Defaults to 0x11 if not specified.
- qcom,inst-ev: The instruction count event that this driver monitors.
Defaults to 0x08 if not specified.
- qcom,stall-ev: The stall cycle event that this driver monitors.
Assumes 100% stall if not specified.
[Second Level Nodes]
Required properties:
- compatible: Must be "qcom,memlat-grp"
- qcom,target-dev: A phandle to the QTI DCVS HW device node that this
node will be using for voting.
- qcom,miss-ev: The cache miss event that this memlat group uses to
measure memory latency sensitivity to this DCVS HW.
- qcom,sampling-path: A phandle to the QTI DCVS PATH device node that the
memlat sampling algorithm will use for voting. This
property or the qcom,threadlat-path property is
required.
- qcom,threadlat-path: A phandle to the QTI DCVS PATH device node that the
threadlat algorithm will use for voting. This property
or the qcom,sampling-path property is required.
Optional properties:
- qcom,access-ev: The cache access event that this driver optionally
monitors to calculate writeback percentage.
- qcom,wb-ev: The cache writeback event that this driver optionally
monitors to calculate writeback percentage.
[Third Level Nodes]
Required properties:
- compiatible: Must be "qcom,memlat-mon"
- qcom,cpulist: List of CPU phandles to be monitored by this mon.
- qcom,cpufreq-memfreq-tbl: A mapping table of cpu frequency to a memory
(i.e. DCVS HW) frequency (both in units of kHz).
A phandle that contains this property may be
provided instead (to share tables across nodes).
A phandle must be used in conjunction with the
optional "qcom,ddr-type" property to support
multiple DDR types.
- qcom,sampling-enabled: Used to determine if this mon should be used by
the memlat sampling algorithm. This property or
the qcom,threadlat-enabled property is required.
- qcom,threadlat-enabled: Used to determine if this mon should be used by
the threadlat algorithm. This property or the
qcom,sampling-enabled property is required.
Optional properties:
- qcom,compute-mon: Used to configure mon as a "compute" mon which
means it monitors compute bound workloads.
- qcom,ddr-type: Specifies the DDR type supported by the
corresponding "qcom,cpufreq-memfreq-tbl" prop.
Example:
qcom_dcvs: qcom,dcvs {
compatible = "qcom,dcvs";
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
ddr_dcvs_fp: fp {
compatible = "qcom,dcvs-path";
};
};
};
silver_ddr_tbl: qcom,silver-ddr-tbl {
ddr4-tbl {
qcom,ddr-type = <7>;
qcom,cpufreq-memfreq-tbl =
< 300000 200000 >,
< 691200 451000 >,
< 1190400 547000 >,
< 1459200 768000 >,
< 1900800 1017000 >;
};
ddr5-tbl {
qcom,ddr-type = <8>;
qcom,cpufreq-memfreq-tbl =
< 300000 200000 >,
< 691200 451000 >,
< 1190400 547000 >,
< 1459200 768000 >,
< 1900800 1555000 >;
}
};
qcom_memlat: qcom,memlat {
compatible = "qcom,memlat";
memlat_ddr: ddr {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
qcom,sampling-path = <&ddr_dcvs_fp>;
qcom,miss-ev = <0x1000>;
silver_ddr_lat: silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cpufreq-memfreq-tbl = <&silver_ddr_tbl>;
qcom,sampling-enabled;
};
};
};

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bindings/soc/qcom/qcom,microdump_modem.txt Normal file
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QTI Microdump Collector Driver
This driver collects crash data from SMEM whenever modem subsytem
crashes and stores it under /devcd to expose to user space.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,microdump_modem"
= EXAMPLE
&soc {
microdump_modem {
compatible = "qcom,microdump_modem";
};
};

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%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/soc/qcom/qcom,msm-eud.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies Inc Embedded USB Debugger (EUD)
maintainers:
- Prakruthi Deepak Heragu <pheragu@codeaurora.org>
description: |+
The EUD (Embedded USB Debugger) is a mini-USB hub implemented
on chip to support the USB-based debug and trace capabilities.
properties:
compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,msm-eud"
reg:
Usage: required
Value type: <prop-encoded-array>
Definition: address and size of EUD register space
reg-names:
Usage: required
Value type: <string>
Definition: Must be "eud_base"
interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: Interrupt number
interrupt-names:
Usage: required
Value type: <string>
Definition: Must be "eud_irq"
reg-names:
Usage: optional
Value type: <string>
Definition: Must be "eud_mode_mgr2" for secure eud
qcom,secure-eud-en:
Usage: optional to enable secure eud
qcom,eud-clock-vote-req:
Usage: optional to enable clock voting from eud
example:
- |
eud: qcom,msm-eud@88e0000 {
compatible = "qcom,msm-eud";
interrupt-names = "eud_irq";
interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x88e0000 0x4000>;
reg-names = "eud_base";
};
client-example:
- |
usb3 {
extcon = <&eud>;
};
...

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QTI PMIC Glink binding
This binding describes the Qualcomm Technologies, Inc. PMIC GLink device. PMIC
Glink handles the communication between different clients (e.g. battery charger,
UCSI PPM) on the Application processor and charger firmware running on the
remote subsystem (e.g. DSP) over Glink channel.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,pmic-glink"
- qcom,pmic-glink-channel:
Usage: required
Value type: <stringlist>
Definition: should be same as Glink channel name under rpmsg device.
- qcom,subsys-name:
Usage: optional
Value type: <stringlist>
Definition: should be the subsystem name for which subsystem restart
notifications should be handled and state transitions be
sent to the clients.
- qcom,protection-domain:
Usage: optional
Value type: <stringlist>
Definition: should be the protection domain service name and path name
for which notifications should be handled and state
transitions be sent to the clients.
Refer to Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt for
information on rpmsg device ("qcom,pmic_glink_rpmsg" used in the example below)
that needs to be specified under a glink device.
= SUBNODE
Each subnode specifies a client of PMIC Glink device that will be instantiated
after the PMIC Glink device initializes.
= EXAMPLE
= PMIC Glink rpmsg device
&glink_adsp {
...
qcom,pmic_glink_rpmsg {
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
};
...
};
= PMIC Glink device with child subnodes
&soc {
qcom,pmic_glink {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
qcom,subsys-name = "adsp";
qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
qcom,batt_chg {
compatible = "qcom,battery-charger";
};
qcom,ucsi_ppm {
compatible = "qcom,ucsi-ppm";
};
};
};

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Qualcomm Technologies, Inc. PMIC PON Log
Certain Qualcomm Technologies, Inc. PMIC devices capture power-on, power-off,
and fault information in a binary log found within SDAM peripherals. The PMIC
PON Log device accesses this log and parses it into a human readable format.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,pmic-pon-log"
- nvmem:
Usage: required
Value type: <phandle-list>
Definition: phandle of the PMIC nvmem device containing the PON log
- nvmem-names:
Usage: required
Value type: <stringlist>
Definition: must be "pon_log"
Example:
pmic-pon-log {
compatible = "qcom,pmic-pon-log";
nvmem = <&pmk8350_sdam_5>;
nvmem-names = "pon_log";
};

36
bindings/soc/qcom/qcom,pmu.txt Normal file
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QTI PMU Driver
This driver provides an interface to request for per-CPU performance counters
that are available on some Qualcomm Technologies, Inc. (QTI) chipsets.
Required properties:
- compatible: Must be "qcom,pmu"
- qcom,long-counter Specify if the pmu counters are long (64 bit) counters.
- qcom,pmu-events-tbl: A list of the pmu events to be configured on the cpus.
The first column in the table contains the event id and
the second column contains a bit mask (cpumask) of
cpus for which the event should be configured on.
The third column contains the AMU id for events that are
present as part of AMU counters. The list of ids can be
found in enum amu_counters (include/soc/qcom/pmu_lib.h).
0xFF represents an invalid id.
The fourth column represents the index in enum
cpucp_ev_idx (include/linux/scmi_pmu.h), which is a
shared enum between hlos and cpucp. This helps
maintain the sequence of events when pmu hardware ids
or cached counts are shared between hlos and cpucp.
0xFF represents an invalid index, which means this event
is not supposed to be shared between hlos and cpucp.
Example:
qcom,pmu {
compatible = "qcom,pmu";
qcom,long-counter;
qcom,pmu-events-tbl =
< 0x0008 0xFF 0x02 0x02 >,
< 0x0011 0xFF 0x01 0x01 >,
< 0x0017 0xFF 0xFF 0x04 >,
< 0x002A 0xFF 0xFF 0xFF >,
< 0x1000 0xFF 0xFF 0xFF >;
};

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%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/soc/qcom/qcom,rimps-log.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Rimps Logging
description: |
RIMPS logging is a device that uses mailbox to collect the logs
generated from rimps, and dump them into a dedicated log buffer
through ipc_logging framework.
An instance of rimps-log should have the mailbox controller phandle and
addresses of log buffer set aside for this purpose.
properties:
compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,rimps-log"
example:
- |
rimps_log: qcom,rimps_log@fd04780 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,rimps-log";
reg = <0x0fd04580 0x200>,
<0x0fd04780 0x200>;
mboxes = <&rimps 1>;
};

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