Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: msm: Add i2c support on divar

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Adds support of GENI based I2C.

Change-Id: I3bf8ce90934d5f4db1e1eb879b7a3a252b626474
This commit is contained in:
kamasali
2022-08-08 19:06:33 +05:30
parent 4aae06b2f1
commit 2cb4fa49a3
1 changed files with 39 additions and 2 deletions
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41
qcom/bengal-qupv3.dtsi
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@@ -1,4 +1,3 @@
&soc {
/* GPI Instance */
@@ -35,6 +34,10 @@
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
iommus = <&apps_smmu 0xE3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
ranges;
status = "ok";
@@ -46,10 +49,13 @@
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_2uart_active>;
pinctrl-1 = <&qupv3_se4_2uart_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -61,6 +67,13 @@
reg-names = "se_phys";
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
dmas = <&gpi_dma0 0 1 2 64 0>,
<&gpi_dma0 1 1 2 64 0>;
dma-names = "tx", "rx";
pinctrl-names = "default", "active", "sleep";
interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 11 IRQ_TYPE_LEVEL_HIGH>;
@@ -84,6 +97,10 @@
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
dmas = <&gpi_dma0 0 0 3 64 0>,
<&gpi_dma0 1 0 3 64 0>;
dma-names = "tx", "rx";
@@ -103,6 +120,10 @@
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
dmas = <&gpi_dma0 0 1 3 64 0>,
<&gpi_dma0 1 1 3 64 0>;
dma-names = "tx", "rx";
@@ -122,6 +143,10 @@
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
dmas = <&gpi_dma0 0 2 3 64 0>,
<&gpi_dma0 1 2 3 64 0>;
dma-names = "tx", "rx";
@@ -142,6 +167,10 @@
reg-names = "se_phys";
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_spi_active>;
pinctrl-1 = <&qupv3_se0_spi_sleep>;
@@ -163,6 +192,10 @@
reg-names = "se_phys";
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
@@ -184,6 +217,10 @@
reg-names = "se_phys";
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_spi_active>;
pinctrl-1 = <&qupv3_se5_spi_sleep>;