Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add eMMC and SD card support for khaje"

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qctecmdr
2022-07-06 23:53:37 -07:00
committed by Gerrit - the friendly Code Review server
parent 03b3bc0b12 0bfcd7becf
commit 2d76627a99
2 changed files with 30 additions and 28 deletions
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6
qcom/khaje-idp.dtsi
View File

@@ -192,12 +192,11 @@
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 325000>;
pinctrl-names = "active", "sleep";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
&sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
&sdc1_rclk_off>;
status = "ok";
};
@@ -214,12 +213,11 @@
qcom,vdd-io-bias-voltage-level = <1256000 1256000>;
qcom,vdd-io-bias-current-level = <0 6000>;
pinctrl-names = "active", "sleep";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
status = "ok";
};

52
qcom/khaje.dtsi
View File

@@ -25,8 +25,8 @@
};
aliases {
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
mmc0 = &sdhc_1; /* SDC1 eMMC slot */
mmc1 = &sdhc_2; /* SDC2 SD Card slot */
ufshc1 = &ufshc_mem; /* Embedded UFS slot */
serial0 = &qupv3_se4_2uart;
hsuart0 = &qupv3_se3_4uart;
@@ -2239,35 +2239,39 @@
compatible = "qcom,sdhci-msm-v5";
reg = <0x4744000 0x1000>, <0x4745000 0x1000>,
<0x4748000 0x8000>;
reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
reg-names = "hc", "cqhci", "cqhci_ice";
interrupts-extended = <&intc GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 19 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "hc_irq", "pwr_irq", "tb_trig_irq";
qcom,bus-width = <8>;
qcom,large-address-bus;
bus-width = <8>;
non-removable;
supports-cqe;
qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
192000000 384000000>;
qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
no-sd;
no-sdio;
qcom,restore-after-cx-collapse;
qcom,devfreq,freq-table = <50000000 200000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
qcom,scaling-lower-bus-speed-mode = "DDR52";
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
/* PM QoS */
qcom,pm-qos-irq-type = "affine_irq";
qcom,pm-qos-irq-latency = <26 26>;
qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
qcom,pm-qos-cmdq-latency-us = <26 26>, <26 26>;
qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface_clk", "core_clk", "ice_core_clk";
clock-names = "iface", "core", "ice_core";
qcom,ice-clk-rates = <300000000 100000000>;
@@ -2277,45 +2281,45 @@
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>;
qcom,nonremovable;
iommus = <&apps_smmu 0xC0 0x0>;
qcom,iommu-dma = "fastmap";
status = "disabled";
};
sdhc_2: sdhci@4784000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x4784000 0x1000>;
reg-names = "hc_mem";
reg-names = "hc";
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <4>;
qcom,large-address-bus;
qcom,clk-rates = <400000 20000000 25000000
50000000 100000000 202000000>;
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
"SDR104";
qcom,devfreq,freq-table = <50000000 202000000>;
bus-width = <4>;
no-sdio;
no-mmc;
qcom,restore-after-cx-collapse;
/* PM QoS */
qcom,pm-qos-irq-type = "affine_irq";
qcom,pm-qos-irq-latency = <26 26>;
qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface_clk", "core_clk";
clock-names = "iface", "core";
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
qcom,vbias-skip-wa;
iommus = <&apps_smmu 0xA0 0x0>;
qcom,iommu-dma = "fastmap";
status = "disabled";
};