Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add pipe_div2_clk for PCIe1 and PCIe2 for sdxpinn"

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qctecmdr
2022-09-06 01:13:38 -07:00
committed by Gerrit - the friendly Code Review server
parent 6bc9609b49 10919eb1c2
commit 2d92322ab3
1 changed files with 16 additions and 14 deletions
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30
qcom/sdxpinn-pcie.dtsi
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@@ -36,8 +36,8 @@
msi-parent = <&pcie0_msi>;
perst-gpio = <&tlmm 44 0>;
wake-gpio = <&tlmm 42 0>;
perst-gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>;
wake-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_clkreq_default
&pcie0_perst_default
@@ -176,8 +176,8 @@
msi-parent = <&pcie1_msi>;
perst-gpio = <&tlmm 125 0>;
wake-gpio = <&tlmm 123 0>;
perst-gpio = <&tlmm 125 GPIO_ACTIVE_HIGH>;
wake-gpio = <&tlmm 123 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie1_clkreq_default
&pcie1_perst_default
@@ -223,6 +223,7 @@
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_CLKREF_EN>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_1_PIPE_DIV2_CLK>,
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
<&pcie_1_pipe_clk>;
@@ -231,12 +232,12 @@
"pcie_aux_clk", "pcie_cfg_ahb_clk",
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
"pcie_phy_refgen_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src";
"pcie_pipe_div2_clk", "pcie_phy_refgen_clk",
"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <100000000>, <0>, <0>;
<0>, <0>, <0>, <100000000>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
<0>, <0>, <0>;
<0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_1_BCR>,
<&gcc GCC_PCIE_1_PHY_BCR>;
@@ -312,8 +313,8 @@
msi-parent = <&pcie2_msi>;
perst-gpio = <&tlmm 122 0>;
wake-gpio = <&tlmm 120 0>;
perst-gpio = <&tlmm 122 GPIO_ACTIVE_HIGH>;
wake-gpio = <&tlmm 120 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie2_clkreq_default
&pcie2_perst_default
@@ -359,6 +360,7 @@
<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
<&gcc GCC_PCIE_2_CLKREF_EN>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_2_PIPE_DIV2_CLK>,
<&gcc GCC_PCIE_2_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_2_PIPE_CLK_SRC>,
<&pcie_2_pipe_clk>;
@@ -367,12 +369,12 @@
"pcie_aux_clk", "pcie_cfg_ahb_clk",
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
"pcie_phy_refgen_clk","pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src";
"pcie_pipe_div2_clk", "pcie_phy_refgen_clk",
"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <100000000>, <0>, <0>;
<0>, <0>, <0>, <100000000>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
<0>, <0>, <0>;
<0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_2_BCR>,
<&gcc GCC_PCIE_2_PHY_BCR>;