Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Enable DCVS for monaco"

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qctecmdr
2022-09-16 06:29:43 -07:00
committed by Gerrit - the friendly Code Review server
parent 71ab9f7dd8 05ed9f3284
commit 2ef21ae72f
1 changed files with 87 additions and 0 deletions
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87
qcom/monaco.dtsi
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@@ -1673,6 +1673,93 @@
};
msm_gpu: qcom,kgsl-3d0@5900000 { };
qcom_pmu: qcom,pmu {
compatible = "qcom,pmu";
qcom,pmu-events-tbl =
< 0x0008 0x0F 0xFF 0xFF >,
< 0x0011 0x0F 0xFF 0xFF >,
< 0x0017 0x0F 0xFF 0xFF >;
};
ddr_freq_table: ddr-freq-table {
qcom,freq-tbl =
< 200000 >,
< 300000 >,
< 451000 >,
< 547000 >,
< 681000 >,
< 768000 >,
< 1017000 >,
< 1353000 >,
< 1555000 >,
< 1804000 >,
< 2029000 >;
};
qcom_dcvs: qcom,dcvs {
compatible = "qcom,dcvs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <0>;
qcom,bus-width = <4>; //CHECK
qcom,freq-tbl = <&ddr_freq_table>;
ddr_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
};
};
};
bwmon_ddr: qcom,bwmon-ddr@4520300 {
compatible = "qcom,bwmon4";
reg = <0x4520300 0x300>, <0x4520200 0x200 >;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
qcom,count-unit = <0x10000>;
};
qcom_memlat: qcom,memlat {
compatible = "qcom,memlat";
ddr {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
qcom,sampling-path = <&ddr_dcvs_sp>;
qcom,miss-ev = <0x17>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 614400 547000 >,
< 864000 681000 >,
< 1363200 1353000 >,
< 1708800 1804000 >;
};
silver-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,sampling-enabled;
qcom,compute-mon;
qcom,cpufreq-memfreq-tbl =
< 614400 200000 >,
< 864000 547000 >,
< 1363200 681000 >,
< 1708800 1353000 >;
};
};
};
};
#include "pm5100.dtsi"