mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
Merge "ARM: dts: msm: Add the APPS SMMU device for Lemans"
This commit is contained in:
qctecmdr
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Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
commit
4fc539e318
@@ -959,6 +959,8 @@
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#include "lemans-4pmic-regulators.dtsi"
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#include "lemans-gdsc.dtsi"
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#include "lemans-pinctrl.dtsi"
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#include "msm-arm-smmu-lemans.dtsi"
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&cam_cc_titan_top_gdsc {
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clocks = <&gcc GCC_CAMERA_AHB_CLK>;
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@@ -1115,5 +1117,4 @@
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status = "ok";
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};
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#include "lemans-pinctrl.dtsi"
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#include "lemans-debug.dtsi"
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311
qcom/msm-arm-smmu-lemans.dtsi
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311
qcom/msm-arm-smmu-lemans.dtsi
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@@ -0,0 +1,311 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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apps_smmu: apps-smmu@15000000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x15000000 0x100000>,
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<0x15182000 0x28>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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#global-interrupts = <2>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
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anoc_1_tbu: anoc_1_tbu@15189000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15189000 0x1000>,
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<0x15182200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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qcom,iova-width = <36>;
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};
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anoc_2_tbu: anoc_2_tbu@15191000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15191000 0x1000>,
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<0x15182208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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qcom,iova-width = <36>;
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};
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mnoc_sf_0_tbu: mnoc_sf_0_tbu@15199000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15199000 0x1000>,
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<0x15182210 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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qcom,iova-width = <36>;
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};
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mnoc_sf_1_tbu: mnoc_sf_1_tbu@0x151a1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151A1000 0x1000>,
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<0x15182218 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0xC00 0x400>;
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qcom,iova-width = <36>;
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};
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mdp_00_tbu: mdp_00_tbu@0x151a9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151A9000 0x1000>,
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<0x15182220 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1000 0x400>;
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qcom,iova-width = <32>;
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};
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mdp_01_tbu: mdp_01_tbu@0x151b1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151B1000 0x1000>,
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<0x15182228 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1400 0x400>;
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qcom,iova-width = <32>;
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};
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mdp_10_tbu: mdp_10_tbu@0x151b9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151B9000 0x1000>,
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<0x15182230 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1800 0x400>;
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qcom,iova-width = <32>;
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};
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mdp_11_tbu: mdp_11_tbu@151c1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151C1000 0x1000>,
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< 0x15182238 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1C00 0x400>;
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qcom,iova-width = <32>;
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};
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nsp_00_tbu: nsp_00_tbu@151c9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151C9000 0x1000>,
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< 0x15182240 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2000 0x400>;
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qcom,iova-width = <32>;
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};
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nsp_01_tbu: nsp_01_tbu@151d1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151D1000 0x1000>,
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< 0x15182248 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2400 0x400>;
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qcom,iova-width = <32>;
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};
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nsp_10_tbu: nsp_10_tbu@151d9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151D9000 0x1000>,
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< 0x15182250 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2800 0x400>;
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qcom,iova-width = <32>;
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};
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nsp_11_tbu: nsp_11_tbu@151e1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151E1000 0x1000>,
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< 0x15182258 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2C00 0x400>;
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qcom,iova-width = <32>;
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};
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lpass_tbu: lpass_tbu@151e9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151E9000 0x1000>,
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< 0x15182260 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x3000 0x400>;
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qcom,iova-width = <32>;
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};
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cam_tbu: cam_tbu@151f1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151F1000 0x1000>,
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< 0x15182268 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x3400 0x400>;
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qcom,iova-width = <32>;
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};
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gpdsp_sail_ss_tbu: gpdsp_sail_ss_tbu@151f9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151F9000 0x1000>,
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< 0x15182270 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x3800 0x400>;
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qcom,iova-width = <32>;
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};
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};
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iommu_test_device {
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compatible = "qcom,iommu-debug-test";
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usecase0_apps {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x580 0>;
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};
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usecase1_apps_fastmap {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x580 0>;
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qcom,iommu-dma = "fastmap";
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};
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usecase2_apps_atomic {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x580 0>;
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qcom,iommu-dma = "atomic";
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};
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usecase3_apps_dma {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x581 0>;
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dma-coherent;
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};
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};
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};
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Reference in New Issue
Block a user