Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
2
0
Fork 0
mirror of https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees synced 2026-02-01 09:04:24 +00:00
Code Issues Packages Projects Releases Wiki Activity

ARM: dts: msm: Add QMP PHY node for Cinder

Browse Source 
Add QMP phy node for SS USB support in Cinder.
Added the voltage regulators in RU & DU DT files.

Change-Id: Ie1c83f29a523333834c0e6cccf9b33a19f38574a
This commit is contained in:
Prashanth K
2022-04-19 12:29:11 +05:30
committed by Gerrit - the friendly Code Review server
parent 1b0cd12661
commit 4fd071c02b
3 changed files with 145 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
qcom/cinder-du.dtsi
View File

@@ -155,4 +155,11 @@
vdda33-supply = <&L2A>;
qcom,vdd-voltage-level = <0 888000 920000>;
};
usb_qmp_phy {
vdd-supply = <&L8A>;
qcom,vdd-voltage-level = <0 888000 920000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&L3A>;
};
};

7
qcom/cinder-ru.dtsi
View File

@@ -150,4 +150,11 @@
vdda33-supply = <&L2A>;
qcom,vdd-voltage-level = <0 880000 920000>;
};
usb_qmp_phy {
vdd-supply = <&L5A>;
qcom,vdd-voltage-level = <0 880000 920000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&L3A>;
};
};

132
qcom/cinder-usb.dtsi
View File

@@ -1,4 +1,5 @@
#include <dt-bindings/clock/qcom,gcc-cinder.h>
#include <dt-bindings/phy/qcom,usb3-4nm-qmp-uni.h>
&soc {
usb0: ssusb@a600000 {
@@ -48,7 +49,7 @@
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
dma-coherent;
usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
usb-phy = <&usb2_phy0>, <&usb_qmp_phy>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
@@ -78,6 +79,135 @@
reset-names = "phy_reset";
};
/* USB port related QMP USB UNI PHY */
usb_qmp_phy: ssphy@88e5000 {
compatible = "qcom,usb-ssphy-qmp-v2";
reg = <0x88e5000 0x2000>,
<0x88E528C 0x4>;
reg-names = "qmp_phy_base",
"pcs_clamp_enable_reg";
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB2_CLKREF_EN>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
"pipe_clk_ext_src", "ref_clk_src",
"ref_clk", "com_aux_clk";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
reset-names = "phy_reset", "phy_phy_reset";
qcom,qmp-phy-init-seq =
/* <reg_offset, value, delay> */
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24 0
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64 0
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00 0
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E 0
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05 0
USB3_UNI_QSERDES_RX_GM_CAL 0x00 0
USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0
USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5 0
USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0
USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F 0
USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0
USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
USB3_UNI_PCS_RX_SIGDET_LVL 0xAA 0
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C 0
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
USB3_UNI_PCS_CDR_RESET_TIME 0x0A 0
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
USB3_UNI_PCS_EQ_CONFIG1 0x4B 0
USB3_UNI_PCS_EQ_CONFIG5 0x10 0
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
0xffffffff 0xffffffff 0x00>;
qcom,qmp-phy-reg-offset =
<USB3_UNI_PCS_PCS_STATUS1
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
USB3_UNI_PCS_POWER_DOWN_CONTROL
USB3_UNI_PCS_SW_RESET
USB3_UNI_PCS_START_CONTROL>;
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};