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https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
msm-vidc: Compile video component devicetree as overlay
Moved devicetree of video component to VENDOR image. Change-Id: Iaa4323cfd9221b95fcc874c1c0ebb30415563f9c Signed-off-by: Karthikeyan Periasamy <kperiasa@quicinc.com>
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6
Kbuild
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6
Kbuild
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dtbo-y += waipio-vidc.dtbo
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always-y := $(dtb-y) $(dtbo-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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9
Makefile
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9
Makefile
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KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
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all: dtbs
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
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%:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
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15
waipio-vidc.dts
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15
waipio-vidc.dts
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-waipio.h>
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#include <dt-bindings/interconnect/qcom,waipio.h>
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#include <dt-bindings/clock/qcom,videocc-waipio.h>
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#include "waipio-vidc.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. waipio v1 SoC";
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compatible = "qcom,waipio";
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qcom,msm-id = <457 0x10000>;
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qcom,board-id = <0 0>;
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};
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104
waipio-vidc.dtsi
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104
waipio-vidc.dtsi
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&soc {
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msm_vidc: qcom,vidc@aa00000 {
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compatible = "qcom,msm-vidc", "qcom,waipio-vidc";
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status = "disable";
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reg = <0x0aa00000 0x00100000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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/* IOMMU Config */
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#address-cells = <1>;
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#size-cells = <1>;
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/* LLCC Cache */
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cache-slice-names = "vidsc0";
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/* Supply */
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iris-ctl-supply = <&video_cc_mvs0c_gdsc>;
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vcodec-supply = <&video_cc_mvs0_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"core_clk", "vcodec_clk";
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clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
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<&clock_videocc VIDEO_CC_MVS0C_CLK>,
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<&clock_videocc VIDEO_CC_MVS0_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi0",
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"core_clk", "vcodec_clk";
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/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
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qcom,clock-configs = <0x0 0x1 0x1>;
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qcom,allowed-clock-rates = <239999999 338000000
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366000000 444000000>;
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resets = <&clock_gcc GCC_VIDEO_AXI0_CLK_ARES>;
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reset-names = "video_axi_reset";
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qcom,reg-presets = <0xB0088 0x0 0x11>;
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/* Video Firmware ELF image name */
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vidc,firmware-name = "vpu20_4v";
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/* Bus Interconnects */
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interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc";
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_VENUS_CFG>,
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<&mc_virt MASTER_LLCC
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&mc_virt SLAVE_EBI1>,
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<&mmss_noc MASTER_VIDEO_P0
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&gem_noc SLAVE_LLCC>;
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/* Bus BW range (low, high) for each bus */
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qcom,bus-range-kbps = <1000 1000
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1000 15000000
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1000 15000000>;
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_ns";
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iommus = <&apps_smmu 0x2100 0x0400>;
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qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x25800000 0xba800000>;
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dma-coherent-hint-cached;
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};
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secure_non_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_non_pixel";
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iommus = <&apps_smmu 0x2104 0x0400>;
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qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */
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buffer-types = <0x480>;
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virtual-addr-pool = <0x01000000 0x24800000>;
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qcom,secure-context-bank;
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};
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secure_bitstream_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_bitstream";
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iommus = <&apps_smmu 0x2101 0x0404>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
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buffer-types = <0x241>;
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virtual-addr-pool = <0x00500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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secure_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_pixel";
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iommus = <&apps_smmu 0x2103 0x0400>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
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buffer-types = <0x106>;
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virtual-addr-pool = <0x00500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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};
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};
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