mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add QUP node for SA8195 target"
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qctecmdr
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Gerrit - the friendly Code Review server
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5b5a3138f2
1071
qcom/sa8195-qupv3.dtsi
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1071
qcom/sa8195-qupv3.dtsi
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File diff suppressed because it is too large
Load Diff
117
qcom/sa8195-ssc-qupv3.dtsi
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117
qcom/sa8195-ssc-qupv3.dtsi
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@@ -0,0 +1,117 @@
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&soc {
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/* QUPv3_3 wrapper instance */
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qupv3_3: qcom,qupv3_3_geni_se@26c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x26c0000 0x6000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&scc SCC_QUPV3_M_HCLK_CLK>,
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<&scc SCC_QUPV3_S_HCLK_CLK>;
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iommus = <&apps_smmu 0x4e3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok";
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qupv3_se20_i2c: i2c@2680000 {
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compatible = "qcom,i2c-geni";
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reg = <0x2680000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se20_i2c_active>;
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pinctrl-1 = <&qupv3_se20_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se21_i2c: i2c@2684000 {
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compatible = "qcom,i2c-geni";
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reg = <0x2684000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE1_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se21_i2c_active>;
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pinctrl-1 = <&qupv3_se21_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se21_spi: spi@2684000 {
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compatible = "qcom,spi-geni";
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reg = <0x2684000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE1_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se21_spi_active>;
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pinctrl-1 = <&qupv3_se21_spi_sleep>;
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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qupv3_se22_i2c: i2c@2688000 {
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compatible = "qcom,i2c-geni";
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reg = <0x2688000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se22_i2c_active>;
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pinctrl-1 = <&qupv3_se22_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se22_spi: spi@2688000 {
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compatible = "qcom,spi-geni";
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reg = <0x2688000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
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<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se22_spi_active>;
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pinctrl-1 = <&qupv3_se22_spi_sleep>;
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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};
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};
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@@ -1,5 +1 @@
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#include <dt-bindings/gpio/gpio.h>
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&uart2 {
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status = "ok";
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};
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File diff suppressed because it is too large
Load Diff
@@ -26,8 +26,8 @@
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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serial0 = &uart2;
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ufshc1 = &ufshc_mem; /* Embedded UFS slot */
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serial0 = &qupv3_se12_2uart;
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};
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cpus {
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@@ -966,21 +966,6 @@
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qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
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};
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qupv3_id_1: geniqup@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x00ac0000 0x6000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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uart2: serial@a90000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x00a90000 0x4000>;
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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thermal_zones: thermal-zones {
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};
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@@ -1832,3 +1817,9 @@
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status = "ok";
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};
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#include "sa8195-thermal.dtsi"
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#include "sa8195-qupv3.dtsi"
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#include "sa8195-ssc-qupv3.dtsi"
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&qupv3_se12_2uart {
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status = "ok";
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};
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