Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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bindings: Documentation: add mmrm dt documentation for dp

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Add documentation for device tree properties
that enable mmrm feature in dp driver.

Change-Id: I8ec0c5f700d9cd0efdf6ab2484169873b532ddad
Signed-off-by: Christina Oliveira <coliveir@quicinc.com>
This commit is contained in:
Christina Oliveira
2021-02-03 16:26:20 -08:00
parent 04a2f36c09
commit 705f44e67c
1 changed files with 12 additions and 5 deletions
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17
bindings/sde-dp.txt
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@@ -22,8 +22,8 @@ DP Controller: Required properties:
- clocks: Clocks required for Display Port operation.
- clock-names: Names of the clocks corresponding to handles. Following clocks are required:
"core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk",
"link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",
"strm0_pixel_clk", "strm1_pixel_clk".
"link_clk_src", "link_iface_clk", "pixel_clk_rcg", "pixel_parent",
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk".
- vdda-1p2-supply: phandle to vdda 1.2V regulator node.
- vdda-0p9-supply: phandle to vdda 0.9V regulator node.
- interrupt-parent phandle to the interrupt parent device node.
@@ -101,6 +101,11 @@ msm_ext_disp is a device which manages the interaction between external
display interfaces, e.g. Display Port, and the audio subsystem.
Optional properties:
- clock-mmrm: List of the clocks that enable setting the clk rate through MMRM driver.
The order of the list must match the 'clocks' and 'clock-names'
properties. The 'DISP_CC' ID of the clock must be used to enable
the property for the respective clock, whereas a value of zero
disables the property.
- vdd_mx-supply: phandle to vdda MX regulator node
- qcom,aux-en-gpio: Specifies the aux-channel enable gpio.
- qcom,aux-sel-gpio: Specifies the aux-channel select gpio.
@@ -170,6 +175,7 @@ sde_dp: qcom,dp_display@0 {
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
<&sde_dp DP_PHY_PLL_VCO_DIV_CLK>,
@@ -177,9 +183,10 @@ sde_dp: qcom,dp_display@0 {
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
"core_usb_pipe_clk", "link_clk", "link_iface_clk",
"pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",
"strm0_pixel_clk", "strm1_pixel_clk";
"core_usb_pipe_clk", "link_clk", "link_clk_src",
"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>;
qcom,pll-revision = "5nm-v1";
qcom,phy-version = <0x420>;