Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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arm64: dts: qcom: sm8150: Add cpufreq HW device node

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Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SM8150 SoCs.

Change-Id: I37fe076fbcc66b04183939ef555381f02825f387
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20191219120633.20723-1-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Git-commit: fea8930bd55e6d88e43ce44cd058aee3b85de274
Git-repo: https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next
[vvegivad@qti.qualcomm.com: minor modifications needed to handle as per cpufreq-hw driver]
This commit is contained in:
Sibi Sankar
2022-01-15 10:57:29 +05:30
committed by Veera Vegivada
parent ac49598904
commit 7116bce820
1 changed files with 22 additions and 0 deletions
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22
qcom/sm8150.dtsi
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@@ -49,6 +49,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -75,6 +76,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -95,6 +97,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_2>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -115,6 +118,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_3>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -135,6 +139,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_4>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -155,6 +160,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_5>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -175,6 +181,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_6>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -195,6 +202,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_7>;
qcom,freq-domain = <&cpufreq_hw 2 4>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
@@ -871,6 +879,20 @@
#clock-cells = <1>;
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0x18323000 0x1400>, <0x18325800 0x1400>,
<0x18327800 0x1400>;
reg-names = "freq-domain0", "freq-domain1",
"freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
qcom,no-accumulative-counter;
#freq-domain-cells = <2>;
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1100>,