Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add pinctrl property for 4W UART node"

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qctecmdr
2022-06-02 03:59:38 -07:00
committed by Gerrit - the friendly Code Review server
parent b835f3ffaf 18ed667ccf
commit 79ac5d6cf3
2 changed files with 17 additions and 15 deletions
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26
qcom/sm8150-pinctrl.dtsi
View File

@@ -1639,6 +1639,19 @@
};
qupv3_se17_4uart_pins: qupv3_se17_4uart_pins {
qupv3_se17_default_tx: qupv3_se17_default_tx {
mux {
pins = "gpio45";
function = "gpio";
};
config {
pins = "gpio45";
drive-strength = <2>;
bias-pull-up;
};
};
qupv3_se17_default_ctsrtsrx:
qupv3_se17_default_ctsrtsrx {
mux {
@@ -1653,19 +1666,6 @@
};
};
qupv3_se17_default_tx: qupv3_se17_default_tx {
mux {
pins = "gpio45";
function = "gpio";
};
config {
pins = "gpio45";
drive-strength = <2>;
bias-pull-up;
};
};
qupv3_se17_ctsrx: qupv3_se17_ctsrx {
mux {
pins = "gpio43", "gpio46";

6
qcom/sm8150-qupv3.dtsi
View File

@@ -533,11 +533,11 @@
/* GNSS UART Instance */
qupv3_se9_2uart: qcom,qup_uart@a84000 {
compatible = "qcom,geni-debug-uart";
compatible = "qcom,msm-geni-serial-hs";
reg = <0xa84000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
@@ -941,6 +941,8 @@
<&qupv3_se17_tx>;
pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
<&qupv3_se17_tx>;
pinctrl-3 = <&qupv3_se17_default_ctsrtsrx>,
<&qupv3_se17_default_tx>;
qcom,wakeup-byte = <0xFD>;
status = "disabled";
};