Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
2
0
Fork 0
mirror of https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees synced 2026-02-01 09:04:24 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge "ARM: dts: msm: Add sdcard support for SA8155"

Browse Source
This commit is contained in:
qctecmdr
2022-08-19 12:22:13 -07:00
committed by Gerrit - the friendly Code Review server
parent 268d95e8f9 1414d17e65
commit 7a3ce7c15e
2 changed files with 79 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
qcom/sa8155-adp-common.dtsi
View File

@@ -35,6 +35,24 @@
qcom,boot-option = <0x0>;
};
&sdhc_2 {
vdd-supply = <&pm8150_1_l17>;
qcom,vdd-voltage-level = <2950000 2960000>;
qcom,vdd-current-level = <200 800000>;
vdd-io-supply = <&pm8150_2_l13>;
qcom,vdd-io-voltage-level = <1808000 2960000>;
qcom,vdd-io-current-level = <200 22000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&pm8150_1_gpios 4 GPIO_ACTIVE_LOW>;
status = "ok";
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4";

61
qcom/sm8150.dtsi
View File

@@ -27,6 +27,7 @@
memory { device_type = "memory"; reg = <0 0 0 0>; };
aliases {
mmc1 = &sdhc_2; /* SDC2 SD card slot */
pci-domain0 = &pcie0; /* PCIe0 domain */
pci-domain1 = &pcie1; /* PCIe1 domain */
serial0 = &qupv3_se12_2uart;
@@ -1233,6 +1234,66 @@
};
};
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-peak-kBps = <1600000 280000>;
opp-avg-kBps = <50000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
opp-peak-kBps = <5600000 1500000>;
opp-avg-kBps = <104000 0>;
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x8804000 0x1000>;
reg-names = "hc";
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
bus-width = <4>;
no-sdio;
no-mmc;
qcom,restore-after-cx-collapse;
iommus = <&apps_smmu 0x06A0 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc2_opp_table>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
status = "disabled";
qos0 {
mask = <0x3f>;
vote = <44>;
};
qos1 {
mask = <0xc0>;
vote = <44>;
};
};
qcom,rmtfs_sharedmem@0 {
compatible = "qcom,sharedmem-uio";
reg = <0x0 0x200000>;