Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: qcom: Add SPU related nodes to kalama dtsi

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Needed for SPU pil on kalama dtsi.

Change-Id: If9184834b2d233529152c5481807c3f213200d66
This commit is contained in:
Nurit Lichtenstein
2021-12-07 15:44:19 +02:00
parent 6fb76fe7c5
commit 8969ffcef0
1 changed files with 95 additions and 0 deletions
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95
qcom/kalama.dtsi
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@@ -501,6 +501,15 @@
reg = <0x0 0xf3e00000 0x0 0x42f3000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
trust_ui_vm_qrtr: trust_ui_vm_qrtr@f80f3000 {
no-map;
reg = <0x0 0xf80f3000 0x0 0x9000>;
@@ -1155,6 +1164,92 @@
};
};
/* PIL spss node - for loading Secure Processor */
spss_pas: remoteproc-spss@1880000 {
compatible = "qcom,kalama-spss-pas";
ranges;
reg = <0x188101c 0x4>,
<0x1881024 0x4>,
<0x1881028 0x4>,
<0x188103c 0x4>,
<0x1881100 0x4>,
<0x1882014 0x4>;
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
"rmb_err", "rmb_general_purpose", "rmb_err_spare2";
interrupts = <0 352 1>;
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
status = "ok";
memory-region = <&spss_region_mem>;
qcom,spss-scsr-bits = <24 25>;
qcom,extra-size = <4096>;
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "crypto_ddr";
glink-edge {
qcom,remote-pid = <8>;
mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "spss_spss";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_SPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
reg = <0x1885008 0x8>,
<0x1885010 0x4>;
reg-names = "qcom,spss-addr",
"qcom,spss-size";
label = "spss";
qcom,glink-label = "spss";
};
};
qcom,spcom {
compatible = "qcom,spcom";
qcom,rproc-handle = <&spss_pas>;
qcom,boot-enabled;
/* predefined channels, remote side is server */
qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
/* sp2soc rmb shared register physical address and bmsk */
qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
/* soc2sp rmb shared register physical address */
qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
status = "ok";
};
spss_utils: qcom,spss_utils {
compatible = "qcom,spss-utils";
/* spss fuses physical address */
qcom,rproc-handle = <&spss_pas>;
qcom,spss-fuse1-addr = <0x221C8214>;
qcom,spss-fuse1-bit = <8>;
qcom,spss-fuse2-addr = <0x221C8214>;
qcom,spss-fuse2-bit = <7>;
qcom,spss-dev-firmware-name = "spss1d.mdt"; /* 8 chars max */
qcom,spss-test-firmware-name = "spss1t.mdt"; /* 8 chars max */
qcom,spss-prod-firmware-name = "spss1p.mdt"; /* 8 chars max */
qcom,spss-debug-reg-addr = <0x01886020>;
qcom,spss-debug-reg-addr1 = <0x01888020>;
qcom,spss-debug-reg-addr3 = <0x0188C020>;
qcom,spss-emul-type-reg-addr = <0x01fc8004>;
pil-mem = <&spss_region_mem>;
qcom,pil-size = <0x0F0000>; // padding to 960KB
status = "ok";
};
tlmm: pinctrl@f000000 {
compatible = "qcom,kalama-pinctrl";
reg = <0x0F000000 0x1000000>;