Merge "ARM: dts: msm: Add skeleton for all SA8195 DT files"

bindings/arm/msm/msm.txt

@@ -198,6 +198,9 @@ compatible = "qcom,sa8155p-adp-star"
 compatible = "qcom,sa8155-adp-air"
 compatible = "qcom,sa8155-v2-adp-air"
 compatible = "qcom,sa8155p-v2-adp-air"
+compatible = "qcom,sa8195p-adp-star"
+compatible = "qcom,sa8195p-adp-star"
+compatible = "qcom,sa8195p-adp-air"
 compatible = "qcom,adp-air"
 compatible = "qcom,kona-rumi"
 compatible = "qcom,kona-mtp"

qcom/Makefile

@@ -69,6 +69,7 @@ dtb-y += $(cinder-dtb-y)
 
 SA8155_BASE_DTB += sa8155.dtb sa8155-v2.dtb
 SA8155P_BASE_DTB += sa8155p.dtb sa8155p-v2.dtb
+SA8195P_BASE_DTB += sa8195p.dtb
 
 SA8155_BOARDS += \
 		 sa8155-adp-star-overlay.dtbo \
@@ -78,11 +79,20 @@ SA8155P_BOARDS += \
 		       sa8155p-adp-star-overlay.dtbo \
 		       sa8155p-adp-air-overlay.dtbo
 
+SA8195P_BOARDS += sa8195p-adp-star-overlay.dtbo \
+		  sa8195p-adp-air-overlay.dtbo
+
 gen3auto-dtb-$(CONFIG_ARCH_SA8155) += \
 	$(call add-overlays, $(SA8155_BOARDS),$(SA8155_BASE_DTB))\
 	$(call add-overlays, $(SA8155P_BOARDS),$(SA8155P_BASE_DTB))
 gen3auto-overlays-dtb-$(CONFIG_ARCH_SA8155) += $(SA8155_BOARDS) $(SA8155P_BOARDS) $(SA8155_BASE_DTB) $(SA8155P_BASE_DTB)
+
+gen3auto-dtb-$(CONFIG_ARCH_SA8195) += \
+		$(call add-overlays, $(SA8195P_BOARDS),$(SA8195P_BASE_DTB))
+gen3auto-overlays-dtb-$(CONFIG_ARCH_SA8195) += $(SA8195P_BOARDS) $(SA8195P_BASE_DTB)
+
 dtb-y += $(gen3auto-dtb-y)
+
 endif
 
 ifeq ($(CONFIG_ARCH_KALAMA), y)

qcom/sa8195p-adp-air-overlay.dts

@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "sa8195p-adp-air.dtsi"
+
+/ {
+	model = "SA8195P ADP-AIR";
+	compatible = "qcom,sa8195p-adp-air", "qcom,sa8195p",
+		"qcom,adp-air";
+	qcom,msm-id = <405 0x20000>;
+	qcom,board-id = <0x02010019 0>;
+};

qcom/sa8195p-adp-air.dtsi

@@ -0,0 +1 @@
+#include "sa8195p-adp-common.dtsi"

qcom/sa8195p-adp-common.dtsi

@@ -0,0 +1,5 @@
+#include <dt-bindings/gpio/gpio.h>
+
+&uart2 {
+	status = "ok";
+};

qcom/sa8195p-adp-star-overlay.dts

@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "sa8195p-adp-star.dtsi"
+
+/ {
+	model = "SA8195P ADP-STAR";
+	compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p",
+		"qcom,adp-star";
+	qcom,msm-id = <405 0x20000>;
+	qcom,board-id = <0x010019 0>;
+};

qcom/sa8195p-adp-star.dtsi

@@ -0,0 +1 @@
+#include "sa8195p-adp-common.dtsi"

qcom/sa8195p.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "sa8195p.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SA8195P SoC";
+	compatible = "qcom,sa8195p";
+	qcom,pmic-name = "PM8150";
+	qcom,board-id = <0 0>;
+};

qcom/sa8195p.dtsi

@@ -0,0 +1,8 @@
+#include "sdmshrike-v2.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SA8195P";
+	qcom,msm-name = "SA8195P";
+	qcom,msm-id = <405 0x20000>;
+};
+

qcom/sdmshrike-v2.dtsi

@@ -0,0 +1,8 @@
+
+#include "sdmshrike.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. SA8195 V2";
+	qcom,msm-name = "SA8195 V2";
+	qcom,msm-id = <340 0x20000>;
+};
+

qcom/sdmshrike.dtsi

@@ -0,0 +1,524 @@
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. SDMSHRIKE";
+	compatible = "qcom,sdmshrike";
+	qcom,msm-name = "SDMSHRIKE";
+	qcom,msm-id = <340 0x10000>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+	aliases {
+		serial0 = &uart2;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			cache-size = <0x8000>;
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-size = <0x20000>;
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+
+				L3_0: l3-cache {
+				      compatible = "arm,arch-cache";
+				      cache-size = <0x400000>;
+				      cache-level = <3>;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			cache-size = <0x8000>;
+			next-level-cache = <&L2_1>;
+			L2_1: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-size = <0x20000>;
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			cache-size = <0x8000>;
+			next-level-cache = <&L2_2>;
+			#cooling-cells = <2>;
+			L2_2: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-size = <0x20000>;
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			cache-size = <0x8000>;
+			next-level-cache = <&L2_3>;
+			L2_3: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-size = <0x20000>;
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1740>;
+			cache-size = <0x10000>;
+			next-level-cache = <&L2_4>;
+			L2_4: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-size = <0x80000>;
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1740>;
+			cache-size = <0x10000>;
+			next-level-cache = <&L2_5>;
+			L2_5: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-size = <0x80000>;
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1740>;
+			cache-size = <0x10000>;
+			next-level-cache = <&L2_6>;
+			L2_6: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-size = <0x80000>;
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1740>;
+			cache-size = <0x10000>;
+			next-level-cache = <&L2_7>;
+			L2_7: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-size = <0x80000>;
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+
+				core3 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	chosen {};
+
+	firmware: firmware { };
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hyp_mem: hyp_mem@85700000 {
+			no-map;
+			reg = <0x0 0x85700000 0x0 0x600000>;
+		};
+
+		xbl_aop_mem: xbl_aop_mem@85e00000 {
+			no-map;
+			reg = <0x0 0x85e00000 0x0 0x120000>;
+		};
+
+		flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 {
+			no-map;
+			reg = <0x0 0x85ffd000 0x0 0x3000>;
+		};
+
+		aop_cmd_db: memory@85f20000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x85f20000 0x0 0x20000>;
+			no-map;
+		};
+
+		smem_region: smem@86000000 {
+			no-map;
+			reg = <0x0 0x86000000 0x0 0x200000>;
+		};
+
+		removed_regions: removed_regions@86200000 {
+			no-map;
+			reg = <0x0 0x86200000 0x0 0x5500000>;
+		};
+
+		pil_camera_mem: camera_region@8b700000 {
+			no-map;
+			reg = <0x0 0x8b700000 0x0 0x500000>;
+		};
+
+		pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 {
+			no-map;
+			reg = <0x0 0x8bc00000 0x0 0x180000>;
+		};
+
+		pil_npu_mem: pil_npu_region@8bd80000 {
+			no-map;
+			reg = <0x0 0x8bd80000 0x0 0x80000>;
+		};
+
+		pil_adsp_mem: pil_adsp_region@8be00000 {
+			no-map;
+			reg = <0x0 0x8be00000 0x0 0x1a00000>;
+		};
+
+		pil_modem_mem: modem_region@8d800000 {
+			no-map;
+			reg = <0x0 0x8d800000 0x0 0x9600000>;
+		};
+
+		pil_video_mem: pil_video_region@96e00000 {
+			no-map;
+			reg = <0x0 0x96e00000 0x0 0x500000>;
+		};
+
+		pil_slpi_mem: pil_slpi_region@97300000 {
+			no-map;
+			reg = <0x0 0x97300000 0x0 0x1400000>;
+		};
+
+		pil_ipa_fw_mem: pil_ipa_fw_region@98700000 {
+			no-map;
+			reg = <0x0 0x98700000 0x0 0x10000>;
+		};
+
+		pil_ipa_gsi_mem: pil_ipa_gsi_region@98710000 {
+			no-map;
+			reg = <0x0 0x98710000 0x0 0x5000>;
+		};
+
+		pil_gpu_mem: pil_gpu_region@98715000 {
+			no-map;
+			reg = <0x0 0x98715000 0x0 0x2000>;
+		};
+
+		pil_spss_mem: pil_spss_region@98800000 {
+			no-map;
+			reg = <0x0 0x98800000 0x0 0x100000>;
+		};
+
+		pil_cdsp_mem: cdsp_regions@98900000 {
+			no-map;
+			reg = <0x0 0x98900000 0x0 0x1400000>;
+		};
+
+		qseecom_mem: qseecom_region {
+			compatible = "shared-dma-pool";
+			no-map;
+			reg = <0x0 0x9e400000 0x0 0x1400000>;
+		};
+
+
+		cont_splash_memory: splash_region {
+			reg = <0x0 0x9c000000 0x0 0x02400000>;
+			label = "cont_splash_region";
+		};
+
+		disp_rdump_memory: disp_rdump_region@9c000000 {
+			reg = <0x0 0x9c000000 0x0 0x02400000>;
+			label = "disp_rdump_region";
+		};
+
+		adsp_mem: adsp_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+		};
+
+		cdsp_mem: cdsp_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x400000>;
+		};
+
+		user_contig_mem: user_contig_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+		};
+
+		qseecom_ta_mem: qseecom_ta_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+		};
+
+		sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x800000>;
+		};
+
+		secure_display_memory: secure_display_region { /* Secure UI */
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0xA000000>;
+		};
+
+		dump_mem: mem_dump_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			size = <0 0x2400000>;
+		};
+
+		uefi_log: uefi_log@8bc00000 {
+			reg = <0x0 0x8bc00000 0x0 0x10000>;
+			label = "uefi_log";
+		};
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x2800000>;
+			linux,cma-default;
+		};
+	};
+
+	soc: soc { };
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	intc: interrupt-controller@17a00000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x20000>;
+		reg = <0x17a00000 0x10000>,     /* GICD */
+		      <0x17a60000 0x100000>;    /* GICR * 8 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&intc>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	timer@17c20000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x17c20000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@17c21000 {
+			frame-number = <0>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c21000 0x1000>,
+			      <0x17c22000 0x1000>;
+		};
+
+		frame@17c23000 {
+			frame-number = <1>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c23000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17c25000 {
+			frame-number = <2>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c25000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17c27000 {
+			frame-number = <3>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c26000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17c29000 {
+			frame-number = <4>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c29000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17c2b000 {
+			frame-number = <5>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c2b000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17c2d000 {
+			frame-number = <6>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c2d000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+	qcom,msm-rtb {
+		compatible = "qcom,msm-rtb";
+		qcom,rtb-size = <0x100000>;
+	};
+
+	qcom,mpm2-sleep-counter@c221000 {
+		compatible = "qcom,mpm2-sleep-counter";
+		reg = <0xc221000 0x1000>;
+		clock-frequency = <32768>;
+	};
+
+	apps_rsc: rsc@18200000 {
+		label = "apps_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0x18200000 0x10000>,
+			<0x18210000 0x10000>,
+			<0x18220000 0x10000>;
+		reg-names = "drv-0", "drv-1", "drv-2";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,tcs-offset = <0xd00>;
+		qcom,drv-id = <2>;
+		qcom,tcs-config = <ACTIVE_TCS  2>,
+				<SLEEP_TCS   3>,
+				<WAKE_TCS    3>,
+				<CONTROL_TCS 1>;
+
+	};
+
+	qupv3_id_1: geniqup@ac0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x00ac0000 0x6000>;
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart2: serial@a90000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0x00a90000 0x4000>;
+			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+	};
+};