mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-01-31 22:47:58 +00:00
ARM: dts: msm: Add clock controller and gdsc nodes for sm8150
Add support for all the clock controllers and also add gdsc regulators. Change-Id: Ic313db887845e43c1d69b82f6bd8af4154145832
This commit is contained in:
Veera Vegivada
@@ -7,3 +7,23 @@
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qcom,msm-name = "SA8155 V1";
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qcom,msm-id = <362 0x10000>;
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};
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&scc {
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compatible = "qcom,sa8155-scc", "syscon";
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};
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&gcc {
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compatible = "qcom,sa8155-gcc", "syscon";
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};
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&videocc {
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compatible = "qcom,sa8155-videocc", "syscon";
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};
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&npucc {
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compatible = "qcom,sa8155-npucc", "syscon";
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};
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&camcc {
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compatible = "qcom,sa8155-camcc", "syscon";
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};
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@@ -62,3 +62,16 @@
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ranges;
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};
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};
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&gpucc {
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compatible = "qcom,sa8155-gpucc", "syscon";
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};
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&scc {
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vdd_scc_cx-supply = <&VDD_CX_LEVEL>;
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status = "ok";
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};
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&gpu_gx_gdsc {
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parent-supply = <&VDD_GFX_LEVEL>;
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};
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244
qcom/sm8150-gdsc.dtsi
Normal file
244
qcom/sm8150-gdsc.dtsi
Normal file
@@ -0,0 +1,244 @@
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&soc {
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/* GDSCs in Global CC */
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emac_gdsc: qcom,gdsc@106004 {
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compatible = "qcom,gdsc";
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regulator-name = "emac_gdsc";
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reg = <0x106004 0x4>;
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status = "disabled";
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};
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pcie_0_gdsc: qcom,gdsc@16b004 {
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compatible = "qcom,gdsc";
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regulator-name = "pcie_0_gdsc";
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reg = <0x16b004 0x4>;
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status = "disabled";
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};
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pcie_1_gdsc: qcom,gdsc@18d004 {
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compatible = "qcom,gdsc";
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regulator-name = "pcie_1_gdsc";
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reg = <0x18d004 0x4>;
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status = "disabled";
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};
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ufs_card_gdsc: qcom,gdsc@175004 {
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compatible = "qcom,gdsc";
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regulator-name = "ufs_card_gdsc";
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reg = <0x175004 0x4>;
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status = "disabled";
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};
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ufs_phy_gdsc: qcom,gdsc@177004 {
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compatible = "qcom,gdsc";
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regulator-name = "ufs_phy_gdsc";
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reg = <0x177004 0x4>;
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status = "disabled";
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};
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usb30_prim_gdsc: qcom,gdsc@10f004 {
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compatible = "qcom,gdsc";
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regulator-name = "usb30_prim_gdsc";
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reg = <0x10f004 0x4>;
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status = "disabled";
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};
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usb30_sec_gdsc: qcom,gdsc@110004 {
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compatible = "qcom,gdsc";
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regulator-name = "usb30_sec_gdsc";
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reg = <0x110004 0x4>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";
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reg = <0x17d040 0x4>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";
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reg = <0x17d044 0x4>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";
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reg = <0x17d048 0x4>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";
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reg = <0x17d04c 0x4>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
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reg = <0x17d050 0x4>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
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reg = <0x17d054 0x4>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
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reg = <0x17d058 0x4>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
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reg = <0x17d05c 0x4>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 {
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compatible = "qcom,gdsc";
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regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
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reg = <0x17d060 0x4>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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/* GDSCs in Camera CC */
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bps_gdsc: qcom,gdsc@ad07004 {
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compatible = "qcom,gdsc";
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regulator-name = "bps_gdsc";
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reg = <0xad07004 0x4>;
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status = "disabled";
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};
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ipe_0_gdsc: qcom,gdsc@ad08004 {
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compatible = "qcom,gdsc";
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regulator-name = "ipe_0_gdsc";
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reg = <0xad08004 0x4>;
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status = "disabled";
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};
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ipe_1_gdsc: qcom,gdsc@ad09004 {
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compatible = "qcom,gdsc";
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regulator-name = "ipe_1_gdsc";
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reg = <0xad09004 0x4>;
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status = "disabled";
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};
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ife_0_gdsc: qcom,gdsc@ad0a004 {
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compatible = "qcom,gdsc";
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regulator-name = "ife_0_gdsc";
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reg = <0xad0a004 0x4>;
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status = "disabled";
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};
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ife_1_gdsc: qcom,gdsc@ad0b004 {
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compatible = "qcom,gdsc";
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regulator-name = "ife_1_gdsc";
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reg = <0xad0b004 0x4>;
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status = "disabled";
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};
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titan_top_gdsc: qcom,gdsc@ad0c1bc {
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compatible = "qcom,gdsc";
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regulator-name = "titan_top_gdsc";
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reg = <0xad0c1bc 0x4>;
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status = "disabled";
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};
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/* GDSCs in Display CC */
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mdss_core_gdsc: qcom,gdsc@af03000 {
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compatible = "qcom,gdsc";
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regulator-name = "mdss_core_gdsc";
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reg = <0xaf03000 0x4>;
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qcom,support-hw-trigger;
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status = "disabled";
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proxy-supply = <&mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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};
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/* GDSCs in Graphics CC */
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gpu_cx_hw_ctrl: syscon@2c91540 {
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compatible = "syscon";
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reg = <0x2c91540 0x4>;
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};
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gpu_cx_gdsc: qcom,gdsc@2c9106c {
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compatible = "qcom,gdsc";
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regulator-name = "gpu_cx_gdsc";
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reg = <0x2c9106c 0x4>;
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hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
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qcom,skip-disable;
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qcom,clk-dis-wait-val = <8>;
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mboxes = <&qmp_aop 0>;
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status = "disabled";
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};
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gpu_gx_domain_addr: syscon@2c91508 {
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compatible = "syscon";
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reg = <0x2c91508 0x4>;
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};
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gpu_gx_sw_reset: syscon@2c91008 {
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compatible = "syscon";
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reg = <0x2c91008 0x4>;
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};
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gpu_gx_gdsc: qcom,gdsc@2c9100c {
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compatible = "qcom,gdsc";
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regulator-name = "gpu_gx_gdsc";
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reg = <0x2c9100c 0x4>;
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domain-addr = <&gpu_gx_domain_addr>;
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sw-reset = <&gpu_gx_sw_reset>;
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qcom,reset-aon-logic;
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status = "disabled";
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};
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/* GDSCs in Video CC */
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mvsc_gdsc: qcom,gdsc@ab00814 {
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compatible = "qcom,gdsc";
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regulator-name = "mvsc_gdsc";
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reg = <0xab00814 0x4>;
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status = "disabled";
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};
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mvs0_gdsc: qcom,gdsc@ab00874 {
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compatible = "qcom,gdsc";
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regulator-name = "mvs0_gdsc";
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reg = <0xab00874 0x4>;
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status = "disabled";
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};
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mvs1_gdsc: qcom,gdsc@ab008b4 {
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compatible = "qcom,gdsc";
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regulator-name = "mvs1_gdsc";
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reg = <0xab008b4 0x4>;
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status = "disabled";
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};
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/* GDSCs in NPU CC */
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npu_core_gdsc: qcom,gdsc@9911028 {
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compatible = "qcom,gdsc";
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regulator-name = "npu_core_gdsc";
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reg = <0x9911028 0x4>;
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status = "disabled";
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};
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};
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281
qcom/sm8150.dtsi
281
qcom/sm8150.dtsi
@@ -3,6 +3,12 @@
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,gcc-sm8150.h>
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#include <dt-bindings/clock/qcom,aop-qmp.h>
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#include <dt-bindings/clock/qcom,camcc-sm8150.h>
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#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
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#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
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#include <dt-bindings/clock/qcom,npucc-sm8150.h>
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#include <dt-bindings/clock/qcom,scc-sm8150.h>
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#include <dt-bindings/clock/qcom,videocc-sm8150.h>
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/ {
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model = "Qualcomm Technologies, Inc. SM8150";
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@@ -703,14 +709,125 @@
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};
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sm8150";
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compatible = "qcom,sm8150-gcc", "syscon";
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reg = <0x100000 0x1f0000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
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vdd_mm-supply = <&VDD_MMCX_LEVEL>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>;
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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videocc: clock-controller@ab00000 {
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compatible = "qcom,sm8150-videocc", "syscon";
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reg = <0xab00000 0x10000>;
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reg-names = "cc_base";
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vdd_mm-supply = <&VDD_MMCX_LEVEL>;
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clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "bi_tcxo";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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camcc: clock-controller@ad00000 {
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compatible = "qcom,sm8150-camcc", "syscon";
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reg = <0xad00000 0x10000>;
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reg-names = "cc_base";
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vdd_mx-supply = <&VDD_MX_LEVEL>;
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vdd_mm-supply = <&VDD_MMCX_LEVEL>;
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clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "bi_tcxo";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dispcc: clock-controller@af00000 {
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compatible = "qcom,sm8150-dispcc", "syscon";
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reg = <0xaf00000 0x20000>;
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reg-names = "cc_base";
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vdd_mm-supply = <&VDD_MMCX_LEVEL>;
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clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "bi_tcxo";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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npucc: clock-controller@9910000 {
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compatible = "qcom,sm8150-npucc", "syscon";
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reg = <0x9910000 0x10000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_gdsc-supply = <&npu_core_gdsc>;
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clocks =
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
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<&gcc GCC_NPU_GPLL0_CLK_SRC>,
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<&gcc GCC_NPU_AXI_CLK>;
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clock-names =
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"bi_tcxo",
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"gcc_npu_gpll0_div_clk_src",
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"gcc_npu_gpll0_clk_src",
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"gcc_npu_axi_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gpucc: clock-controller@2c90000 {
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compatible = "qcom,sm8150-gpucc", "syscon";
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reg = <0x2c90000 0x9000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_mx-supply = <&VDD_MX_LEVEL>;
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clocks =
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
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<&gcc GCC_GPU_CFG_AHB_CLK>;
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clock-names = "bi_tcxo",
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"sleep_clk";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>;
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"gcc_gpu_gpll0_clk_src",
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"gcc_gpu_gpll0_div_clk_src",
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"iface";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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scc: clock-controller@2b10000 {
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compatible = "qcom,sm8150-scc", "syscon";
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reg = <0x2b10000 0x30000>;
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vdd_scc_cx-supply = <&pm8150_l8_level>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "bi_tcxo";
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#clock-cells = <1>;
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status = "disabled";
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||||
};
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cpucc: syscon@182a0000 {
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compatible = "syscon";
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reg = <0x182a0000 0x4>;
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};
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mccc: syscon@90b0000 {
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compatible = "syscon";
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reg = <0x90b0000 0x1000>;
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||||
};
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||||
debugcc: debug-clock-controller@0 {
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compatible = "qcom,sm8150-debugcc";
|
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qcom,gcc = <&gcc>;
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qcom,videocc = <&videocc>;
|
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qcom,camcc = <&camcc>;
|
||||
qcom,dispcc = <&dispcc>;
|
||||
qcom,npucc = <&npucc>;
|
||||
qcom,gpucc = <&gpucc>;
|
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qcom,cpucc = <&cpucc>;
|
||||
qcom,mccc = <&mccc>;
|
||||
clock-names = "xo_clk_src";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
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||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
qupv3_id_1: geniqup@ac0000 {
|
||||
@@ -781,3 +898,159 @@
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#include "sm8150-regulator.dtsi"
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#include "sm8150-pinctrl.dtsi"
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#include "sm8150-dma-heaps.dtsi"
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#include "sm8150-gdsc.dtsi"
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&emac_gdsc {
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status = "ok";
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};
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||||
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&pcie_0_gdsc {
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status = "ok";
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||||
};
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||||
|
||||
&pcie_1_gdsc {
|
||||
status = "ok";
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||||
};
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||||
|
||||
&ufs_phy_gdsc {
|
||||
status = "ok";
|
||||
};
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||||
|
||||
&ufs_card_gdsc {
|
||||
status = "ok";
|
||||
};
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||||
|
||||
&usb30_prim_gdsc {
|
||||
status = "ok";
|
||||
};
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||||
|
||||
&usb30_sec_gdsc {
|
||||
status = "ok";
|
||||
};
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||||
|
||||
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&bps_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&ipe_0_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&ipe_1_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&ife_0_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&ife_1_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&titan_top_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&mdss_core_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpu_cx_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpu_gx_gdsc {
|
||||
parent-supply = <&VDD_GFX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&mvsc_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&mvs0_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&mvs1_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&npu_core_gdsc {
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user