Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: msm: Update MPM irqchip device for monaco

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Update MPM irqchip device while at this update the
IPC interrupt register to cluster0 register and add
the mpm as wakeup parent for GPIO interrupts.

Change-Id: I035591ee4618263f30bb463e981f1a86a2927bfc
This commit is contained in:
Raghavendra Kakarla
2022-09-15 09:33:14 +05:30
parent d90fa44d37
commit 971e060c7f
3 changed files with 8 additions and 7 deletions
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2
qcom/monaco-pinctrl.dtsi
View File

@@ -7,7 +7,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&wakegic>;
wakeup-parent = <&mpm>;
qupv3_se6_2uart_pins: qupv3_se6_2uart_pins {
qupv3_se6_2uart_tx_active: qupv3_se6_2uart_tx_active {

2
qcom/monaco-thermal.dtsi
View File

@@ -45,7 +45,7 @@
"tsens_tm_physical";
interrupts-extended = <&intc 0 275 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 190 IRQ_TYPE_LEVEL_HIGH>,
<&wakegic 89 IRQ_TYPE_EDGE_RISING>;
<&mpm 89 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tsens-upper-lower",
"tsens-critical",
"tsens-0C";

11
qcom/monaco.dtsi
View File

@@ -1018,7 +1018,7 @@
<0x1c0a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts-extended = <&wakegic 86 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,mid = <0>;
qcom,channel = <0>;
@@ -1544,12 +1544,13 @@
};
};
wakegic: wake-gic {
compatible = "qcom,mpm-gic-monaco", "qcom,mpm";
mpm: interrupt-controller@45f01b8 {
compatible = "qcom,mpm-monaco", "qcom,mpm";
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
reg = <0x45f01b8 0x1000>,
<0xf111008 0x4>;
reg-names = "vmpm", "ipc";
<0xf111008 0x4>,
<0xf121000 0x1000>;
reg-names = "vmpm", "ipc", "timer";
qcom,num-mpm-irqs = <96>;
interrupt-controller;
interrupt-parent = <&intc>;