mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
Merge "ARM: dts: msm: Add initial device tree for cinder"
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qctecmdr
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Gerrit - the friendly Code Review server
commit
a27bf50e30
@@ -48,6 +48,18 @@ KALAMA_BOARDS += \
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dtb-$(CONFIG_ARCH_KALAMA) += \
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$(call add-overlays, $(KALAMA_BOARDS),$(KALAMA_BASE_DTB))
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ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
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CINDER_BASE_DTB += cinder.dtb
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CINDER_BOARDS += cinder-rumi-overlay.dtbo \
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cinder-idp-overlay.dtbo
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dtb-$(CONFIG_ARCH_CINDER) += \
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$(call add-overlays, $(CINDER_BOARDS), $(CINDER_BASE_DTB))
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else
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dtb-$(CONFIG_ARCH_CINDER) += cinder-rumi.dtb \
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cinder-idp.dtb
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endif
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always-y := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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11
qcom/cinder-idp-overlay.dts
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11
qcom/cinder-idp-overlay.dts
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@@ -0,0 +1,11 @@
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/dts-v1/;
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/plugin/;
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#include "cinder-idp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cinder IDP";
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compatible = "qcom,cinder-idp", "qcom,cinder", "qcom,idp";
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qcom,msm-id = <539 0x10000>;
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qcom,board-id = <0x1 0x0>;
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};
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10
qcom/cinder-idp.dts
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10
qcom/cinder-idp.dts
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@@ -0,0 +1,10 @@
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/dts-v1/;
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#include "cinder.dtsi"
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#include "cinder-idp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cinder IDP";
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compatible = "qcom,cinder-idp", "qcom,cinder", "qcom,idp";
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qcom,board-id = <0x1 0x0>;
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};
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5
qcom/cinder-idp.dtsi
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5
qcom/cinder-idp.dtsi
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@@ -0,0 +1,5 @@
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&soc {
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};
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12
qcom/cinder-rumi-overlay.dts
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12
qcom/cinder-rumi-overlay.dts
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@@ -0,0 +1,12 @@
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/dts-v1/;
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/plugin/;
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#include "cinder.dtsi"
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#include "cinder-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cinder RUMI";
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compatible = "qcom,cinder-rumi", "qcom,cinder", "qcom,rumi";
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qcom,msm-id = <539 0x10000>;
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qcom,board-id = <0xF 0x0>;
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};
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11
qcom/cinder-rumi.dts
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11
qcom/cinder-rumi.dts
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@@ -0,0 +1,11 @@
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/dts-v1/;
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/memreserve/ 0x90000000 0x00010000;
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#include "cinder.dtsi"
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#include "cinder-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cinder RUMI";
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compatible = "qcom,cinder-rumi", "qcom,cinder", "qcom,rumi";
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qcom,board-id = <0xF 0x0>;
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};
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15
qcom/cinder-rumi.dtsi
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15
qcom/cinder-rumi.dtsi
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@@ -0,0 +1,15 @@
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&chosen {
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bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
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};
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&arch_timer {
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clock-frequency = <500000>;
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};
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&memtimer {
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clock-frequency = <500000>;
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};
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&soc {
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};
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9
qcom/cinder.dts
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9
qcom/cinder.dts
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@@ -0,0 +1,9 @@
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/dts-v1/;
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#include "cinder.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cinder SoC";
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compatible = "qcom,cinder";
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qcom,board-id = <0x0 0x0>;
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};
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196
qcom/cinder.dtsi
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196
qcom/cinder.dtsi
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@@ -0,0 +1,196 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm Technologies, Inc. Cinder";
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compatible = "qcom,cinder";
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qcom,msm-id = <539 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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chosen: chosen { };
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aliases { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x80000>; /* GICR * 4 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@17c20000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17c20000 0x1000>;
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clock-frequency = <19200000>;
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frame@17c21000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c21000 0x1000>,
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<0x17c22000 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c23000 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c25000 0x1000>,
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<0x17c26000 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c27000 0x1000>;
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status = "disabled";
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};
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frame@17c29000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c29000 0x1000>;
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status = "disabled";
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};
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frame@17c2b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c2b000 0x1000>;
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status = "disabled";
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};
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frame@17c2d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c2d000 0x1000>;
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status = "disabled";
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};
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};
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};
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