Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Update clock controller nodes for Khaje"

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qctecmdr
2022-06-17 18:01:34 -07:00
committed by Gerrit - the friendly Code Review server
parent 07fc6e3996 66ebbe3699
commit b024f50390
1 changed files with 35 additions and 28 deletions
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63
qcom/khaje.dtsi
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@@ -2516,32 +2516,6 @@
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&sleep_clk>;
clock-names = "bi_tcxo",
"bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc: clock-controller@5f00000 {
compatible = "qcom,khaje-dispcc", "syscon";
reg = <0x05f00000 0x20000>;
reg-names = "cc_base";
clock-names = "cfg_ahb_clk";
clocks = <&gcc GCC_DISP_AHB_CLK>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
#clock-cells = <1>;
#reset-cells = <1>;
};
gpucc: clock-controller@5990000 {
compatible = "qcom,khaje-gpucc", "syscon";
reg = <0x5990000 0x9000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&sleep_clk>,
@@ -2559,12 +2533,45 @@
#reset-cells = <1>;
};
dispcc: clock-controller@5f00000 {
compatible = "qcom,khaje-dispcc", "syscon";
reg = <0x05f00000 0x20000>;
reg-names = "cc_base";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>;
clock-names = "bi_tcxo",
"sleep_clk",
"iface",
"gcc_disp_gpll0_clk";
vdd_cx-supply = <&VDD_CX_LEVEL>;
#clock-cells = <1>;
#reset-cells = <1>;
};
gpucc: clock-controller@5990000 {
compatible = "qcom,khaje-gpucc", "syscon";
reg = <0x5990000 0x9000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&gcc GPLL0>,
<&sleep_clk>;
clock-names = "bi_tcxo",
"bi_tcxo_ao", "gpll0_out_main", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
mccc_debug: syscon@447d200 {
compatible = "syscon";
reg = <0x447d200 0x100>;
};
cpucc_debug: syscon@f11101c {
apsscc_debug: syscon@f11101c {
compatible = "syscon";
reg = <0xf11101c 0x4>;
};
@@ -2575,7 +2582,7 @@
qcom,dispcc = <&dispcc>;
qcom,gpucc = <&gpucc>;
qcom,mccc = <&mccc_debug>;
qcom,cpucc = <&cpucc_debug>;
qcom,apsscc = <&apsscc_debug>;
clock-names = "xo_clk_src";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
#clock-cells = <1>;