ARM: dts: msm: add hgsl to sa8155 vm for GPU doorbell

hgsl device is for GPU doorbell feature which allows
GVM to submit commands to GPU directly.

Change-Id: Ib05082e80b411e02d62beb07ee83f7c684db06b4

bindings/soc/qcom/hgsl-tcsr.txt

@@ -0,0 +1,31 @@
+Top Control and Status Register(TCSR) for HGSL
+
+TCSR hardware contains compute signal sub-block, which allows drivers in hypervisor
+Linux to communicate with GPU hardware directly. This HGSL TCSR driver is to enable
+the TCSR compute signal hardware. There are multiple instances of compute signal.
+Each instance is either a signal sender or signal receiver.
+
+The HGSL TCSR driver is built on top of generic TCSR driver, refer to
+Documentation/devicetree/bindings/mfd/qcom,tcsr.txt for the generic TCSR driver.
+
+Required properties:
+- compatible : Must be "qcom,hgsl-tcsr-sender" or "qcom,hgsl-tcsr-receiver"
+- syscon     : Point to the generic TCSR compute signal node
+- syscon-glb : Point to the generice TCSR node for compute signal global control.
+	       This is only needed by signal sender.
+- interrupts : Specify IRQ information used by the compute signal.
+	       This is only needed by signal receiver.
+
+Examples:
+	hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
+		compatible = "qcom,hgsl-tcsr-sender";
+		syscon = <&tcsr_compute_signal_sender0>;
+		syscon-glb = <&tcsr_compute_signal_glb>;
+	};
+
+	hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
+		compatible = "qcom,hgsl-tcsr-receiver";
+		syscon = <&tcsr_compute_signal_receiver0>;
+		interrupts = <0 238 0>;
+	};
+

bindings/soc/qcom/hgsl.txt

@@ -0,0 +1,32 @@
+* HGSL
+
+HGSL(Hypervisor Graphics system layer) is graphics driver under the hypervisor system.
+
+Required properties:
+- compatible : Must be "qcom,hgsl"
+
+- reg : physical base address and length of the register set(s).
+
+- reg-names : names corresponding to each reg property value.
+	      reg_hwver: HW version registers
+	      reg_doorbell_idx: address of GMUAO_DOORBELL_IDX
+
+Optional properties:
+- db-off: Disable Doorbell feature but keep hgsl for ifence service
+- qcom,glb-db-senders : Point to possible nodes of HGSL TCSR sender. The user will select
+		        which sender to use. The driver will use TCSR compute signal to
+		        send signal to GPU.
+- qcom,glb-db-receivers : Point to possible nodes of HGSL TCSR receiver. The user will
+			  select which receiver to use. The driver will use TCSR compute
+			  signal to receive signal from GPU.
+
+Example:
+	msm_gpu_hyp {
+		compatible = "qcom,hgsl";
+		reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
+		reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";
+
+		db-off = <0>;
+		qcom,glb-db-senders = <&hgsl_tcsr_sender0 &hgsl_tcsr_sender1>;
+		qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 &hgsl_tcsr_receiver1>;
+	};

qcom/sa8155-vm.dtsi

@@ -412,3 +412,64 @@
 &qupv3_se12_2uart {
 	status = "disabled";
 };
+&soc {
+	tcsr_compute_signal_glb: syscon@0x1fd8000 {
+		compatible = "syscon";
+		reg = <0x1fd8000 0x1000>;
+	};
+
+	tcsr_compute_signal_sender0: syscon@0x1fd9000 {
+		compatible = "syscon";
+		reg = <0x1fd9000 0x1000>;
+	};
+
+	tcsr_compute_signal_sender1: syscon@0x1fdd000 {
+		compatible = "syscon";
+		reg = <0x1fdd000 0x1000>;
+	};
+
+	tcsr_compute_signal_receiver0: syscon@0x1fdb000 {
+		compatible = "syscon";
+		reg = <0x1fdb000 0x1000>;
+	};
+
+	tcsr_compute_signal_receiver1: syscon@0x1fdf000 {
+		compatible = "syscon";
+		reg = <0x1fdf000 0x1000>;
+	};
+
+	hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
+		compatible = "qcom,hgsl-tcsr-sender";
+		syscon = <&tcsr_compute_signal_sender0>;
+		syscon-glb = <&tcsr_compute_signal_glb>;
+	};
+
+	hgsl_tcsr_sender1: hgsl_tcsr_sender1 {
+		compatible = "qcom,hgsl-tcsr-sender";
+		syscon = <&tcsr_compute_signal_sender1>;
+		syscon-glb = <&tcsr_compute_signal_glb>;
+	};
+
+	hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
+		compatible = "qcom,hgsl-tcsr-receiver";
+		syscon = <&tcsr_compute_signal_receiver0>;
+		interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 {
+		compatible = "qcom,hgsl-tcsr-receiver";
+		syscon = <&tcsr_compute_signal_receiver1>;
+		interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	msm_gpu_hyp: qcom,hgsl@0x2c00000 {
+		compatible = "qcom,hgsl";
+		reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
+		reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";
+
+		qcom,glb-db-senders = <&hgsl_tcsr_sender0
+					&hgsl_tcsr_sender1>;
+		qcom,glb-db-receivers = <&hgsl_tcsr_receiver0
+					&hgsl_tcsr_receiver1>;
+	};
+};