Merge 85a089b88d on remote branch

Change-Id: I903ca2a54f6c354f85fec2d41466fa9283f8c236
2026-02-01 09:49:52 +00:00 · 2022-10-31 03:02:36 -07:00
parent b4b49ac12b 85a089b88d
commit b3506e76ed
73 changed files with 3839 additions and 303 deletions
--- a/bindings/arm/msm/mdm-modem.txt
+++ b/bindings/arm/msm/mdm-modem.txt
@@ -6,7 +6,7 @@ to be reset.

 Required Properties:
 - compatible:	The bus devices need to be compatible with "qcom,ext-mdm9x55", "qcom,ext-sdx50m",
-		"qcom,ext-sdx55m", "qcom,ext-lemur", "qcom,ext-pinn".
+		"qcom,ext-sdx55m", "qcom,ext-lemur", "qcom,ext-pinn", "qcom,ext-baagha".

 Required named gpio properties:
 - qcom,mdm2ap-errfatal-gpio: gpio for the external modem to indicate to the apps processor
--- a/bindings/arm/msm/qcom,llcc.txt
+++ b/bindings/arm/msm/qcom,llcc.txt
@@ -15,9 +15,10 @@ Properties:
                    "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,waipio-llcc"
 			or "qcom,sdxlemur-llcc" or "qcom,diwali-llcc"
 			or "qcom,kalama-llcc" or "qcom,cinder-llcc"
-			or "qcom,sdmshrike-llcc".
+			or "qcom,sdmshrike-llcc" or "qcom,lemans-llcc".
 		    "qcom,llcc-v2" must be appended for V2 hardware or
-		    "qcom,llcc-v21" for V2.1 or "qcom,llcc-v41" for V4.1.
+		    "qcom,llcc-v21" for V2.1 or "qcom,llcc-v31" for V3.1 or
+		    "qcom,llcc-v41" for V4.1.

 - reg:
 	Usage: required
--- a/bindings/interrupt-controller/qcom,mpm.txt
+++ b/bindings/interrupt-controller/qcom,mpm.txt
@@ -27,6 +27,7 @@ Properties:
 		"qcom,mpm-khaje"
 		"qcom,mpm-monaco"
 		"qcom,mpm-scuba"
+		"qcom,mpm-sa410m"

 - interrupts:
 	Usage: required
--- a/bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/bindings/pinctrl/qcom,pmic-gpio.txt
@@ -44,6 +44,7 @@ PMIC's from Qualcomm.
 		    "qcom,pmx55-gpio"
 		    "qcom,pmx65-gpio"
 		    "qcom,pmx75-gpio"
+		    "qcom,pmx35-gpio"
 		    "qcom,pm7550ba-gpio"
 		    "qcom,pm8550-gpio"
 		    "qcom,pm8550b-gpio"
@@ -53,6 +54,7 @@ PMIC's from Qualcomm.
 		    "qcom,pmr735d-gpio"
 		    "qcom,pm5100-gpio"
 		    "qcom,pm8775-gpio"
+		    "qcom,pm2250-gpio"

 		    And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
 		    if the device is on an spmi bus or an ssbi bus respectively
--- a/bindings/ptp/qcom,ptp-tsc.txt
+++ b/bindings/ptp/qcom,ptp-tsc.txt
@@ -23,9 +23,13 @@ Optional properties:
 - qcom,tsc-nsec-update: boolean property to indicate the TSC counters
 			have values in nanoseconds, rather than in secs
 			and nanoseconds.
- qcom,etu-event-sel: array of ETU slice numbers.
- qcom,etu-event-names: ETU slice names for the corresponding
-			event slice numbers.
+- qcom,etu-slice: array of ETU slice numbers corresponding to the ETU sel.
+		In case this property is not defined the sel number will be
+		considered as the slice number for ETU offset calculation.
+- qcom,etu-event-sel: array of ETU event sel numbers for the corresponding
+			ETU slice numbers.
+- qcom,etu-event-names: ETU event sel names for the corresponding
+			event sel numbers.
 - interrupts: interrupt numbers associated with the ETU slice.
 - interrupt-names: names corresponding to the above interrupt numbers.
 - pinctrl-<#> : pinctrl configurations
@@ -44,6 +48,7 @@ Example:
                assigned-clocks = <&gcc GCC_TSC_CNTR_CLK>, <&gcc GCC_TSC_ETU_CLK>;
                assigned-clock-rates = <500000000> , <500000000>;

+		qcom,etu-slice = <1 5>;
 		qcom,etu-event-sel = <1 3>;
 		qcom,etu-event-names = "gps_pps", "tod_pps";

--- a/bindings/regulator/rpmh-regulator.txt
+++ b/bindings/regulator/rpmh-regulator.txt
@@ -89,6 +89,14 @@ First Level Nodes - RPMh Interface
 		    parameters values will only be sent after some consumer
 		    makes a request.

+- qcom,disable-mode
+	Usage:      optional
+	Value type: <u32>
+	Definition: Specifies the mode to set for a VRM regulator when it gets disabled.
+		    The actual previously voted mode will be restored when the regulator
+		    is enabled.
+		    Supported values are RPMH_REGULATOR_MODE_* (i.e. 0 to 4).
+
 =========================================
 Second Level Nodes - Regulator Interfaces
 =========================================
--- a/bindings/thermal/qcom-spmi-adc-tm5.yaml
+++ b/bindings/thermal/qcom-spmi-adc-tm5.yaml
@@ -17,8 +17,20 @@ properties:
  reg:
    maxItems: 1

-  interrupts:
-    maxItems: 1
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,spmi-adc-tm5
+    then:
+      properties:
+        interrupts:
+          maxItems: 1
+      required:
+        - interrupts
+    else:
+      properties:
+        interrupts: false

  "#thermal-sensor-cells":
    const: 1
@@ -105,7 +117,6 @@ patternProperties:
 required:
  - compatible
  - reg
-  - interrupts
  - "#address-cells"
  - "#size-cells"
  - "#thermal-sensor-cells"
--- a/bindings/thermal/qti-virtual-sensor.txt
+++ b/bindings/thermal/qti-virtual-sensor.txt
@@ -0,0 +1,47 @@
+===================================================================
+VIRTUAL sensor driver
+===================================================================
+
+Virtual sensor driver will be used to give maximum or minimum temperature of set of thermal zones.
+Generally this set of thermal zones are categorized based on the sensor present on that subsytem.
+
+Properties:
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: must be "qcom,vs-sensor"
+
+	Virtual sensor driver properties:
+- qcom,sensors:
+	Usage: required
+	Value type: <List of Thermal Zones>
+	Definition: List of thermal zones whom maximum or minimum temperature need to find out.
+
+- qcom,logic:
+	Usage: optional
+	value type: <integer>
+	Definition: It can be 1 or 0. 1 is identifier for maximum temperature and 0 is identifier
+			for minimum temperature.
+
+- qcom,sensor_id:
+	Usage: optional
+	value type: <integer>
+	Definition: It will be 0,1,2.. depending upon how many thermal sensors are present in the target.
+
+Example:
+	virtual_sensor: virtual-sensor {
+		compatible = "qcom,vs-sensor";
+		#thermal-sensor-cells = <1>;
+
+		cpu_max: cpu-max{
+			qcom,sensors = <&cpuss_0 &cpuss_1 &cpuss_2 &cpuss_3>;
+			qcom,logic = <1>;
+			qcom,sensor_id = <0>;
+		};
+
+		modem_max: modem-max{
+			qcom,sensors = <&modem_offline &modem_q6 & modem_offline_fec &modem_offline_phy_0 &modem_offline_phy_1>;
+			qcom,logic = <1>;
+			qcom,sensor_id = <1>;
+		};
+	};
--- a/bindings/usb/qcom,msm-phy.txt
+++ b/bindings/usb/qcom,msm-phy.txt
@@ -160,3 +160,105 @@ Example:
 			 0x2c78 0x27>;

 	};
+
+QUSB2 High-Speed PHY
+
+Required properties:
+ - compatible: Should be "qcom,qusb2phy" or "qcom,qusb2phy-v2"
+ - reg: Address and length of the QUSB2 PHY register set
+ - reg-names: Should be "qusb_phy_base".
+ - <supply-name>-supply: phandle to the regulator device tree node
+   Required supplies are:
+	"vdd" : vdd supply for digital circuit operation
+	"vdda18" : 1.8v high-voltage analog supply
+	"vdda33" : 3.3v high-voltage analog supply
+	"refgen" : 1.2v high-voltage analog supply
+ - clocks: a list of phandles to the PHY clocks. Use as per
+   Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
+   property. "ref_clk_src" is a mandatory clock.
+ - qcom,vdd-voltage-level: This property must be a list of three integer
+   values (no, min, max) where each value represents either a voltage in
+   microvolts or a value corresponding to voltage corner
+ - phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode.
+ - resets: reset specifier pair consists of phandle for the reset controller
+   and reset lines used by this controller.
+ - reset-names: reset signal name strings sorted in the same order as the resets
+   property.
+ - qcom,qusb-phy-reg-offset: Provides important phy register offsets in an order defined in phy driver.
+
+Optional properties:
+ - reg-names: Additional registers corresponding with the following:
+   "efuse_addr": EFUSE address to read and update analog tune parameter.
+   "emu_phy_base" : phy base address used for programming emulation target phy.
+   "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset.
+   "tcsr_clamp_dig_n" : To enable/disable digital clamp to the phy. When
+   de-asserted, it will prevent random leakage from qusb2 phy resulting from
+   out of sequence turn on/off of 1p8, 3p3 and DVDD regulators.
+   "refgen_north_bg_reg" : address used to read REFGEN status for overriding QUSB PHY register.
+   "tcsr_conn_box_spare" : To enable/disable USB HS AC/DC coupling feature. When
+   enabled, DP/DM signals will take path through capacitor when USB HS device is
+   connected. This is a required property if 'qcom,usb-hs-ac-bitmask' property is present.
+ - clocks: a list of phandles to the PHY clocks. Use as per
+   Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
+   property. "cfg_ahb_clk" and "ref_clk" are optional clocks.
+ - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair.
+ - qcom,qusb-phy-host-init-seq: QUSB PHY initialization sequence for host mode
+   with value,reg pair.
+ - qcom,emu-init-seq : emulation initialization sequence with value,reg pair.
+ - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair.
+ - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair.
+ - qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register for "qcom,qusb2phy".
+ - qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble for "qcom,qusb2phy".
+ - qcom,efuse-bit-pos: start bit position within EFUSE register for "qcom,qusb2phy-v2".
+ - qcom,efuse-num-bits: Number of bits to read from EFUSE register for "qcom,qusb2phy-v2".
+ - qcom,emulation: Indicates that we are running on emulation platform.
+ - qcom,hold-reset: Indicates that hold QUSB PHY into reset state.
+ - qcom,phy-clk-scheme: Should be one of "cml" or "cmos" if ref_clk_addr is provided.
+ - qcom,major-rev: provide major revision number to differentiate power up sequence. default is 2.0
+ - pinctrl-names/pinctrl-0/1: The GPIOs configured as output function. Allowed names are
+   "default" and "sleep".
+ - qcom,tune2-efuse-correction: The value to be adjusted from fused value for
+   improved rise/fall times.
+ - qcom,host-chirp-erratum: Indicates host chirp fix is required.
+ - qcom,override-bias-ctrl2: Indicates override is done from driver for
+   BIAS_CTRL2 register.
+ - nvmem-cells: specifies the handle to represent the SoC revision.
+   usually it is defined by qfprom device node.
+ - nvmem-cell-names: specifies the given nvmem cell name as defined in
+   qfprom node.
+ - qcom,usb-hs-ac-bitmask: Specifies the polarity and enable bitfields in
+   tcsr_conn_box_spare register so as to enable USB HS AC/DC coupling feature.
+ - qcom,usb-hs-ac-value: Specifies the value to be written to polarity and
+   enable bitfields so as to enable USB HS AC/DC coupling feature. This is a
+   required property if 'qcom,usb-hs-ac-bitmask' property is present.
+
+Example:
+	qusb_phy: qusb@f9b39000 {
+		compatible = "qcom,qusb2phy";
+		reg = <0x00079000 0x7000>;
+		reg-names = "qusb_phy_base";
+		vdd-supply = <&pm8994_s2_corner>;
+		vdda18-supply = <&pm8994_l6>;
+		vdda33-supply = <&pm8994_l24>;
+		refgen-supply = <&pm8994_l21>;
+		qcom,vdd-voltage-level = <1 5 7>;
+		qcom,qusb-phy-reg-offset =
+			<0x240 /* QUSB2PHY_PORT_TUNE1 */
+			 0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */
+			 0x210 /* QUSB2PHY_PWR_CTRL1 */
+			 0x230 /* QUSB2PHY_INTR_CTRL */
+			 0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */
+			 0x254 /* QUSB2PHY_TEST1 */
+			 0x198>; /* QUSB2PHY_PLL_BIAS_CONTROL_2 */
+		qcom,efuse-bit-pos = <21>;
+		qcom,efuse-num-bits = <3>;
+
+		clocks = <&clock_rpm clk_ln_bb_clk>,
+			 clock_gcc clk_gcc_rx2_usb1_clkref_clk>,
+			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>;
+		clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk";
+		resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+	};
--- a/qcom/Makefile
+++ b/qcom/Makefile
@@ -63,7 +63,9 @@ KALAMA_BOARDS += \
 NOAPQ_KALAMA_BOARDS += \
 		 kalama-rumi-overlay.dtbo \
 		 kalama-pinn-cdp-overlay.dtbo \
-		 kalama-pinn-mtp-overlay.dtbo
+		 kalama-pinn-mtp-overlay.dtbo \
+		 kalama-baagha-cdp-overlay.dtbo \
+		 kalama-baagha-mtp-overlay.dtbo

 kalama-dtb-$(CONFIG_ARCH_KALAMA) += \
 	$(call add-overlays, $(KALAMA_BOARDS) $(NOAPQ_KALAMA_BOARDS),$(KALAMA_BASE_DTB))\
@@ -115,8 +117,6 @@ KHAJE_BOARDS += \
 		 khajeg-idp-pm8010-overlay.dtbo \
 		 khajeg-idps-display-90hz-overlay.dtbo

-
-
 bengal-dtb-$(CONFIG_ARCH_KHAJE) += \
        $(call add-overlays, $(KHAJE_BOARDS) ,$(KHAJE_BASE_DTB))
 bengal-overlays-dtb-$(CONFIG_ARCH_KHAJE) += $(KHAJE_BOARDS) $(KHAJE_BASE_DTB)
@@ -222,12 +222,17 @@ sdxpinn-dtb-$(CONFIG_ARCH_SDXPINN) += sdxpinn-rumi.dtb sa525m-rumi.dtb \
 		sdxpinn-idp-mbb.dtb
 dtb-y += $(sdxpinn-dtb-y)

+SA410M_AUTO_BASE_DTB += sa410m.dtb
+SA410M_AUTO_BOARDS += \
+		sa410m-rumi-overlay.dtbo \
+		sa410m-nand-idp-overlay.dtbo \
+		sa410m-emmc-idp-overlay.dtbo \
+		sa410m-nand-ccard-overlay.dtbo \
+		sa410m-emmc-ccard-overlay.dtbo
+
 sa410m_auto-dtb-$(CONFIG_ARCH_SA410M) += \
-				sa410m-rumi.dtb \
-				sa410m-nand-idp.dtb \
-				sa410m-emmc-idp.dtb \
-				sa410m-nand-ccard.dtb \
-				sa410m-emmc-ccard.dtb
+	$(call add-overlays, $(SA410M_AUTO_BOARDS) ,$(SA410M_AUTO_BASE_DTB))
+sa410m_auto-overlays-dtb-$(CONFIG_ARCH_SA410M) += $(SA410M_AUTO_BOARDS) $(SA410M_AUTO_BASE_DTB)
 dtb-y += $(sa410m_auto-dtb-y)

 SA8155_LA_GVM_BASE_DTB += sa8155-vm-la.dtb
@@ -240,11 +245,20 @@ DIREWOLF_LV_GVM_BASE_DTB += direwolf-vm-lv.dtb
 DIREWOLF_LV_GVM_BOARDS += \
                   direwolf-vm-lv-overlay.dtbo

+
+SA8195_LA_GVM_BASE_DTB += sa8195-vm-la.dtb
+
+SA8195_LA_GVM_BOARDS += \
+                   sa8195-vm-la-overlay.dtbo
+
 autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \
 	$(call add-overlays, $(SA8155_LA_GVM_BOARDS),$(SA8155_LA_GVM_BASE_DTB)) \
-	$(call add-overlays, $(DIREWOLF_LV_GVM_BOARDS),$(DIREWOLF_LV_GVM_BASE_DTB))
+	$(call add-overlays, $(DIREWOLF_LV_GVM_BOARDS),$(DIREWOLF_LV_GVM_BASE_DTB)) \
+	$(call add-overlays, $(SA8195_LA_GVM_BOARDS),$(SA8195_LA_GVM_BASE_DTB))
 autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += \
-	$(SA8155_LA_GVM_BOARDS) $(DIREWOLF_LV_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) $(DIREWOLF_LV_GVM_BASE_DTB)
+	$(SA8155_LA_GVM_BOARDS) $(DIREWOLF_LV_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) $(DIREWOLF_LV_GVM_BASE_DTB) \
+	$(SA8195_LA_GVM_BOARDS) $(SA8195_LA_GVM_BASE_DTB)
+
 dtb-y += $(autogvm-dtb-y)

 SCUBA_AUTO_BASE_DTB += scuba_auto.dtb
--- a/qcom/bengal-coresight.dtsi
+++ b/qcom/bengal-coresight.dtsi
--- a/qcom/cinder-thermal.dtsi
+++ b/qcom/cinder-thermal.dtsi
@@ -11,6 +11,21 @@
 		interrupt-names = "uplow","critical";
 		#thermal-sensor-cells = <1>;
 	};
+
+	virtual_sensor: virtual-sensor {
+		compatible = "qcom,vs-sensor";
+		#thermal-sensor-cells = <1>;
+
+		cpu_max: cpu-max {
+			qcom,sensors = <&cpuss_0 &cpuss_1 &cpuss_2 &cpuss_3>;
+			qcom,logic = <1>;
+		};
+
+		modem_max: modem-max {
+			qcom,sensors = <&modem_q6 &modem_offline_fec &modem_offline_phy_0 &modem_offline_phy_1 &modem_offline>;
+			qcom,logic = <1>;
+		};
+	};
 };

 &thermal_zones {
@@ -33,7 +48,7 @@
 		};
 	};

-	cpuss-0 {
+	cpuss_0: cpuss-0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 1>;
@@ -58,7 +73,7 @@
 		};
 	};

-	cpuss-1 {
+	cpuss_1: cpuss-1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 2>;
@@ -83,7 +98,7 @@
 		};
 	};

-	cpuss-2 {
+	cpuss_2: cpuss-2 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 3>;
@@ -108,7 +123,7 @@
 		};
 	};

-	cpuss-3 {
+	cpuss_3: cpuss-3 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 4>;
@@ -133,7 +148,7 @@
 		};
 	};

-	modem_q6 {
+	modem_q6: modem_q6 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 5>;
@@ -152,7 +167,7 @@
 		};
 	};

-	modem_offline_fec {
+	modem_offline_fec: modem_offline_fec {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 6>;
@@ -171,7 +186,7 @@
 		};
 	};

-	modem_offline_phy-0 {
+	modem_offline_phy_0: modem_offline_phy-0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 7>;
@@ -190,7 +205,7 @@
 		};
 	};

-	modem_offline_phy-1 {
+	modem_offline_phy_1: modem_offline_phy-1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 8>;
@@ -285,7 +300,7 @@
 		};
 	};

-	modem_offline {
+	modem_offline: modem_offline {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 13>;
@@ -341,4 +356,42 @@
 			};
 		};
 	};
+
+	cpuss_max {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&virtual_sensor 0>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modemss_max {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&virtual_sensor 1>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
 };
--- a/qcom/cinder.dtsi
+++ b/qcom/cinder.dtsi
@@ -29,6 +29,8 @@
 		hsuart1 = &qupv3_se8_4uart; /* IPC HSUART Instance */
 		hsuart2 = &qupv3_se13_4uart; /* Time Sync UART */
 		i2c0 = &qupv3_se5_i2c;
+		i2c1 = &i2c_slave;
+		i2c2 = &qupv3_se4_i2c;
 	};

 	firmware: firmware { };
@@ -618,7 +620,7 @@

 		qcom,signal-aop;
 		qcom,qmp = <&aoss_qmp>;
-		memory-region = <&mpss_mem>;
+		memory-region = <&mpss_mem &q6_mpss_dtb_mem &system_cma>;

 		/* Inputs from mss */
 		interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
@@ -1186,9 +1188,10 @@
 		clock-names = "cfg_ahb", "cntr", "etu";
 		assigned-clocks = <&gcc GCC_TSC_CNTR_CLK>, <&gcc GCC_TSC_ETU_CLK>;
 		assigned-clock-rates = <500000000>, <500000000>;
-		interrupts = <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
+		interrupts = <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>,
 			     <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
 		interrupt-names = "tod_pps", "gps_pps";
+		qcom,etu-slice = <1 5>;
 		qcom,etu-event-sel = <1 3>;
 		qcom,etu-event-names = "gps_pps", "tod_pps";
 		pinctrl-names = "default";
@@ -1586,6 +1589,14 @@
 	status = "ok";
 };

+&qupv3_se4_i2c {
+	status = "ok";
+};
+
+&i2c_slave {
+	status = "ok";
+};
+
 &qupv3_se7_2uart {
 	status = "ok";
 };
--- a/qcom/direwolf-vm-lv.dtsi
+++ b/qcom/direwolf-vm-lv.dtsi
@@ -1,2 +1,6 @@
 &soc {
 };
+
+&hab {
+	vmid = <3>;
+};
--- a/qcom/kalama-baagha-cdp-overlay.dts
+++ b/qcom/kalama-baagha-cdp-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include "kalama-cdp.dtsi"
+#include "sdxbaagha-external-soc.dtsi"
+#include "kalama-baagha.dtsi"
+
+/ {
+	model = "KALAMA BAAGHA CDP";
+	compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp";
+	qcom,msm-id = <519 0x10000>, <536 0x10000>;
+	qcom,board-id = <0x04010001 0x4>;
+};
--- a/qcom/kalama-baagha-mtp-overlay.dts
+++ b/qcom/kalama-baagha-mtp-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include "kalama-mtp.dtsi"
+#include "sdxbaagha-external-soc.dtsi"
+#include "kalama-baagha.dtsi"
+
+/ {
+	model = "KALAMA BAAGHA MTP";
+	compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp";
+	qcom,msm-id = <519 0x10000>, <536 0x10000>;
+	qcom,board-id = <0x03010008 0x3>;
+};
--- a/qcom/kalama-baagha.dtsi
+++ b/qcom/kalama-baagha.dtsi
@@ -0,0 +1,8 @@
+&mdm0 {
+	compatible = "qcom,ext-baagha";
+	qcom,mdm-link-info = "011a_01.01.00";
+};
+
+&modem_pas {
+	status = "disabled";
+};
--- a/qcom/kalama-pinn-cdp-overlay.dts
+++ b/qcom/kalama-pinn-cdp-overlay.dts
@@ -8,6 +8,6 @@
 / {
 	model = "KALAMA PINN CDP";
 	compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp";
-	qcom,msm-id = <519 0x10000>;
+	qcom,msm-id = <519 0x10000>, <536 0x10000>;
 	qcom,board-id = <0x03010001 0x3>;
 };
--- a/qcom/kalama-pinn-mtp-overlay.dts
+++ b/qcom/kalama-pinn-mtp-overlay.dts
@@ -8,6 +8,6 @@
 / {
 	model = "KALAMA PINN MTP";
 	compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp";
-	qcom,msm-id = <519 0x10000>;
+	qcom,msm-id = <519 0x10000>, <536 0x10000>;
 	qcom,board-id = <0x02010008 0x2>;
 };
--- a/qcom/kalama-sg-hhg.dtsi
+++ b/qcom/kalama-sg-hhg.dtsi
@@ -81,6 +81,16 @@
 	qcom,init-voltage = <2800000>;
 };

+&regulator_ocp_notifier {
+	/delete-property/ periph-c40-supply;
+	/delete-property/ periph-c41-supply;
+	/delete-property/ periph-c42-supply;
+	/delete-property/ periph-c43-supply;
+	/delete-property/ periph-c44-supply;
+	/delete-property/ periph-c45-supply;
+	/delete-property/ periph-c46-supply;
+};
+
 &usb_qmp_dp_phy {
 	pinctrl-names = "default";
 };
--- a/qcom/kalama-vm.dtsi
+++ b/qcom/kalama-vm.dtsi
@@ -106,7 +106,7 @@
 		vendor = "QTI";
 		image-name = "qcom,trustedvm";
 		qcom,pasid = <0x0 0x1c>;
-		qcom,qtee-config-info = "p=77,78,7C,8F,97,159,199,47E,7F1;";
+		qcom,qtee-config-info = "p=39,77,78,7C,8F,97,159,199,47E,7F1;";
 		qcom,secdomain-ids = <45>;
 		qcom,primary-vm-index = <0>;
 		vm-uri = "vmuid/trusted-ui";
--- a/qcom/kalama.dtsi
+++ b/qcom/kalama.dtsi
@@ -479,10 +479,10 @@
 		reg = <0x0 0xd4d00000 0x0 0x3300000>;
 	};

-	tz_reserved_mem: tz_reserved_region@d8000000 {
-		no-map;
-		reg = <0x0 0xd8000000 0x0 0x100000>;
-	};
+	/*
+	 * tz_reserved_mem not passed to linux as valid memory. Size
+	 * varies based on bootloader policy.
+	 */

 	xbl_sc_mem: xbl_sc_region@d8100000 {
 		no-map;
--- a/qcom/kalamap-sg-hhg.dtsi
+++ b/qcom/kalamap-sg-hhg.dtsi
@@ -15,3 +15,18 @@
 	vreg-3p3-supply = <&nvme_vreg>;
 	qcom,boot-option = <0x2>;
 };
+
+&regulator_ocp_notifier {
+	/delete-property/ periph-ac1-supply;
+	/delete-property/ periph-ac2-supply;
+	/delete-property/ periph-ac3-supply;
+	/delete-property/ periph-ac4-supply;
+	/delete-property/ periph-ac5-supply;
+	/delete-property/ periph-ac6-supply;
+	/delete-property/ periph-ac7-supply;
+	/delete-property/ periph-bc3-supply;
+	/delete-property/ periph-bc4-supply;
+	/delete-property/ periph-bc5-supply;
+	/delete-property/ periph-bc6-supply;
+	/delete-property/ periph-bc7-supply;
+};
--- a/qcom/khaje-atp-overlay.dts
+++ b/qcom/khaje-atp-overlay.dts
@@ -7,7 +7,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. Khaje ATP";
 	compatible = "qcom,khaje-atp", "qcom,khaje", "qcom,atp";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <33 0>;
 	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
 };
--- a/qcom/khaje-idp-nopmi-overlay.dts
+++ b/qcom/khaje-idp-nopmi-overlay.dts
@@ -7,7 +7,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. KHAJE IDP nopmi";
 	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0x10022 0>;
 	qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
 };
--- a/qcom/khaje-idp-overlay.dts
+++ b/qcom/khaje-idp-overlay.dts
@@ -8,7 +8,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. Khaje IDP";
 	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0x10022 0>;
 	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
 };
--- a/qcom/khaje-idp-pm8010-overlay.dts
+++ b/qcom/khaje-idp-pm8010-overlay.dts
@@ -8,7 +8,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. Khaje IDP with PM8010";
 	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0x10222 0>;
 	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
 };
--- a/qcom/khaje-idp-usbc-overlay.dts
+++ b/qcom/khaje-idp-usbc-overlay.dts
@@ -8,7 +8,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. KHAJE IDP USBC Audio";
 	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0x1010022 0>;
 	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
 };
--- a/qcom/khaje-idp-usbc.dts
+++ b/qcom/khaje-idp-usbc.dts
@@ -7,7 +7,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. KHAJE IDP USBC Audio";
 	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0x1010022 0>;
 	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
 };
--- a/qcom/khaje-idps-display-90hz-overlay.dts
+++ b/qcom/khaje-idps-display-90hz-overlay.dts
@@ -9,7 +9,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. KHAJE IDPS + 90Hz";
 	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0x10122 0>;
 	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
 };
--- a/qcom/khaje-qrd-hvdcp3p5-overlay.dts
+++ b/qcom/khaje-qrd-hvdcp3p5-overlay.dts
@@ -9,7 +9,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. Khaje QRD HVDCP3P5";
 	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0x1010B 0>;
 	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
 };
--- a/qcom/khaje-qrd-nopmi-overlay.dts
+++ b/qcom/khaje-qrd-nopmi-overlay.dts
@@ -7,7 +7,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. KHAJE QRD nopmi overlay";
 	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0x1000B 0>;
 	qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
 };
--- a/qcom/khaje-qrd-nowcd9375-overlay.dts
+++ b/qcom/khaje-qrd-nowcd9375-overlay.dts
@@ -9,7 +9,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. Khaje QRD NOWCD9375";
 	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0x2010B 0>;
 	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
 };
--- a/qcom/khaje-qrd-overlay.dts
+++ b/qcom/khaje-qrd-overlay.dts
@@ -8,7 +8,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. Khaje QRD";
 	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0x1000B 0>;
 	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
 };
--- a/qcom/khaje.dtsi
+++ b/qcom/khaje.dtsi
@@ -11,12 +11,13 @@
 / {
 	model = "Qualcomm Technologies, Inc. Khaje SoC";
 	compatible = "qcom,khaje";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	interrupt-parent = <&intc>;

 	#address-cells = <2>;
 	#size-cells = <2>;
 	memory { device_type = "memory"; reg = <0 0 0 0>; };
+	ddr-regions { };

 	mem-offline {
 		compatible = "qcom,mem-offline";
--- a/qcom/lemans-dma-heaps.dtsi
+++ b/qcom/lemans-dma-heaps.dtsi
@@ -0,0 +1,52 @@
+#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
+
+&soc {
+	qcom,dma-heaps {
+
+		compatible = "qcom,dma-heaps";
+
+		qcom,qseecom {
+			qcom,dma-heap-name = "qcom,qseecom";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_mem>;
+		};
+
+		qcom,qseecom_ta {
+			qcom,dma-heap-name = "qcom,qseecom-ta";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_ta_mem>;
+		};
+
+		qcom,display {
+			qcom,dma-heap-name = "qcom,display";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			qcom,max-align = <9>;
+			memory-region = <&non_secure_display_memory>;
+		};
+
+		qcom,adsp {
+			qcom,dma-heap-name = "qcom,adsp";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&adsp_mem>;
+		};
+
+		qcom,secure_cdsp {
+			qcom,dma-heap-name = "qcom,secure-cdsp";
+			qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
+			memory-region = <&cdsp_secure_mem>;
+			qcom,token = <0x20000000>;
+		};
+
+		qcom,sp_hlos {
+			qcom,dma-heap-name = "qcom,sp-hlos";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&sp_mem>;
+		};
+
+		qcom,user_contig {
+			qcom,dma-heap-name = "qcom,user-contig";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&user_contig_mem>;
+		};
+	};
+};
--- a/qcom/lemans-pcie.dtsi
+++ b/qcom/lemans-pcie.dtsi
@@ -0,0 +1,584 @@
+#include <dt-bindings/clock/qcom,gcc-lemans.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&soc {
+	pcie0: qcom,pcie@0x01c00000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c00000 0x3000>,
+			<0x1c04000 0x2000>,
+			<0x40000000 0xf20>,
+			<0x40000f20 0xa8>,
+			<0x40001000 0x4000>,
+			<0x40100000 0x100000>,
+			<0x01c03000 0x1000>;
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "mhi";
+
+		cell-index = <0>;
+		linux,pci-domain = <0>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
+			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
+
+		interrupt-parent = <&pcie0>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+
+		perst-gpio = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+		wake-gpio = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pcie0_perst_default
+				&pcie0_clkreq_default
+				&pcie0_wake_default>;
+		pinctrl-1 = <&pcie0_perst_default
+				&pcie0_clkreq_sleep
+				&pcie0_wake_default>;
+
+		gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
+		vreg-1p2-supply = <&L1C>;
+		vreg-0p9-supply = <&L5A>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+		vreg-mx-supply = <&VDD_MXC_LEVEL>;
+
+		qcom,vreg-1p8-voltage-level = <1200000 1200000 25800>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 186000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_SVS_L1
+				RPMH_REGULATOR_LEVEL_SVS_L1
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_SVS_L1
+				RPMH_REGULATOR_LEVEL_SVS_L1
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_SVS_L1
+				RPMH_REGULATOR_LEVEL_SVS_L1
+				100000000
+				/* Gen4 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_0_AUX_CLK>,
+			<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_CLKREF_EN>,
+			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+			<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+			<&gcc GCC_PCIE_0_PHY_AUX_CLK>,
+			<&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
+			<&pcie_0_pipe_clk>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
+				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
+				"pcie_0_ldo",
+				"pcie_0_slv_q2a_axi_clk", "pcie_phy_refgen_clk",
+				"pcie_pipe_clk_mux", "pcie_phy_aux_clk",
+				"pcie_0_pipediv2_clk",
+				"pcie_pipe_clk_ext_src";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <100000000>, <0>,
+					<0>, <0>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+								<0>, <0>, <0>, <0>, <0>, <0>;
+
+
+		resets = <&gcc GCC_PCIE_0_BCR>,
+			<&gcc GCC_PCIE_0_PHY_BCR>;
+		reset-names = "pcie_0_core_reset",
+				"pcie_0_phy_reset";
+
+		dma-coherent;
+		msi-map = <0x0 &gic_its 0x5000 0x1>,
+			<0x100 &gic_its 0x5001 0x1>;
+
+		qcom,smmu-sid-base = <0x0000>;
+		iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
+			<0x100 &pcie_smmu 0x0001 0x1>,
+			<0x200 &pcie_smmu 0x0002 0x1>,
+			<0x300 &pcie_smmu 0x0003 0x1>,
+			<0x400 &pcie_smmu 0x0004 0x1>,
+			<0x500 &pcie_smmu 0x0005 0x1>,
+			<0x600 &pcie_smmu 0x0006 0x1>,
+			<0x700 &pcie_smmu 0x0007 0x1>,
+			<0x800 &pcie_smmu 0x0008 0x1>,
+			<0x900 &pcie_smmu 0x0009 0x1>,
+			<0xa00 &pcie_smmu 0x000a 0x1>,
+			<0xb00 &pcie_smmu 0x000b 0x1>,
+			<0xc00 &pcie_smmu 0x000c 0x1>,
+			<0xd00 &pcie_smmu 0x000d 0x1>,
+			<0xe00 &pcie_smmu 0x000e 0x1>,
+			<0xf00 &pcie_smmu 0x000f 0x1>;
+
+		qcom,boot-option = <0x0>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,slv-addr-space-size = <0x1fd00000>;
+		qcom,ep-latency = <10>;
+		qcom,core-preset = <0x77777777>;
+
+		qcom,pcie-phy-ver = <109>;
+		qcom,phy-status-offset = <0x1214>;
+		qcom,phy-status-bit = <7>;
+		qcom,phy-power-down-offset = <0x1240>;
+		qcom,phy-sequence = <0x1240 0x03 0x0
+				0x1010 0x00 0x0
+				0x101c 0x31 0x0
+				0x1020 0x01 0x0
+				0x1024 0xde 0x0
+				0x1028 0x07 0x0
+				0x1030 0x97 0x0
+				0x1034 0x0c 0x0
+				0x1044 0x14 0x0
+				0x1048 0x90 0x0
+				0x1058 0x0f 0x0
+				0x1074 0x06 0x0
+				0x1078 0x06 0x0
+				0x107c 0x16 0x0
+				0x1080 0x16 0x0
+				0x1084 0x36 0x0
+				0x1088 0x36 0x0
+				0x1094 0x08 0x0
+				0x10a4 0x46 0x0
+				0x10a8 0x04 0x0
+				0x10ac 0x0a 0x0
+				0x10b0 0x1a 0x0
+				0x10b4 0x14 0x0
+				0x10b8 0x34 0x0
+				0x10bc 0x82 0x0
+				0x10c4 0xd0 0x0
+				0x10cc 0x55 0x0
+				0x10d0 0x55 0x0
+				0x10d4 0x03 0x0
+				0x10d8 0x55 0x0
+				0x10dc 0x55 0x0
+				0x10e0 0x05 0x0
+				0x110c 0x02 0x0
+				0x1154 0x34 0x0
+				0x1158 0x12 0x0
+				0x115c 0x00 0x0
+				0x1168 0x0a 0x0
+				0x116c 0x04 0x0
+				0x119c 0x88 0x0
+				0x1174 0x60 0x0
+				0x117c 0x06 0x0
+				0x11a0 0x14 0x0
+				0x11a8 0x0f 0x0
+				0x0220 0x16 0x0
+				0x03c0 0x38 0x0
+				0x0a20 0x16 0x0
+				0x0bc0 0x38 0x0
+				0x0360 0x9a 0x0
+				0x0364 0xb0 0x0
+				0x0368 0x92 0x0
+				0x036c 0xf0 0x0
+				0x0370 0x42 0x0
+				0x0374 0x99 0x0
+				0x0378 0x29 0x0
+				0x037c 0x9a 0x0
+				0x0380 0xfb 0x0
+				0x0384 0x92 0x0
+				0x0388 0xec 0x0
+				0x038c 0x43 0x0
+				0x0390 0xdd 0x0
+				0x0394 0x0d 0x0
+				0x0398 0xf3 0x0
+				0x039c 0xf8 0x0
+				0x03a0 0xec 0x0
+				0x03a4 0xd6 0x0
+				0x03a8 0x83 0x0
+				0x03ac 0xf5 0x0
+				0x03b0 0x5e 0x0
+				0x0b60 0x9a 0x0
+				0x0b64 0xb0 0x0
+				0x0b68 0x92 0x0
+				0x0b6c 0xf0 0x0
+				0x0b70 0x42 0x0
+				0x0b74 0x99 0x0
+				0x0b78 0x29 0x0
+				0x0b7c 0x9a 0x0
+				0x0b80 0xfb 0x0
+				0x0b84 0x92 0x0
+				0x0b88 0xec 0x0
+				0x0b8c 0x43 0x0
+				0x0b90 0xdd 0x0
+				0x0b94 0x0d 0x0
+				0x0b98 0xf3 0x0
+				0x0b9c 0xf8 0x0
+				0x0ba0 0xec 0x0
+				0x0ba4 0xd6 0x0
+				0x0ba8 0x83 0x0
+				0x0bac 0xf5 0x0
+				0x0bb0 0x5e 0x0
+				0x03b4 0x20 0x0
+				0x022c 0x3f 0x0
+				0x0230 0x37 0x0
+				0x0bb4 0x20 0x0
+				0x0a2c 0x3f 0x0
+				0x0a30 0x37 0x0
+				0x0078 0x05 0x0
+				0x007c 0xf6 0x0
+				0x0080 0x0f 0x0
+				0x0878 0x05 0x0
+				0x087c 0xf6 0x0
+				0x0880 0x0f 0x0
+				0x0290 0x00 0x0
+				0x0a90 0x00 0x0
+				0x03f8 0x1f 0x0
+				0x0400 0x1f 0x0
+				0x0408 0x1f 0x0
+				0x0410 0x1f 0x0
+				0x0418 0x1f 0x0
+				0x0420 0x1f 0x0
+				0x03f4 0x1f 0x0
+				0x03fc 0x1f 0x0
+				0x0404 0x1f 0x0
+				0x0bf8 0x1f 0x0
+				0x0c00 0x1f 0x0
+				0x0c08 0x1f 0x0
+				0x0c10 0x1f 0x0
+				0x0c18 0x1f 0x0
+				0x0c20 0x1f 0x0
+				0x0bf4 0x1f 0x0
+				0x0bfc 0x1f 0x0
+				0x0c04 0x1f 0x0
+				0x0438 0x09 0x0
+				0x0c38 0x09 0x0
+				0x0208 0x0c 0x0
+				0x0a08 0x0c 0x0
+				0x020c 0x08 0x0
+				0x0a0c 0x08 0x0
+				0x021c 0x04 0x0
+				0x0a1c 0x04 0x0
+				0x02d4 0x04 0x0
+				0x0ad4 0x04 0x0
+				0x02dc 0x08 0x0
+				0x0adc 0x08 0x0
+				0x0308 0x0b 0x0
+				0x0b08 0x0b 0x0
+				0x0318 0x7c 0x0
+				0x0b18 0x7c 0x0
+				0x027c 0x10 0x0
+				0x0a7c 0x10 0x0
+				0x02b4 0x00 0x0
+				0x0ab4 0x00 0x0
+				0x02ec 0x05 0x0
+				0x0aec 0x05 0x0
+				0x02c4 0x00 0x0
+				0x02c8 0x1f 0x0
+				0x0ac4 0x00 0x0
+				0x0ac8 0x1f 0x0
+				0x0030 0x1f 0x0
+				0x0034 0x07 0x0
+				0x0830 0x1f 0x0
+				0x0834 0x07 0x0
+				0x141c 0xc1 0x0
+				0x1490 0x00 0x0
+				0x13e0 0x16 0x0
+				0x13e4 0x22 0x0
+				0x1508 0x02 0x0
+				0x14a0 0x16 0x0
+				0x1584 0x28 0x0
+				0x1370 0x2e 0x0
+				0x155c 0x2e 0x0
+				0x140c 0x1d 0x0
+				0x1388 0x66 0x0
+				0x1e24 0x00 0x0
+				0x1e28 0x00 0x0
+				0x1828 0x00 0x0
+				0x1c28 0x00 0x0
+				0x127c 0x00 0x0
+				0x1260 0x00 0x0
+				0x1200 0x00 0x0
+				0x1244 0x03 0x0>;
+
+		pcie0_rp: pcie0_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie1: qcom,pcie@0x01c10000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c10000 0x3000>,
+			<0x01c14000 0x4000>,
+			<0x60000000 0xf20>,
+			<0x60000f20 0xa8>,
+			<0x60001000 0x4000>,
+			<0x60100000 0x100000>,
+			<0x01c13000 0x1000>;
+		reg-names = "parf", "phy", "dm_core",
+				"elbi", "iatu", "conf", "mhi";
+
+		cell-index = <1>;
+		linux,pci-domain = <1>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
+			<0x02000000 0x0  0x60300000 0x60300000 0x0 0x1fd00000>;
+
+		interrupt-parent = <&pcie1>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+
+		perst-gpio = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+		wake-gpio = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pcie1_perst_default
+				&pcie1_clkreq_default
+				&pcie1_wake_default>;
+		pinctrl-1 = <&pcie1_perst_default
+				&pcie1_clkreq_sleep
+				&pcie1_wake_default>;
+
+		gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>;
+		vreg-1p2-supply = <&L1C>;
+		vreg-0p9-supply = <&L5A>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+		vreg-mx-supply = <&VDD_MXC_LEVEL>;
+
+		qcom,vreg-1p8-voltage-level = <1200000 1200000 33300>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 439000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_SVS_L1
+				RPMH_REGULATOR_LEVEL_SVS_L1
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_SVS_L1
+				RPMH_REGULATOR_LEVEL_SVS_L1
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_SVS_L1
+				RPMH_REGULATOR_LEVEL_SVS_L1
+				100000000
+				/* Gen4 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&pcie_anoc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_1_AUX_CLK>,
+			<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_CLKREF_EN>,
+			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+			<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
+			<&gcc GCC_PCIE_1_PHY_AUX_CLK>,
+			<&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
+			<&pcie_1_pipe_clk>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
+				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
+				"pcie_1_ldo",
+				"pcie_1_slv_q2a_axi_clk", "pcie_phy_refgen_clk",
+				"pcie_pipe_clk_mux", "pcie_phy_aux_clk",
+				"pcie_1_pipediv2_clk",
+				"pcie_pipe_clk_ext_src";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <100000000>, <0>,
+					<0>, <0>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+								<0>, <0>, <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_1_BCR>,
+			<&gcc GCC_PCIE_1_PHY_BCR>;
+		reset-names = "pcie_1_core_reset",
+				"pcie_1_phy_reset";
+
+		dma-coherent;
+		msi-map = <0x0 &gic_its 0x5080 0x1>,
+			<0x100 &gic_its 0x5081 0x1>;
+		qcom,smmu-sid-base = <0x0080>;
+		iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
+			<0x100 &pcie_smmu 0x0081 0x1>,
+			<0x200 &pcie_smmu 0x0082 0x1>,
+			<0x300 &pcie_smmu 0x0083 0x1>,
+			<0x400 &pcie_smmu 0x0084 0x1>,
+			<0x500 &pcie_smmu 0x0085 0x1>,
+			<0x600 &pcie_smmu 0x0086 0x1>,
+			<0x700 &pcie_smmu 0x0087 0x1>,
+			<0x800 &pcie_smmu 0x0088 0x1>,
+			<0x900 &pcie_smmu 0x0089 0x1>,
+			<0xa00 &pcie_smmu 0x008a 0x1>,
+			<0xb00 &pcie_smmu 0x008b 0x1>,
+			<0xc00 &pcie_smmu 0x008c 0x1>,
+			<0xd00 &pcie_smmu 0x008d 0x1>,
+			<0xe00 &pcie_smmu 0x008e 0x1>,
+			<0xf00 &pcie_smmu 0x008f 0x1>;
+
+		qcom,boot-option = <0x0>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,slv-addr-space-size = <0x1fd00000>;
+		qcom,ep-latency = <10>;
+		qcom,core-preset = <0x77777777>;
+
+		qcom,pcie-phy-ver = <1093>;
+		qcom,phy-status-offset = <0x2214>;
+		qcom,phy-status-bit = <7>;
+		qcom,phy-power-down-offset = <0x2240>;
+
+		qcom,phy-sequence = <0x2240 0x03 0x0
+				0x2010 0x00 0x0
+				0x201c 0x31 0x0
+				0x2020 0x01 0x0
+				0x2024 0xde 0x0
+				0x2028 0x07 0x0
+				0x2030 0x97 0x0
+				0x2034 0x0c 0x0
+				0x2044 0x1c 0x0
+				0x2048 0x90 0x0
+				0x2058 0x0f 0x0
+				0x2074 0x06 0x0
+				0x2078 0x06 0x0
+				0x207c 0x16 0x0
+				0x2080 0x16 0x0
+				0x2084 0x36 0x0
+				0x2088 0x36 0x0
+				0x2094 0x08 0x0
+				0x20a4 0x46 0x0
+				0x20a8 0x04 0x0
+				0x20ac 0x0a 0x0
+				0x20b0 0x1a 0x0
+				0x20b4 0x14 0x0
+				0x20b8 0x34 0x0
+				0x20bc 0x82 0x0
+				0x20c4 0xd0 0x0
+				0x20cc 0x55 0x0
+				0x20d0 0x55 0x0
+				0x20d4 0x03 0x0
+				0x20d8 0x55 0x0
+				0x20dc 0x55 0x0
+				0x20e0 0x05 0x0
+				0x210c 0x02 0x0
+				0x2154 0x34 0x0
+				0x2158 0x12 0x0
+				0x215c 0x00 0x0
+				0x2168 0x0a 0x0
+				0x216c 0x04 0x0
+				0x219c 0x88 0x0
+				0x2174 0x60 0x0
+				0x217c 0x06 0x0
+				0x21a0 0x14 0x0
+				0x21a8 0x0f 0x0
+				0x3a2c 0x3f 0x0
+				0x3a30 0x37 0x0
+				0x3a90 0x00 0x0
+				0x3bc0 0x38 0x0
+				0x3ab4 0x00 0x0
+				0x3aec 0x05 0x0
+				0x3bb4 0x20 0x0
+				0x3b08 0x0b 0x0
+				0x3b18 0x7c 0x0
+				0x3a7c 0x10 0x0
+				0x3bf4 0x1f 0x0
+				0x3bf8 0x1f 0x0
+				0x3bfc 0x1f 0x0
+				0x3c00 0x1f 0x0
+				0x3c04 0x1f 0x0
+				0x3c08 0x1f 0x0
+				0x3c10 0x1f 0x0
+				0x3c18 0x1f 0x0
+				0x3c20 0x1f 0x0
+				0x3c38 0x09 0x0
+				0x3b60 0x9a 0x0
+				0x3b64 0xb0 0x0
+				0x3b68 0x92 0x0
+				0x3b6c 0xf0 0x0
+				0x3b70 0x42 0x0
+				0x3b74 0x99 0x0
+				0x3b78 0x29 0x0
+				0x3b7c 0x9a 0x0
+				0x3b80 0xb6 0x0
+				0x3b84 0x92 0x0
+				0x3b88 0xf0 0x0
+				0x3b8c 0x43 0x0
+				0x3b90 0xdd 0x0
+				0x3b94 0x0d 0x0
+				0x3b98 0xf3 0x0
+				0x3b9c 0xf6 0x0
+				0x3ba0 0xee 0x0
+				0x3ba4 0xd2 0x0
+				0x3ba8 0x83 0x0
+				0x3bac 0xf9 0x0
+				0x3bb0 0x3d 0x0
+				0x3ac4 0x00 0x0
+				0x3ac8 0x1f 0x0
+				0x3a08 0x0c 0x0
+				0x3a0c 0x08 0x0
+				0x3a1c 0x04 0x0
+				0x3a20 0x16 0x0
+				0x3ad4 0x04 0x0
+				0x3adc 0x08 0x0
+				0x3878 0x05 0x0
+				0x387c 0xf6 0x0
+				0x3880 0x0f 0x0
+				0x3834 0x07 0x0
+				0x3830 0x1f 0x0
+				0x241c 0xc1 0x0
+				0x2490 0x00 0x0
+				0x23e0 0x16 0x0
+				0x23e4 0x22 0x0
+				0x2508 0x02 0x0
+				0x24a0 0x16 0x0
+				0x2584 0x28 0x0
+				0x2370 0x2e 0x0
+				0x255c 0x2e 0x0
+				0x2388 0x66 0x0
+				0x240c 0x1d 0x0
+				0x2200 0x00 0x0
+				0x2244 0x03 0x0>;
+
+		pcie1_rp: pcie1_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+};
+
--- a/qcom/lemans-pinctrl.dtsi
+++ b/qcom/lemans-pinctrl.dtsi
@@ -1470,4 +1470,112 @@
 			};
 		};
 	};
+
+	pcie0 {
+		pcie0_perst_default: pcie0_perst_default {
+			mux {
+				pins = "gpio2";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio2";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie0_clkreq_default: pcie0_clkreq_default {
+			mux {
+				pins = "gpio1";
+				function = "pcie0_clkreq";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie0_wake_default: pcie0_wake_default {
+			mux {
+				pins = "gpio0";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie0_clkreq_sleep: pcie0_clkreq_sleep {
+			mux {
+				pins = "gpio1";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	pcie1 {
+		pcie1_perst_default: pcie1_perst_default {
+			mux {
+				pins = "gpio4";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie1_clkreq_default: pcie1_clkreq_default {
+			mux {
+				pins = "gpio3";
+				function = "pcie1_clkreq";
+			};
+
+			config {
+				pins = "gpio3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie1_wake_default: pcie1_wake_default {
+			mux {
+				pins = "gpio5";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie1_clkreq_sleep: pcie1_clkreq_sleep {
+			mux {
+				pins = "gpio3";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
 };
--- a/qcom/lemans-rumi.dtsi
+++ b/qcom/lemans-rumi.dtsi
@@ -9,3 +9,31 @@

 &soc {
 };
+
+&soc {
+	usb_emu_phy_0: usb_emu_phy@a784000 {
+		compatible = "qcom,usb-emu-phy";
+		reg = <0x0a784000 0x9500>;
+
+		qcom,emu-init-seq = <0xfffff 0x4
+				     0x2110010 0x34
+				     0x0110010 0x34
+				     0xffff3 0x4
+				     0xffff0 0x4
+				     0x100000 0x20
+				     0x0 0x20
+				     0x1A0 0x20
+				     0x100000 0x3c
+				     0x0 0x3c
+				     0x10060 0x3c
+				     0x0 0x4
+				     0x9 0x14>;
+	};
+};
+
+&usb0 {
+	dwc3@a600000 {
+		usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
+		maximum-speed = "high-speed";
+	};
+};
--- a/qcom/lemans-usb.dtsi
+++ b/qcom/lemans-usb.dtsi
@@ -0,0 +1,502 @@
+#include <dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h>
+#include <dt-bindings/clock/qcom,gcc-lemans.h>
+
+&soc {
+	usb0: ssusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa600000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq";
+
+		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
+		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,core-clk-rate-disconnected = <133333333>;
+		qcom,pm-qos-latency = <2>;
+
+		qcom,host-poweroff-in-pm-suspend;
+
+		interconnect-names = "usb-ddr", "ddr-usb";
+		interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
+				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
+
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0xa600000 0xd93c>;
+			iommus = <&apps_smmu 0x080 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+			interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy0>, <&usb_qmp_phy0>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,is-utmi-l1-suspend;
+			snps,usb2-gadget-lpm-disable;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,ssp-u3-u0-quirk;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "otg";
+		};
+	};
+
+	/* Primary USB port related High Speed PHY */
+	usb2_phy0: hsphy@88e4000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e4000 0x120>,
+			<0x088e3000 0x4>;
+		reg-names = "hsusb_phy_base",
+			"eud_enable_reg";
+
+		vdd-supply = <&L7A>;
+		vdda18-supply = <&L6C>;
+		vdda33-supply = <&L9A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+	};
+
+	/* Primary USB port related QMP PHY */
+	usb_qmp_phy0: ssphy@88e8000 {
+		compatible = "qcom,usb-ssphy-qmp-v2";
+		reg = <0x88e8000 0x2000>,
+		    <0x088e828c 0x4>;
+		reg-names = "qmp_phy_base",
+			"pcs_clamp_enable_reg";
+
+		vdd-supply = <&L7A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&L1C>;
+
+		clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
+			 <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>,
+			 <&rpmhcc RPMH_CXO_CLK>,
+			 <&gcc GCC_USB_CLKREF_EN>,
+			 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"ref_clk", "com_aux_clk";
+
+		resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+				<&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
+		reset-names = "phy_reset", "phy_phy_reset";
+
+		qcom,qmp-phy-reg-offset =
+				<USB3_UNI_PCS_PCS_STATUS1
+				USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
+				USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+				USB3_UNI_PCS_POWER_DOWN_CONTROL
+				USB3_UNI_PCS_SW_RESET
+				USB3_UNI_PCS_START_CONTROL>;
+
+		qcom,qmp-phy-init-seq =
+				/* <reg_offset, value> */
+				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL	0x1A
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL	0x11
+				USB3_UNI_QSERDES_COM_HSCLK_SEL	0x01
+				USB3_UNI_QSERDES_COM_DEC_START_MODE0	0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0	0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0	0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0	0x02
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1E
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0	0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0	0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0	0x36
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0	0x24
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0	0x34
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0	0x14
+				USB3_UNI_QSERDES_COM_LOCK_CMP_EN	0x04
+				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE	0x0A
+				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1	0x02
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1	0x24
+				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1	0x08
+				USB3_UNI_QSERDES_COM_DEC_START_MODE1	0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1	0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1	0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1	0x02
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1	0x82
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1	0x34
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1	0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1	0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1	0x36
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1E
+				USB3_UNI_QSERDES_COM_SSC_EN_CENTER	0x01
+				USB3_UNI_QSERDES_COM_SSC_PER1	0x31
+				USB3_UNI_QSERDES_COM_SSC_PER2	0x01
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1	0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1	0x07
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0	0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0	0x07
+				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP	0x02
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4	0xDC
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3	0xBD
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2	0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH	0x7F
+				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW	0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4	0xA9
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3	0x7B
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2	0xE4
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH	0x24
+				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW	0x64
+				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS	0x99
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1	0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2	0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1	0x00
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2	0x04
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN	0x2F
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW	0xFF
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	0x0F
+				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN	0x0A
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1	0x54
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2	0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2	0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4	0x0A
+				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x47
+				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	0x80
+				USB3_UNI_QSERDES_RX_SIGDET_CNTRL	0x04
+				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL	0x0E
+				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	0x38
+				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN	0x05
+				USB3_UNI_QSERDES_RX_GM_CAL	0x00
+				USB3_UNI_QSERDES_RX_SIGDET_ENABLES	0x00
+				USB3_UNI_QSERDES_TX_LANE_MODE_1	0xA5
+				USB3_UNI_QSERDES_TX_LANE_MODE_2	0x82
+				USB3_UNI_QSERDES_TX_LANE_MODE_3	0x3F
+				USB3_UNI_QSERDES_TX_LANE_MODE_4	0x3F
+				USB3_UNI_QSERDES_TX_PI_QEC_CTRL	0x21
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX	0x10
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX	0x0E
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG1	0xC4
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG2	0x89
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG3	0x20
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG6	0x13
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L	0xE7
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H	0x03
+				USB3_UNI_PCS_RX_SIGDET_LVL	0xAA
+				USB3_UNI_PCS_PCS_TX_RX_CONFIG	0x0C
+				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x07
+				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0xF8
+				USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1		0x6F
+				USB3_UNI_PCS_CDR_RESET_TIME	0x0A
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1	0x88
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2	0x13
+				USB3_UNI_PCS_EQ_CONFIG1	0x4B
+				USB3_UNI_PCS_EQ_CONFIG5	0x10
+				USB3_UNI_PCS_REFGEN_REQ_CONFIG1	0x21>;
+	};
+
+	usb1: ssusb@a800000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa800000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq";
+
+		USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>;
+		clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+			<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_SEC_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&gcc GCC_USB30_SEC_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,core-clk-rate-disconnected = <133333333>;
+		qcom,pm-qos-latency = <2>;
+
+		qcom,host-poweroff-in-pm-suspend;
+
+		interconnect-names = "usb-ddr", "ddr-usb";
+		interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,
+				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
+
+		dwc3@a800000 {
+			compatible = "snps,dwc3";
+			reg = <0xa800000 0xd93c>;
+			interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+			iommus = <&apps_smmu 0x0A0 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+			usb-phy = <&usb2_phy1>, <&usb_qmp_phy1>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,ssp-u3-u0-quirk;
+			snps,is-utmi-l1-suspend;
+			snps,usb2-gadget-lpm-disable;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "otg";
+		};
+	};
+
+	/* Secondary USB port related High Speed PHY */
+	usb2_phy1: hsphy@88e6000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e6000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&L7A>;
+		vdda18-supply = <&L6C>;
+		vdda33-supply = <&L9A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+				<&gcc GCC_USB_CLKREF_EN>;
+		clock-names = "ref_clk_src", "ref_clk";
+
+		resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
+		reset-names = "phy_reset";
+	};
+
+	/* Secondary USB port related QMP PHY */
+	usb_qmp_phy1: ssphy@88ea000 {
+		compatible = "qcom,usb-ssphy-qmp-v2";
+		reg = <0x88ea000 0x2000>,
+		    <0x088ea28c 0x4>;
+		reg-names = "qmp_phy_base",
+			"pcs_clamp_enable_reg";
+
+		vdd-supply = <&L7A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&L1C>;
+
+		clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+			 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
+			 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>,
+			 <&usb3_phy_wrapper_gcc_usb30_sec_pipe_clk>,
+			 <&rpmhcc RPMH_CXO_CLK>,
+			 <&gcc GCC_USB_CLKREF_EN>,
+			 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"ref_clk", "com_aux_clk";
+
+		resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+				<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+		reset-names = "phy_reset", "phy_phy_reset";
+
+		qcom,qmp-phy-reg-offset =
+				<USB3_UNI_PCS_PCS_STATUS1
+				USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
+				USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+				USB3_UNI_PCS_POWER_DOWN_CONTROL
+				USB3_UNI_PCS_SW_RESET
+				USB3_UNI_PCS_START_CONTROL>;
+
+		qcom,qmp-phy-init-seq =
+				/* <reg_offset, value> */
+				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL	0x1A
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL	0x11
+				USB3_UNI_QSERDES_COM_HSCLK_SEL	0x01
+				USB3_UNI_QSERDES_COM_DEC_START_MODE0	0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0	0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0	0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0	0x02
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1E
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0	0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0	0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0	0x36
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0	0x24
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0	0x34
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0	0x14
+				USB3_UNI_QSERDES_COM_LOCK_CMP_EN	0x04
+				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE	0x0A
+				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1	0x02
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1	0x24
+				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1	0x08
+				USB3_UNI_QSERDES_COM_DEC_START_MODE1	0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1	0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1	0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1	0x02
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1	0x82
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1	0x34
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1	0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1	0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1	0x36
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1E
+				USB3_UNI_QSERDES_COM_SSC_EN_CENTER	0x01
+				USB3_UNI_QSERDES_COM_SSC_PER1	0x31
+				USB3_UNI_QSERDES_COM_SSC_PER2	0x01
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1	0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1	0x07
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0	0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0	0x07
+				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP	0x02
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4	0xDC
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3	0xBD
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2	0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH	0x7F
+				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW	0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4	0xA9
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3	0x7B
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2	0xE4
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH	0x24
+				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW	0x64
+				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS	0x99
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1	0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2	0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1	0x00
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2	0x04
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN	0x2F
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW	0xFF
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	0x0F
+				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN	0x0A
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1	0x54
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2	0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2	0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4	0x0A
+				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x47
+				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	0x80
+				USB3_UNI_QSERDES_RX_SIGDET_CNTRL	0x04
+				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL	0x0E
+				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	0x38
+				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN	0x05
+				USB3_UNI_QSERDES_RX_GM_CAL	0x00
+				USB3_UNI_QSERDES_RX_SIGDET_ENABLES	0x00
+				USB3_UNI_QSERDES_TX_LANE_MODE_1	0xA5
+				USB3_UNI_QSERDES_TX_LANE_MODE_2	0x82
+				USB3_UNI_QSERDES_TX_LANE_MODE_3	0x3F
+				USB3_UNI_QSERDES_TX_LANE_MODE_4	0x3F
+				USB3_UNI_QSERDES_TX_PI_QEC_CTRL	0x21
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX	0x10
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX	0x0E
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG1	0xC4
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG2	0x89
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG3	0x20
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG6	0x13
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L	0xE7
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H	0x03
+				USB3_UNI_PCS_RX_SIGDET_LVL	0xAA
+				USB3_UNI_PCS_PCS_TX_RX_CONFIG	0x0C
+				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x07
+				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0xF8
+				USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1		0x6F
+				USB3_UNI_PCS_CDR_RESET_TIME	0x0A
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1	0x88
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2	0x13
+				USB3_UNI_PCS_EQ_CONFIG1	0x4B
+				USB3_UNI_PCS_EQ_CONFIG5	0x10
+				USB3_UNI_PCS_REFGEN_REQ_CONFIG1	0x21>;
+	};
+
+	/* Tertiary USB port related controller */
+	usb2: hsusb@a400000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa400000 0x100000>;
+		reg-names = "core_base";
+
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq";
+
+		USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>;
+		clocks = <&gcc GCC_USB20_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_USB20_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB20_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&gcc GCC_USB20_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <120000000>;
+
+		qcom,host-poweroff-in-pm-suspend;
+		qcom,default-mode-host;
+
+		interconnect-names = "usb-ddr", "ddr-usb";
+		interconnects = <&aggre1_noc MASTER_USB2 &mc_virt SLAVE_EBI1>,
+				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB2>;
+
+		dwc3@a400000 {
+			compatible = "snps,dwc3";
+			reg = <0xa400000 0xd800>;
+			iommus = <&apps_smmu 0x020 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy2>, <&usb_nop_phy>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,is-utmi-l1-suspend;
+			snps,usb2-gadget-lpm-disable;
+			tx-fifo-resize;
+			maximum-speed = "high-speed";
+			dr_mode = "host";
+		};
+	};
+
+	/* Tertiary USB port related High Speed PHY */
+	usb2_phy2: hsphy@88e7000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e7000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&L7A>;
+		vdda18-supply = <&L6C>;
+		vdda33-supply = <&L9A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+				<&gcc GCC_USB_CLKREF_EN>;
+		clock-names = "ref_clk_src", "ref_clk";
+
+		resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
+		reset-names = "phy_reset";
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+};
--- a/qcom/lemans.dtsi
+++ b/qcom/lemans.dtsi
@@ -373,6 +373,62 @@
 		size = <0 0x3000000>;
 	};

+	sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
+	qseecom_mem: qseecom_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1400000>;
+	};
+
+	qseecom_ta_mem: qseecom_ta_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
+	adsp_mem: adsp_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
+	cdsp_secure_mem: secure_cdsp_region { /* Secure DSP */
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x4800000>;
+	};
+
+	non_secure_display_memory: non_secure_display_region {
+		compatible = "shared-dma-pool";
+		reusable;
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		size = <0x0 0xa400000>;
+		alignment = <0x0 0x400000>;
+	};
+
+	user_contig_mem: user_contig_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
 	/* global autoconfigured region for contiguous allocations */
 	linux,cma {
 		compatible = "shared-dma-pool";
@@ -1140,6 +1196,11 @@
 #include "lemans-gdsc.dtsi"
 #include "lemans-pinctrl.dtsi"
 #include "msm-arm-smmu-lemans.dtsi"
+#include "lemans-dma-heaps.dtsi"
+#include "lemans-debug.dtsi"
+#include "lemans-qupv3.dtsi"
+#include "lemans-pcie.dtsi"
+#include "lemans-usb.dtsi"

 &cam_cc_titan_top_gdsc {
 	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
@@ -1327,9 +1388,6 @@
 	status = "ok";
 };

-#include "lemans-debug.dtsi"
-#include "lemans-qupv3.dtsi"
-
 &qupv3_se10_2uart {
 	status = "ok";
 };
--- a/qcom/monaco-idp-v1-common.dtsi
+++ b/qcom/monaco-idp-v1-common.dtsi
@@ -1,6 +1,24 @@
 #include "monaco-thermal-overlay.dtsi"
 #include "monaco-haptics-fifo-data.dtsi"

+&sdhc_1 {
+	status = "ok";
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+
+	vdd-supply = <&L25A>;
+	qcom,vdd-voltage-level = <3080000 3080000>;
+	qcom,vdd-current-level = <0 250000>;
+
+	vdd-io-supply = <&L15A>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 250000>;
+};
+
 &pm5100_sdam_2 {
 	hap_cl_brake: cl_brake@7c {
 		reg = <0x7c 0x1>;
--- a/qcom/monaco-idp-v1.dtsi
+++ b/qcom/monaco-idp-v1.dtsi
@@ -3,24 +3,6 @@
 #include <dt-bindings/iio/qti_power_supply_iio.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>

-&sdhc_1 {
-	status = "ok";
-
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&sdc1_on>;
-	pinctrl-1 = <&sdc1_off>;
-
-	vdd-supply = <&L25A>;
-	qcom,vdd-voltage-level = <3080000 3080000>;
-	qcom,vdd-current-level = <0 250000>;
-
-	vdd-io-supply = <&L15A>;
-	qcom,vdd-io-always-on;
-	qcom,vdd-io-lpm-sup;
-	qcom,vdd-io-voltage-level = <1800000 1800000>;
-	qcom,vdd-io-current-level = <0 250000>;
-};
-
 &soc {
 	bluetooth: bt_wcn3990 {
 		compatible = "qcom,qcc5100";
--- a/qcom/monaco-pmic.dtsi
+++ b/qcom/monaco-pmic.dtsi
@@ -54,6 +54,12 @@
 			linux,can-disable;
 		};
 	};
+
+	pmic-pon-log {
+		compatible = "qcom,pmic-pon-log";
+		nvmem = <&pm5100_sdam_5>;
+		nvmem-names = "pon_log";
+	};
 };

 &pm5100_adc {
--- a/qcom/monaco.dtsi
+++ b/qcom/monaco.dtsi
@@ -929,12 +929,12 @@
 				      <&adsp_smp2p_in 3 0>,
 				      <&adsp_smp2p_in 9 0>;

-		interrupt-names = "qcom,wdog",
-				  "qcom,err-fatal",
-				  "qcom,proxy-unvote",
-				  "qcom,err-ready",
-				  "qcom,stop-ack",
-				  "qcom,dsentry-ack";
+		interrupt-names = "wdog",
+				  "fatal",
+				  "handover",
+				  "ready",
+				  "stop-ack",
+				  "shutdown-ack";

 		/* Outputs to lpass */
 		qcom,smem-states = <&adsp_smp2p_out 0>;
@@ -958,6 +958,12 @@
 				qcom,non-wake-svc = <0x51
 						0x190>;
 			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
 		};
 	};

@@ -970,7 +976,7 @@

 		cx-supply = <&VDD_CX_LEVEL>;
 		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
-		reg-names = "vdd_cx";
+		reg-names = "cx";

 		memory-region = <&pil_modem_mem>;

@@ -980,16 +986,14 @@
 				<&modem_smp2p_in 2 0>,
 				<&modem_smp2p_in 1 0>,
 				<&modem_smp2p_in 3 0>,
-				<&modem_smp2p_in 7 0>,
 				<&modem_smp2p_in 9 0>;

-		interrupt-names = "qcom,wdog",
-				  "qcom,err-fatal",
-				  "qcom,proxy-unvote",
-				  "qcom,err-ready",
-				  "qcom,stop-ack",
-				  "qcom,shutdown-ack",
-				  "qcom,dsentry-ack";
+		interrupt-names = "wdog",
+				  "fatal",
+				  "handover",
+				  "ready",
+				  "stop-ack",
+				  "shutdown-ack";

 		/* Outputs to mss */
 		qcom,smem-states = <&modem_smp2p_out 0>;
@@ -1184,6 +1188,61 @@
 		#mbox-cells = <1>;
 	};

+	qcom,msm-adsprpc-mem {
+		compatible = "qcom,msm-adsprpc-mem-region";
+		memory-region = <&adsp_mem>;
+		restrict-access;
+	};
+
+	qcom,msm_fastrpc {
+		compatible = "qcom,msm-fastrpc-compute";
+		qcom,rpc-latency-us = <611>;
+		qcom,adsp-remoteheap-vmid = <22 37>;
+		qcom,fastrpc-adsp-audio-pdr;
+		qcom,fastrpc-adsp-sensors-pdr;
+
+		qcom,msm_fastrpc_compute_cb1 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x01C3 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable";
+		};
+
+		qcom,msm_fastrpc_compute_cb2 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x01C4 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable";
+		};
+
+		qcom,msm_fastrpc_compute_cb3 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x01C5 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable";
+		};
+
+		qcom,msm_fastrpc_compute_cb4 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x01C6 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable";
+		};
+
+		qcom,msm_fastrpc_compute_cb5 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x01C7 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable";
+		};
+
+	};
+
 	rpm-glink {
 		compatible = "qcom,glink-rpm";
 		interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
@@ -1692,6 +1751,103 @@
 		qcom,ipa-napi-enable;
 	};

+	ipa_hw: qcom,ipa@0x5800000 {
+		compatible = "qcom,ipa";
+		reg = <0x5800000 0x34000>,
+			<0x5804000 0x28000>;
+		reg-names = "ipa-base", "gsi-base";
+		interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "ipa-irq", "gsi-irq";
+		pas-ids = <0xf>;
+		firmware-names = "ipa_fws";
+		memory-regions = <&pil_ipa_fw_mem>;
+		qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */
+		qcom,ipa-hw-mode = <0>;
+		qcom,platform-type = <1>; /* MSM platform */
+		qcom,ee = <0>;
+		qcom,use-ipa-tethering-bridge;
+		qcom,modem-cfg-emb-pipe-flt;
+		qcom,ipa-wdi2;
+		qcom,ipa-wdi2_over_gsi;
+		qcom,ipa-endp-delay-wa;
+		qcom,use-ipa-pm;
+		qcom,arm-smmu;
+		qcom,ipa-fltrt-not-hashable;
+		qcom,skip-ieob-mask-wa;
+		qcom,msm-bus,name = "ipa";
+		qcom,max_num_smmu_cb = <3>;
+		clocks = <&rpmcc RPM_SMD_IPA_CLK>;
+		clock-names = "core_clk";
+		qcom,interconnect,num-cases = <5>;
+		qcom,interconnect,num-paths = <4>;
+		interconnects = <&system_noc MASTER_IPA &system_noc SNOC_BIMC_SLV>,
+				<&bimc SNOC_BIMC_MAS &bimc SLAVE_EBI_CH0>,
+				<&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
+				<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_IPA_CFG>;
+		interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "ipa_to_imem", "appss_to_ipa";
+		/* No vote */
+		qcom,no-vote =
+		<0 0 0 0 0 0 0 0>;
+
+		/* SVS2 */
+		qcom,svs2 =
+		<80000 590000 80000 2160000 80000 560000 80000 120000>;
+
+		/* SVS */
+		qcom,svs =
+		<80000 800000 80000 5414000 80000 920000 80000 180000>;
+
+		/* NOMINAL */
+		qcom,nominal =
+		<206000 1500000 206000 7200000 206000 1560000 206000 380000>;
+
+		/* TURBO */
+		qcom,turbo =
+		<206000 1800000 206000 8500000 206000 1880000 206000 520000>;
+		qcom,bus-vector-names =
+		"MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
+		qcom,throughput-threshold = <310 600 1000>;
+		qcom,scaling-exceptions = <>;
+
+		/* smp2p information */
+		qcom,smp2p_map_ipa_1_out {
+			compatible = "qcom,smp2p-map-ipa-1-out";
+			qcom,smem-states = <&smp2p_ipa_1_out 0>;
+			qcom,smem-state-names = "ipa-smp2p-out";
+		};
+
+		qcom,smp2p_map_ipa_1_in {
+			compatible = "qcom,smp2p-map-ipa-1-in";
+			interrupts-extended = <&smp2p_ipa_1_in 0 0>;
+			interrupt-names = "ipa-smp2p-in";
+		};
+
+		ipa_smmu_ap: ipa_smmu_ap {
+			compatible = "qcom,ipa-smmu-ap-cb";
+			iommus = <&apps_smmu 0x0140 0x0>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>;
+			/* modem tables in IMEM */
+			qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>;
+			qcom,iommu-dma = "fastmap";
+			qcom,iommu-geometry = <0 0xB0000000>;
+		};
+
+		ipa_smmu_wlan: ipa_smmu_wlan {
+			compatible = "qcom,ipa-smmu-wlan-cb";
+			iommus = <&apps_smmu 0x141 0x0>;
+			/* ipa-uc ram */
+			qcom,iommu-dma = "atomic";
+		};
+
+		ipa_smmu_uc: ipa_smmu_uc {
+			compatible = "qcom,ipa-smmu-uc-cb";
+			iommus = <&apps_smmu 0x0142 0x0>;
+			qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>;
+			qcom,iommu-dma = "atomic";
+		};
+	};
+
 	qcom,power-state {
 		compatible = "qcom,power-state";
 	};
--- a/qcom/pm5100.dtsi
+++ b/qcom/pm5100.dtsi
@@ -299,6 +299,11 @@

 		};

+		pm5100_sdam_5: sdam@7400 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7400>;
+		};
+
 		pm5100_sdam_7: sdam@7600 {
 			compatible = "qcom,spmi-sdam";
 			reg = <0x7600>;
--- a/qcom/pmx35.dtsi
+++ b/qcom/pmx35.dtsi
@@ -0,0 +1,75 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pmx35@0 {
+		compatible = "qcom,spmi-pmic";
+		reg = <1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmx35_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pon_hlos@1300 {
+			compatible = "qcom,pm8998-pon";
+			reg = <0x1300>, <0x800>;
+			reg-names = "pon_hlos", "pon_pbs";
+			qcom,log-kpd-event;
+
+			pwrkey {
+				compatible = "qcom,pmk8350-pwrkey";
+				interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
+				linux,code = <KEY_POWER>;
+			};
+
+			resin{
+				compatible = "qcom,pmk8350-resin";
+				interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+				linux,code = <KEY_VOLUMEDOWN>;
+			};
+		};
+
+
+		pmx35_vbus_detect: qcom,pmd-vbus-det@1900 {
+			compatible = "qcom,pm8941-misc";
+			reg = <0x1900>;
+			interrupts = <0x0 0x19 0x0 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "usb_vbus";
+			status = "disabled";
+		};
+
+		pmx35_gpios: pinctrl@8800 {
+			compatible = "qcom,pmx35-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pmx35_pwm: pwms@e800 {
+			compatible = "qcom,pwm-lpg";
+			reg = <0xe800>;
+			reg-names = "lpg-base";
+			#pwm-cells = <2>;
+			qcom,num-lpg-channels = <4>;
+		};
+
+		pmx35_rtc: qcom,pmx35_rtc {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6400>, <0x6500>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x65 0x1 IRQ_TYPE_NONE>;
+		};
+	};
+};
--- a/qcom/quin-vm-common.dtsi
+++ b/qcom/quin-vm-common.dtsi
@@ -1,6 +1,8 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

 / {
 	#address-cells = <2>;
@@ -74,12 +76,39 @@
 		status = "ok";
 	};

+	dummycc: qcom,dummycc {
+		compatible = "qcom,dummycc";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gcc: virtio_clock@1c200000 {
+		compatible = "virtio,mmio";
+		reg = <0x1c200000 0x1000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	scc: virtio_clock@1c300000 {
+		compatible = "virtio,mmio";
+		reg = <0x1c300000 0x1000>;
+		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+		#clock-cells = <1>;
+	};
+
 	intc: vgic@0 {
 		qvm,vdev = "gic";
 		#interrupt-cells = <3>;
 		interrupt-controller;
 	};

+	regulator: virtio_regulator@1c700000 {
+		compatible = "virtio,mmio";
+		reg = <0x1c700000 0x1000>;
+		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	qcom_dma_heaps: qcom,dma-heaps {
 		compatible = "qcom,dma-heaps";

--- a/qcom/sa410m-emmc-ccard-overlay.dts
+++ b/qcom/sa410m-emmc-ccard-overlay.dts
@@ -1,4 +1,5 @@
 /dts-v1/;
+/plugin/;

 #include "sa410m-idp.dtsi"

@@ -8,3 +9,7 @@
 	qcom,msm-id=<560 0x10000>;
 	qcom,board-id = <25 0x0>;
 };
+
+&qnand_1 {
+	status = "disabled";
+};
--- a/qcom/sa410m-emmc-idp-overlay.dts
+++ b/qcom/sa410m-emmc-idp-overlay.dts
@@ -1,4 +1,5 @@
 /dts-v1/;
+/plugin/;

 #include "sa410m-idp.dtsi"

@@ -8,3 +9,7 @@
 	qcom,msm-id=<560 0x10000>;
 	qcom,board-id = <34 0x0>;
 };
+
+&qnand_1 {
+	status = "disabled";
+};
--- a/qcom/sa410m-idp.dtsi
+++ b/qcom/sa410m-idp.dtsi
@@ -1 +1,21 @@
-#include "sa410m.dtsi"
+&soc { } ;
+
+&qnand_1 {
+	status = "ok";
+};
+
+&sdhc_1 {
+	status = "ok";
+	vdd-supply = <&L20A>;
+	qcom,vdd-voltage-level = <2856000 2856000>;
+	qcom,vdd-current-level = <0 570000>;
+	vdd-io-supply = <&L14A>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 325000>;
+	max-frequency = <100000000>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+};
--- a/qcom/sa410m-nand-ccard-overlay.dts
+++ b/qcom/sa410m-nand-ccard-overlay.dts
@@ -1,4 +1,5 @@
 /dts-v1/;
+/plugin/;

 #include "sa410m-idp.dtsi"

@@ -8,3 +9,11 @@
 	qcom,msm-id=<560 0x10000>;
 	qcom,board-id = <25 0x1>;
 };
+
+&qnand_1 {
+	status = "ok";
+};
+
+&sdhc_1 {
+	status = "disabled";
+};
--- a/qcom/sa410m-nand-idp-overlay.dts
+++ b/qcom/sa410m-nand-idp-overlay.dts
@@ -1,4 +1,5 @@
 /dts-v1/;
+/plugin/;

 #include "sa410m-idp.dtsi"

@@ -8,3 +9,11 @@
 	qcom,msm-id=<560 0x10000>;
 	qcom,board-id = <34 0x1>;
 };
+
+&qnand_1 {
+	status = "ok";
+};
+
+&sdhc_1 {
+	status = "disabled";
+};
--- a/qcom/sa410m-pinctrl.dtsi
+++ b/qcom/sa410m-pinctrl.dtsi
@@ -691,4 +691,54 @@
 			};
 		};
 	};
+
+	sdc1_on: sdc1_on {
+		clk {
+			pins = "sdc1_clk";
+			bias-disable;
+			drive-strength = <16>;
+		};
+
+		cmd {
+			pins = "sdc1_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data {
+			pins = "sdc1_data";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		rclk {
+			pins = "sdc1_rclk";
+			bias-pull-down;
+		};
+	};
+
+	sdc1_off: sdc1_off {
+		clk {
+			pins = "sdc1_clk";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		cmd {
+			pins = "sdc1_cmd";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		data {
+			pins = "sdc1_data";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		rclk {
+			pins = "sdc1_rclk";
+			bias-pull-down;
+		};
+	};
 };
--- a/qcom/sa410m-rumi-overlay.dts
+++ b/qcom/sa410m-rumi-overlay.dts
@@ -1,4 +1,5 @@
 /dts-v1/;
+/plugin/;

 #include "sa410m-rumi.dtsi"

@@ -6,5 +7,5 @@
 	model = "Qualcomm Technologies, Inc. SA410M RUMI";
 	compatible = "qcom,sa410m", "qcom,rumi", "qcom,sa410m-rumi";
 	qcom,msm-id=<560 0x10000>;
-	qcom,board-id = <15 0x400>;
+	qcom,board-id = <15 0>;
 };
--- a/qcom/sa410m-rumi.dtsi
+++ b/qcom/sa410m-rumi.dtsi
@@ -1,5 +1,3 @@
-#include "sa410m.dtsi"
-
 &arch_timer {
 	clock-frequency = <500000>;
 };
@@ -37,3 +35,31 @@
 	clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&pcie_0_pipe_clk>,
 		<&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
 };
+
+&qnand_1 {
+	status = "ok";
+};
+
+&sdhc_1 {
+	status = "ok";
+	vdd-supply = <&L20A>;
+	qcom,vdd-voltage-level = <2856000 2856000>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&L14A>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	/delete-property/ mmc-ddr-1_8v;
+	/delete-property/ mmc-hs200-1_8v;
+	/delete-property/ mmc-hs400-1_8v;
+	/delete-property/ mmc-hs400-enhanced-strobe;
+
+	max-frequency = <100000000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+};
--- a/qcom/sa410m.dts
+++ b/qcom/sa410m.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "sa410m.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SA410M";
+	compatible = "qcom,sa410m";
+	qcom,board-id = <0 0>;
+};
--- a/qcom/sa410m.dtsi
+++ b/qcom/sa410m.dtsi
@@ -6,10 +6,13 @@
 #include <dt-bindings/clock/qcom,rpmcc.h>

 / {
-	#address-cells = <2>;
-	#size-cells = <2>;
+	model = "Qualcomm Technologies, Inc. SA410M";
+	compatible = "qcom,sa410m";
+	qcom,msm-id = <560 0x10000>;
 	interrupt-parent = <&intc>;

+	#address-cells = <2>;
+	#size-cells = <2>;
 	memory { device_type = "memory"; reg = <0 0 0 0>; };

 	reserved_memory: reserved-memory { };
@@ -24,6 +27,8 @@

 	aliases {
 		serial0 = &qupv3_se4_2uart;
+		qpic_nand1 = &qnand_1;
+		mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
 	};

 	firmware: firmware {};
@@ -36,10 +41,13 @@
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x0>;
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD0>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;
 			L2_0: l2-cache {
 				compatible = "arm,arch-cache";
@@ -59,10 +67,13 @@
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x1>;
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD1>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;

 			L1_I_1: l1-icache {
@@ -79,9 +90,12 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD2>;
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;

 			L1_I_2: l1-icache {
@@ -98,9 +112,12 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD3>;
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;

 			L1_I_3: l1-icache {
@@ -133,9 +150,56 @@
 		};
 	};

+	idle-states {
+		SILVER_OFF: silver-c3 {  /* C3 */
+			compatible = "arm,idle-state";
+			idle-state-name = "pc";
+			entry-latency-us = <297>;
+			exit-latency-us = <324>;
+			min-residency-us = <1110>;
+			arm,psci-suspend-param = <0x40000003>;
+			local-timer-stop;
+		};
+
+		SILVER_CLUSTER_D3: silver-cluster-d3 { /* D3 */
+			compatible = "domain-idle-state";
+			idle-state-name = "pwr-l2-pc";
+			entry-latency-us = <800>;
+			exit-latency-us = <2118>;
+			min-residency-us = <7376>;
+			arm,psci-suspend-param = <0x41000043>;
+		};
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
+
+		CPU_PD0: cpu-pd0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD1: cpu-pd1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD2: cpu-pd2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD3: cpu-pd3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CLUSTER_PD0: cluster-pd0 {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&SILVER_CLUSTER_D3>;
+		};
+
 	};

 	chosen {
@@ -195,6 +259,11 @@
 		reg = <0x0 0x52910000 0x0 0x5000>;
 	};

+	pil_reserved_unused_mem: pil_reserved_unused_region@52915000 {
+		no-map;
+		reg = <0x0 0x52915000 0x0 0xEB000>;
+	};
+
 	tz_stat: tz_stat@53200000 {
 		no-map;
 		reg = <0x0 0x53200000 0x0 0x100000>;
@@ -263,6 +332,17 @@
 	};
 };

+&firmware {
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+	};
+
+	qcom_smcinvoke {
+		compatible = "qcom,smcinvoke";
+	};
+};
+
+
 &soc {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -282,6 +362,45 @@
 		#gpio-cells = <0>;
 	};

+	mpm: interrupt-controller@45f01b8 {
+		compatible = "qcom,mpm-sa410m", "qcom,mpm";
+		reg = <0x45f01b8 0x1000>,
+		      <0xf111008 0x4>,  /* MSM_APCS_GCC_BASE 4K */
+		      <0xf121000 0x1000>;
+		reg-names = "vmpm", "ipc", "timer";
+		interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+		qcom,num-mpm-irqs = <96>;
+		interrupt-controller;
+		interrupt-parent = <&intc>;
+		#interrupt-cells = <2>;
+	};
+
+	rpm_bus: qcom,rpm-smd {
+		compatible = "qcom,rpm-smd";
+		rpm-channel-name = "rpm_requests";
+		interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+		power-domains = <&CLUSTER_PD>;
+		rpm-channel-type = <15>; /* SMD_APPS_RPM */
+	};
+
+	cluster-device {
+		compatible = "qcom,lpm-cluster-dev";
+		power-domains = <&CLUSTER_PD>;
+	};
+
+	rpm-sleep-stats@4690000 {
+		compatible = "qcom,rpm-sleep-stats";
+		reg = <0x04690000 0x400>;
+	};
+
+	qcom,rpm-master-stats@45f0150 {
+		compatible = "qcom,rpm-master-stats";
+		reg = <0x45f0150 0x5000>;
+		qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ";
+		qcom,master-stats-version = <2>;
+		qcom,master-offset = <4096>;
+	};
+
 	arch_timer: timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
@@ -369,7 +488,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
-			//wakeup-parent = <&wakegic>;
+			wakeup-parent = <&mpm>;
 	};

 	qcom-secure-buffer {
@@ -380,6 +499,14 @@
 		compatible = "qcom,scm";
 	};

+	qcom,rmtfs_sharedmem@0 {
+		compatible = "qcom,sharedmem-uio";
+		reg = <0x0 0x280000>;
+		reg-names = "rmtfs";
+		qcom,client-id = <0x00000001>;
+		qcom,vm-nav-path;
+	};
+
 	clocks {
 		xo_board: xo-board {
 			compatible = "fixed-clock";
@@ -454,6 +581,15 @@
 		#clock-cells = <1>;
 	};

+	cpufreq_hw: qcom,cpufreq-hw {
+		compatible = "qcom,cpufreq-hw";
+		reg = <0xf521000 0x1400>;
+		reg-names = "freq-domain0";
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+		clock-names = "xo", "alternate";
+		#freq-domain-cells = <1>;
+	};
+
 	bimc_noc: interconnect@0 {
 		compatible = "qcom,sa410m-bimc";
 		#interconnect-cells = <1>;
@@ -476,10 +612,226 @@

 	thermal_zones: thermal-zones { };

+	rpm_msg_ram: memory@045f0000 {
+		compatible = "qcom,rpm-msg-ram";
+		reg = <0x45f0000 0x7000>;
+	};
+
+	apcs_glb: mailbox@0f111000 {
+		compatible = "qcom,scuba-apcs-hmss-global";
+		reg = <0xF111000 0x1000>;
+
+		#mbox-cells = <1>;
+	};
+
+	rpm-glink {
+		compatible = "qcom,glink-rpm";
+		interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+		qcom,rpm-msg-ram = <&rpm_msg_ram>;
+		mboxes = <&apcs_glb 0>;
+
+		qcom,rpm_glink_ssr {
+			qcom,glink-channels = "glink_ssr";
+			// qcom,notify-edges = <&glink_adsp>;
+		};
+	};
+
+	tcsr_mutex_block: syscon@00340000 {
+		compatible = "syscon";
+		reg = <0x340000 0x20000>;
+	};
+
+	tcsr_mutex: hwlock {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_block 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
+	smem: qcom,smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_region>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	qcom,glinkpkt {
+		compatible = "qcom,glinkpkt";
+
+		qcom,glinkpkt-at-mdm0 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DS";
+			qcom,glinkpkt-dev-name = "at_mdm0";
+		};
+
+		qcom,glinkpkt-data40-cntl {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA40_CNTL";
+			qcom,glinkpkt-dev-name = "smdcntl8";
+		};
+
+		qcom,glinkpkt-data1 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA1";
+			qcom,glinkpkt-dev-name = "smd7";
+		};
+
+		qcom,glinkpkt-data4 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA4";
+			qcom,glinkpkt-dev-name = "smd8";
+		};
+
+		qcom,glinkpkt-data11 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA11";
+			qcom,glinkpkt-dev-name = "smd11";
+		};
+	};
+
+	qcom,smp2p-modem {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 14>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
+			qcom,entry-name = "ipa";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		/* ipa - inbound entry from mss */
+		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
+			qcom,entry-name = "ipa";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 10>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	qcom,sps {
 		compatible = "qcom,msm-sps-4k";
 		qcom,pipe-attr-ee;
 	};
+
+	qnand_1: nand@0x4840000 {
+		compatible = "qcom,msm-nand";
+		reg =   <0x4840000 0x1000>,
+			<0x4844000 0x1c000>;
+		reg-names =     "nand_phys",
+				"bam_phys";
+		qcom,reg-adjustment-offset = <0x4000>;
+		interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "bam_irq";
+		clock-names = "core_clk";
+		clocks = <&rpmcc RPM_SMD_QPIC_CLK>;
+
+		//interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>;
+		interconnect-names = "nand-ddr";
+		qcom,msm-bus,name = "qpic_nand";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<0 0>,
+		/* Voting for max b/w on PNOC bus for now */
+			<1057800 725760>;
+
+		iommus = <&apps_smmu 0x100 0x7>;
+		qcom,iommu-dma = "bypass";
+		status = "disabled";
+	};
+
+	sdhc_1: sdhci@4744000 {
+		status = "disabled";
+
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
+		reg-names = "hc", "cqhci";
+
+		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		bus-width = <8>;
+		non-removable;
+		supports-cqe;
+
+		no-sd;
+		no-sdio;
+		qcom,restore-after-cx-collapse;
+
+		mmc-ddr-1_8v;
+		mmc-hs200-1_8v;
+		mmc-hs400-1_8v;
+		mmc-hs400-enhanced-strobe;
+
+		cap-mmc-hw-reset;
+
+		clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+			<&gcc GCC_SDCC1_AHB_CLK>;
+		clock-names = "core", "iface";
+
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>;
+
+		/* Add dt entry for gcc hw reset */
+		//resets = <&gcc GCC_EMMC_BCR>;
+		//reset-names = "core_reset";
+
+		iommus = <&apps_smmu 0xC0 0x0>;
+		qcom,iommu-dma = "bypass";
+
+		qos0 {
+			mask = <0x0f>;
+			vote = <44>;
+		};
+
+	qcom_qseecom: qseecom@c1700000 {
+		compatible = "qcom,qseecom";
+		memory-region = <&qseecom_mem>;
+		qseecom_mem = <&qseecom_mem>;
+		qseecom_ta_mem = <&qseecom_ta_mem>;
+		user_contig_mem = <&user_contig_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,no-clock-support;
+		qcom,appsbl-qseecom-support;
+		qcom,commonlib64-loaded-by-uefi;
+		qcom,qsee-reentrancy-support = <2>;
+	};
 };

 #include "sa410m-stub-regulators.dtsi"
--- a/qcom/sa525m.dtsi
+++ b/qcom/sa525m.dtsi
@@ -5,3 +5,7 @@
 	compatible = "qcom,sdxpinn";
 	qcom,msm-id=<558 0x10000> ;
 };
+
+&qnand_1 {
+	status = "ok";
+};
--- a/qcom/sa8155-vm-la-overlay.dts
+++ b/qcom/sa8155-vm-la-overlay.dts
@@ -1,7 +1,6 @@
 /dts-v1/;
 /plugin/;

-#include "sa8155-vm.dtsi"

 / {
 	model = "Qualcomm Technologies, Inc. SA8155 Single LA Guest Virtual Machine";
--- a/qcom/sa8155-vm-pcie.dtsi
+++ b/qcom/sa8155-vm-pcie.dtsi
@@ -0,0 +1,612 @@
+&soc {
+	pcie0: qcom,pcie@1c00000 {
+		compatible = "qcom,pci-msm";
+		cell-index = <0>;
+
+		reg = <0x1c00000 0x4000>,
+			<0x1c06000 0x1000>,
+			<0x60000000 0xf1d>,
+			<0x60000f20 0xa8>,
+			<0x60001000 0x1000>,
+			<0x60100000 0x100000>,
+			<0x60200000 0x100000>,
+			<0x60300000 0x3d00000>;
+
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "io", "bars";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
+			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
+		interrupt-parent = <&pcie0>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,phy-sequence = <0x0840 0x03 0x0
+				0x0094 0x08 0x0
+				0x0154 0x34 0x0
+				0x016c 0x08 0x0
+				0x0058 0x0f 0x0
+				0x00a4 0x42 0x0
+				0x0110 0x24 0x0
+				0x011c 0x03 0x0
+				0x0118 0xb4 0x0
+				0x010c 0x02 0x0
+				0x01bc 0x11 0x0
+				0x00bc 0x82 0x0
+				0x00d4 0x03 0x0
+				0x00d0 0x55 0x0
+				0x00cc 0x55 0x0
+				0x00b0 0x1a 0x0
+				0x00ac 0x0a 0x0
+				0x00c4 0x68 0x0
+				0x00e0 0x02 0x0
+				0x00dc 0xaa 0x0
+				0x00d8 0xab 0x0
+				0x00b8 0x34 0x0
+				0x00b4 0x14 0x0
+				0x0158 0x01 0x0
+				0x0074 0x06 0x0
+				0x007c 0x16 0x0
+				0x0084 0x36 0x0
+				0x0078 0x06 0x0
+				0x0080 0x16 0x0
+				0x0088 0x36 0x0
+				0x01b0 0x1e 0x0
+				0x01ac 0xb9 0x0
+				0x01b8 0x18 0x0
+				0x01b4 0x94 0x0
+				0x0050 0x07 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x029c 0x12 0x0
+				0x0284 0x35 0x0
+				0x0288 0x82 0x0
+				0x023c 0x11 0x0
+				0x051c 0x03 0x0
+				0x0518 0x1c 0x0
+				0x0524 0x1e 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x05b4 0x04 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0510 0x17 0x0
+				0x04d4 0x04 0x0
+				0x04d8 0x07 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0570 0xff 0x0
+				0x0574 0xff 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x66 0x0
+				0x04fc 0x00 0x0
+				0x04f8 0xc0 0x0
+				0x0460 0x30 0x0
+				0x0464 0x00 0x0
+				0x05bc 0x0c 0x0
+				0x04dc 0x0d 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x09a4 0x01 0x0
+				0x0c90 0x00 0x0
+				0x0c40 0x01 0x0
+				0x0c48 0x01 0x0
+				0x0c50 0x00 0x0
+				0x0cb4 0x33 0x0
+				0x0cbc 0x00 0x0
+				0x0ce0 0x58 0x0
+				0x0ca4 0x0f 0x0
+				0x0048 0x90 0x0
+				0x0c1c 0xc1 0x0
+				0x0988 0x88 0x0
+				0x0998 0x0b 0x0
+				0x08dc 0x0d 0x0
+				0x09ec 0x12 0x0
+				0x0800 0x00 0x0
+				0x0844 0x03 0x0>;
+
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pcie0_clkreq_default
+			&pcie0_perst_default
+			&pcie0_wake_default>;
+		pinctrl-1 = <&pcie0_clkreq_sleep
+			&pcie0_perst_default
+			&pcie0_wake_default>;
+
+		perst-gpio = <&tlmm 35 0>;
+		wake-gpio = <&tlmm 37 0>;
+
+		gdsc-core-vdd-supply = <&pcie_0_gdsc>;
+		vreg-1p2-supply = <&pm8150_2_l8>;
+		vreg-0p9-supply = <&pm8150_2_l18>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 24000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
+
+		msi-parent = <&pcie0_msi>;
+
+		qcom,no-l0s-supported;
+
+		qcom,ep-latency = <10>;
+
+		qcom,slv-addr-space-size = <0x4000000>;
+
+		qcom,phy-status-offset = <0x814>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x840>;
+
+		qcom,boot-option = <0x1>;
+
+		linux,pci-domain = <0>;
+
+		qcom,pcie-phy-ver = <2114>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+
+		qcom,smmu-sid-base = <0x1d80>;
+		qcom,no-l1-supported;
+		qcom,no-l1ss-supported;
+		qcom,no-aux-clk-sync;
+		qcom,core-preset = <0x77777777>;
+		dma-coherent;
+		iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
+			<0x100 &apps_smmu 0x1d81 0x1>,
+			<0x200 &apps_smmu 0x1d82 0x1>,
+			<0x300 &apps_smmu 0x1d83 0x1>,
+			<0x400 &apps_smmu 0x1d84 0x1>,
+			<0x500 &apps_smmu 0x1d85 0x1>,
+			<0x600 &apps_smmu 0x1d86 0x1>,
+			<0x700 &apps_smmu 0x1d87 0x1>,
+			<0x800 &apps_smmu 0x1d88 0x1>,
+			<0x900 &apps_smmu 0x1d89 0x1>,
+			<0xa00 &apps_smmu 0x1d8a 0x1>,
+			<0xb00 &apps_smmu 0x1d8b 0x1>,
+			<0xc00 &apps_smmu 0x1d8c 0x1>,
+			<0xd00 &apps_smmu 0x1d8d 0x1>,
+			<0xe00 &apps_smmu 0x1d8e 0x1>,
+			<0xf00 &apps_smmu 0x1d8f 0x1>;
+
+		clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+			<&dummycc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_0_AUX_CLK>,
+			<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_0_CLKREF_CLK>,
+			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
+			<&gcc GCC_PCIE_PHY_AUX_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
+				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
+				"pcie_ldo", "pcie_0_slv_q2a_axi_clk",
+				"pcie_0_tbu_clk", "pcie_0_phy_refgen_clk",
+				"pcie_0_phy_aux_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <100000000>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+						 <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_0_BCR>,
+			<&gcc GCC_PCIE_0_PHY_BCR>;
+
+		reset-names = "pcie_0_core_reset",
+				"pcie_0_phy_reset";
+
+		pcie_rc0: pcie_rc0 {
+			#address-cells = <5>;
+			#size-cells = <0>;
+			reg = <0 0 0 0 0>;
+			pci-ids = "17cb:0108";
+		};
+	};
+
+	pcie0_msi: qcom,pcie0_msi@17a00040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a00040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pcie1: qcom,pcie@1c08000 {
+		compatible = "qcom,pci-msm";
+		cell-index = <1>;
+
+		reg = <0x1c08000 0x4000>,
+			<0x1c0e000 0x2000>,
+			<0x40000000 0xf1d>,
+			<0x40000f20 0xa8>,
+			<0x40001000 0x1000>,
+			<0x40100000 0x100000>,
+			<0x40200000 0x100000>,
+			<0x40300000 0x1fd00000>;
+
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "io", "bars";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
+			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
+		interrupt-parent = <&pcie1>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,phy-sequence = <0x0a40 0x03 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xb9 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0x94 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x023c 0x11 0x0
+				0x0284 0x35 0x0
+				0x0288 0x82 0x0
+				0x029c 0x12 0x0
+				0x0304 0x02 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0460 0x30 0x0
+				0x0464 0x00 0x0
+				0x04d4 0x04 0x0
+				0x04d8 0x07 0x0
+				0x04dc 0x0d 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x04f8 0xc0 0x0
+				0x04fc 0x00 0x0
+				0x0510 0x17 0x0
+				0x0518 0x1c 0x0
+				0x051c 0x03 0x0
+				0x0524 0x1e 0x0
+				0x0570 0xff 0x0
+				0x0574 0xff 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x66 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x05bc 0x0c 0x0
+				0x063c 0x11 0x0
+				0x0684 0x35 0x0
+				0x0688 0x82 0x0
+				0x069c 0x12 0x0
+				0x0704 0x20 0x0
+				0x0808 0x0c 0x0
+				0x0814 0x03 0x0
+				0x0834 0x7f 0x0
+				0x0844 0x70 0x0
+				0x0860 0x30 0x0
+				0x0864 0x00 0x0
+				0x08d4 0x04 0x0
+				0x08d8 0x07 0x0
+				0x08dc 0x0d 0x0
+				0x08e8 0x00 0x0
+				0x08ec 0x0e 0x0
+				0x08f0 0x4a 0x0
+				0x08f4 0x0f 0x0
+				0x08f8 0xc0 0x0
+				0x08fc 0x00 0x0
+				0x0910 0x17 0x0
+				0x0918 0x1c 0x0
+				0x091c 0x03 0x0
+				0x0924 0x1e 0x0
+				0x0970 0xff 0x0
+				0x0974 0xff 0x0
+				0x0978 0xff 0x0
+				0x097c 0x7f 0x0
+				0x0980 0x66 0x0
+				0x0984 0x24 0x0
+				0x0988 0xe4 0x0
+				0x098c 0xec 0x0
+				0x0990 0x3b 0x0
+				0x0994 0x36 0x0
+				0x0998 0xd4 0x0
+				0x099c 0x54 0x0
+				0x09a0 0xdb 0x0
+				0x09a4 0x3b 0x0
+				0x09a8 0x31 0x0
+				0x09bc 0x0c 0x0
+				0x0adc 0x05 0x0
+				0x0b88 0x88 0x0
+				0x0b98 0x0b 0x0
+				0x0ba4 0x01 0x0
+				0x0bec 0x12 0x0
+				0x0e0c 0x0d 0x0
+				0x0e14 0x07 0x0
+				0x0e1c 0xc1 0x0
+				0x0e40 0x01 0x0
+				0x0e48 0x01 0x0
+				0x0e90 0x00 0x0
+				0x0eb4 0x33 0x0
+				0x0ebc 0x00 0x0
+				0x0ee0 0x58 0x0
+				0x0ea4 0x0f 0x0
+				0x0a00 0x00 0x0
+				0x0a44 0x03 0x0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie1_clkreq_default
+			&pcie1_perst_default
+			&pcie1_wake_default>;
+
+		perst-gpio = <&tlmm 102 0>;
+		wake-gpio = <&tlmm 104 0>;
+
+		gdsc-core-vdd-supply = <&pcie_1_gdsc>;
+		vreg-1p2-supply = <&pm8150_2_l8>;
+		vreg-0p9-supply = <&pm8150_2_l18>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 24000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
+
+		msi-parent = <&pcie1_msi>;
+
+		qcom,no-l0s-supported;
+
+		qcom,ep-latency = <10>;
+
+		qcom,slv-addr-space-size = <0x20000000>;
+
+		qcom,phy-status-offset = <0xa14>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0xa40>;
+
+		qcom,boot-option = <0x1>;
+
+		linux,pci-domain = <1>;
+
+		qcom,pcie-phy-ver = <2111>;
+		qcom,aux-clk-freq = <20>;
+
+		qcom,smmu-sid-base = <0x1e00>;
+		qcom,core-preset = <0x77777777>;
+
+		dma-coherent;
+		iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
+			<0x100 &apps_smmu 0x1e01 0x1>,
+			<0x200 &apps_smmu 0x1e02 0x1>,
+			<0x300 &apps_smmu 0x1e03 0x1>,
+			<0x400 &apps_smmu 0x1e04 0x1>,
+			<0x500 &apps_smmu 0x1e05 0x1>,
+			<0x600 &apps_smmu 0x1e06 0x1>,
+			<0x700 &apps_smmu 0x1e07 0x1>,
+			<0x800 &apps_smmu 0x1e08 0x1>,
+			<0x900 &apps_smmu 0x1e09 0x1>,
+			<0xa00 &apps_smmu 0x1e0a 0x1>,
+			<0xb00 &apps_smmu 0x1e0b 0x1>,
+			<0xc00 &apps_smmu 0x1e0c 0x1>,
+			<0xd00 &apps_smmu 0x1e0d 0x1>,
+			<0xe00 &apps_smmu 0x1e0e 0x1>,
+			<0xf00 &apps_smmu 0x1e0f 0x1>;
+
+		clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+			<&dummycc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_1_AUX_CLK>,
+			<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_1_CLKREF_CLK>,
+			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+			<&gcc GCC_PCIE_PHY_AUX_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
+				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
+				"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_phy_aux_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <100000000>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+						 <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_1_BCR>,
+			<&gcc GCC_PCIE_1_PHY_BCR>;
+
+		reset-names = "pcie_1_core_reset",
+				"pcie_1_phy_reset";
+
+		status = "disabled";
+		pcie_rc1: pcie_rc1 {
+			#address-cells = <5>;
+			#size-cells = <0>;
+			reg = <0 0 0 0 0>;
+			pci-ids = "17cb:0108";
+		};
+	};
+
+	pcie1_msi: qcom,pcie1_msi@17a00040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a00040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
+
+		status = "disabled";
+	};
+
+};
--- a/qcom/sa8155-vm-qupv3.dtsi
+++ b/qcom/sa8155-vm-qupv3.dtsi
@@ -0,0 +1,108 @@
+&soc {
+	/* QUPv3 SE Instances
+	 * Qup0 0: SE 0
+	 * Qup0 1: SE 1
+	 * Qup0 2: SE 2
+	 * Qup0 3: SE 3
+	 * Qup0 4: SE 4
+	 * Qup0 5: SE 5
+	 * Qup0 6: SE 6
+	 * Qup0 7: SE 7
+	 * Qup1 0: SE 8
+	 * Qup1 1: SE 9
+	 * Qup1 2: SE 10
+	 * Qup1 3: SE 11
+	 * Qup1 4: SE 12
+	 * Qup1 5: SE 13
+	 * Qup2 0: SE 14
+	 * Qup2 1: SE 15
+	 * Qup2 2: SE 16
+	 * Qup2 3: SE 17
+	 * Qup2 4: SE 18
+	 * Qup2 5: SE 19
+	 */
+
+	/* QUPv3_1  wrapper  instance */
+	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0xac0000 0x6000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x603 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		/* Debug UART Instance */
+		qupv3_se12_2uart: qcom,qup_uart@a90000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0xa90000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se12_2uart_active>;
+			pinctrl-1 = <&qupv3_se12_2uart_sleep>;
+			status = "disabled";
+		};
+	};
+
+	/* QUPv3_2  wrapper  instance */
+	qupv3_2: qcom,qupv3_2_geni_se@cc0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0xcc0000 0x6000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x7a3  0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		/* HS UART Instance */
+		qupv3_se17_4uart: qcom,qup_uart@c8c000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0xc8c000 0x4000>;
+			reg-names = "se_phys";
+			interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+					<&tlmm 46 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se17_default_ctsrtsrx>,
+						<&qupv3_se17_default_tx>;
+			pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
+						<&qupv3_se17_tx>;
+			pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
+						<&qupv3_se17_tx>;
+			pinctrl-3 = <&qupv3_se17_default_ctsrtsrx>,
+						<&qupv3_se17_default_tx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		qupv3_se19_i2c: i2c@c94000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xc94000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se19_i2c_active>;
+			pinctrl-1 = <&qupv3_se19_i2c_sleep>;
+			status = "disabled";
+		};
+	};
+};
--- a/qcom/sa8155-vm.dtsi
+++ b/qcom/sa8155-vm.dtsi
@@ -1,10 +1,14 @@
+#include <dt-bindings/clock/qcom,gcc-sm8150.h>
 #include "quin-vm-common.dtsi"
 #include "pm8150-vm.dtsi"
-
 / {
 	model = "Qualcomm Technologies, Inc. SA8155 Guest Virtual Machine";
 	qcom,msm-name  = "SA8155 v2";
 	qcom,msm-id = <362 0x20000>;
+	aliases {
+		hsuart0 = &qupv3_se17_4uart;
+		serial0 = &qupv3_se12_2uart;
+	};

 	cpus {
 		#address-cells = <2>;
@@ -132,6 +136,44 @@
 };

 &soc {
+	/* Rome 3.3V supply */
+	vreg_wlan: vreg_wlan {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "vreg_wlan";
+	};
+
+	/* PWR_CTR2_VDD_1P8 supply */
+	vreg_conn_1p8: vreg_conn_1p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_1p8";
+		pinctrl-names = "default";
+		pinctrl-0 = <&conn_power_1p8_active>;
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&tlmm 173 0>;
+	};
+
+	/* PWR_CTR1_VDD_PA supply */
+	vreg_conn_pa: vreg_conn_pa {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_pa";
+		pinctrl-names = "default";
+		pinctrl-0 = <&conn_power_pa_active>;
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&tlmm 174 0>;
+	};
+
+	VDD_CX_LEVEL: VDD_MMCX_LEVEL:
+	S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8150_2_s9_level";
+		regulator-min-microvolt
+			= <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt
+			= <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
 	apps_smmu: apps-smmu@0x15000000 {
 		compatible = "qcom,qsmmu-v500";
 		reg = <0x15000000 0x100000>,
@@ -232,10 +274,140 @@
 		compatible = "qcom,iommu-dma";
 		memory-region = <&system_cma>;
 	};
+
+	qcom_rng: qrng@793000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x793000 0x1000>;
+		qcom,no-qrng-config;
+		clocks = <&gcc GCC_PRNG_AHB_CLK>;
+		clock-names = "km_clk_src";
+	};
+
+	pdc: interrupt-controller@b220000 {
+		compatible = "qcom,sm8150-pdc","qcom,pdc";
+		reg = <0xb220000 0x30000>;
+		qcom,pdc-ranges = <6 486 6>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
+	};
 };

 #include "sm8150-pinctrl.dtsi"
+#include "sa8155-vm-pcie.dtsi"
+#include "sa8155-vm-qupv3.dtsi"

 &tlmm {
 	/delete-property/ wakeup-parent;
 };
+
+&regulator {
+	virt_regulator {
+		compatible = "virtio,device31";
+
+		usb30_prim_gdsc: usb30_prim_gdsc {
+			regulator-name = "usb30_prim_gdsc";
+		};
+
+		usb30_sec_gdsc: usb30_sec_gdsc {
+			regulator-name = "usb30_sec_gdsc";
+		};
+
+		pcie_0_gdsc: pcie_0_gdsc {
+			regulator-name = "pcie_0_gdsc";
+		};
+
+		pcie_1_gdsc: pcie_1_gdsc {
+			regulator-name = "pcie_1_gdsc";
+		};
+
+		L2A: pm8150_1_l2: regulator-pm8150-1-l2 {
+			regulator-name = "ldoa2";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+		};
+
+		L5A: pm8150_1_l5: regulator-pm8150-1-l5 {
+			regulator-name = "ldoa5";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+		};
+
+		L12A: pm8150_1_l12: regulator-pm8150-1-l12 {
+			regulator-name = "ldoa12";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		L17A: pm8150_1_l17: regulator-pm8150-1-l17 {
+			regulator-name = "ldoa17";
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <2960000>;
+		};
+
+		L8C: pm8150_2_l8: regulator-pm8150-2-l8 {
+			regulator-name = "ldoc8";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-allow-set-load;
+		};
+
+		L13C: pm8150_2_l13: regulator-pm8150-2-l13 {
+			regulator-name = "ldoc13";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+		};
+
+		L15C: pm8150_2_l15: regulator-pm8150-2-l15 {
+			regulator-name = "ldoc15";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1904000>;
+		};
+
+		L18C: pm8150_2_l18: regulator-pm8150-2-l18 {
+			regulator-name = "ldoc18";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-allow-set-load;
+		};
+
+		S6A: pm8150_1_s6: regulator-pm8150-1-s6 {
+			regulator-name = "smpa6";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <1352000>;
+		};
+
+		S4C: pm8150_2_s4: regulator-pm8150-2-s4 {
+			regulator-name = "smpc4";
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <1400000>;
+		};
+
+		S5C: pm8150_2_s5: regulator-pm8150-2-s5 {
+			regulator-name = "smpc5";
+			regulator-min-microvolt = <1824000>;
+			regulator-max-microvolt = <2040000>;
+		};
+	};
+};
+
+&hab {
+	/delete-node/ mmidgrp1400;
+	/delete-node/ mmidgrp1500;
+};
+
+&pcie0_msi {
+	status = "ok";
+};
+
+&pcie0 {
+	status = "ok";
+};
+
+&qupv3_se17_4uart {
+	status = "ok";
+};
+
+&qupv3_se12_2uart {
+	status = "disabled";
+};
--- a/qcom/sa8195-vm-la-overlay.dts
+++ b/qcom/sa8195-vm-la-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "sa8195-vm.dtsi"
+#include "sa8195-vm-la.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SA8195 Single LA Virtual Machine";
+	compatible = "qcom,sa8195p", "qcom,quinvm";
+	qcom,pmic-name = "PM8195";
+	qcom,board-id = <0 0x1000001>;
+};
--- a/qcom/sa8195-vm-la.dts
+++ b/qcom/sa8195-vm-la.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sa8195-vm.dtsi"
+#include "sa8195-vm-la.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SA8195 Single LA Virtual Machine";
+	compatible = "qcom,sa8195p", "qcom,quinvm";
+	qcom,pmic-name = "PM8195";
+	qcom,board-id = <0 0x1000001>;
+};
--- a/qcom/sa8195-vm-la.dtsi
+++ b/qcom/sa8195-vm-la.dtsi
@@ -0,0 +1,2 @@
+&soc {
+};
--- a/qcom/sa8195-vm.dtsi
+++ b/qcom/sa8195-vm.dtsi
@@ -0,0 +1,7 @@
+#include "quin-vm-common.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SA8195 Virtual Machine";
+	qcom,msm-name = "SA8195P";
+	qcom,msm-id = <405 0x20000>;
+};
--- a/qcom/scuba_auto.dtsi
+++ b/qcom/scuba_auto.dtsi
@@ -186,6 +186,11 @@
 		reg = <0x0 0x52910000 0x0 0x5000>;
 	};

+	pil_reserved_unused_mem: pil_reserved_unused_region@52915000 {
+		no-map;
+		reg = <0x0 0x52915000 0x0 0xEB000>;
+	};
+
 	tz_stat: tz_stat@53200000 {
 		no-map;
 		reg = <0x0 0x53200000 0x0 0x100000>;
@@ -255,6 +260,16 @@

 };

+&firmware {
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+	};
+
+	qcom_smcinvoke {
+		compatible = "qcom,smcinvoke";
+	};
+};
+
 &soc {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -298,6 +313,22 @@
 		hyplog-size-offset = <0x414>;
 	};

+	qcom_qseecom: qseecom@c1700000 {
+		compatible = "qcom,qseecom";
+		memory-region = <&qseecom_mem>;
+		qseecom_mem = <&qseecom_mem>;
+		qseecom_ta_mem = <&qseecom_ta_mem>;
+		user_contig_mem = <&user_contig_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,no-clock-support;
+		qcom,appsbl-qseecom-support;
+		qcom,commonlib64-loaded-by-uefi;
+		qcom,qsee-reentrancy-support = <2>;
+	};
+
 	memtimer: timer@f120000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -415,6 +446,7 @@
 		reg-names = "wdt-base";
 		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
 				<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
 	};

 	rpm_msg_ram: memory@045f0000 {
--- a/qcom/sdmshrike.dtsi
+++ b/qcom/sdmshrike.dtsi
@@ -334,7 +334,9 @@
 		};
 	};

-	chosen {};
+	chosen {
+		bootargs = "kpti=0 ssbd=force-off";
+	};

 	firmware: firmware {
 		android {
--- a/qcom/sdxbaagha-external-soc.dtsi
+++ b/qcom/sdxbaagha-external-soc.dtsi
@@ -0,0 +1,51 @@
+&soc {
+	mdm0: qcom,remoteproc-esoc0 {
+		cell-index = <0>;
+		#address-cells = <0>;
+		interrupt-parent = <&mdm0>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0xffffffff>;
+		interrupt-names =
+			"err_fatal_irq",
+			"status_irq";
+		interrupt-map = <0 &tlmm 31 0x3
+				 1 &tlmm 28 0x3>;
+		/* modem attributes */
+		qcom,ramdump-delay-ms = <3000>;
+		qcom,ramdump-timeout-ms = <120000>;
+		qcom,vddmin-modes = "normal";
+		qcom,vddmin-drive-strength = <8>;
+		qcom,sfr-query;
+		qcom,sysmon-id = <20>;
+		qcom,ssctl-instance-id = <0x10>;
+		qcom,support-shutdown;
+		qcom,pil-force-shutdown;
+		pinctrl-names = "default", "mdm_active", "mdm_suspend";
+		pinctrl-0 = <&ap2mdm_pon_reset_default>;
+		pinctrl-1 = <&ap2mdm_active &mdm2ap_active>;
+		pinctrl-2 = <&ap2mdm_sleep &mdm2ap_sleep>;
+		qcom,mdm2ap-status-gpio   = <&tlmm 28 0x00>;
+		qcom,ap2mdm-status-gpio   = <&tlmm 29 0x00>;
+		qcom,ap2mdm-errfatal-gpio = <&tlmm 30 0x00>;
+		qcom,mdm2ap-errfatal-gpio = <&tlmm 31 0x00>;
+		qcom,ap2mdm-soft-reset-gpio = <&pm8550_gpios 1 0>;
+
+		reg-names = "l10b";
+		l10c-supply = <&L10B>;
+		l10c-uV-uA = <1200000 100000>;
+
+		qcom,esoc-skip-restart-for-mdm-crash;
+		status = "ok";
+	};
+};
+
+&pm8550_gpios {
+	ap2mdm_pon_reset {
+		ap2mdm_pon_reset_default: ap2mdm_pon_reset_default {
+			/* MDM PON control*/
+			pins = "gpio1";
+			function = "normal";
+			power-source = <1>; /* 1.8V */
+		};
+	};
+};
--- a/qcom/sdxbaagha-pinctrl.dtsi
+++ b/qcom/sdxbaagha-pinctrl.dtsi
@@ -8,6 +8,7 @@
 		interrupt-controller;
 		interrupt-parent = <&intc>;
 		#interrupt-cells = <2>;
+		wakeup-parent = <&pdc>;

 		qupv3_se3_2uart_pins: qupv3_se3_2uart_pins {
 			qupv3_se3_2uart_tx_active: qupv3_se3_2uart_tx_active {
--- a/qcom/sdxbaagha.dtsi
+++ b/qcom/sdxbaagha.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/soc/qcom,ipcc.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,sdxbaagha.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>

 / {
 	#address-cells = <1>;
@@ -240,6 +241,45 @@
 		#mbox-cells = <1>;
 	};

+	apps_rsc: rsc@17040000 {
+		label = "apps_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0x17040000 0x10000>,
+		      <0x17050000 0x10000>;
+		reg-names = "drv-0", "drv-1";
+		qcom,drv-count = <2>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+
+		apps_rsc_drv1: drv@1 {
+			qcom,drv-id = <1>;
+			qcom,tcs-offset = <0xd00>;
+			channel@0 {
+				qcom,tcs-config = <ACTIVE_TCS    2>,
+						  <SLEEP_TCS     1>,
+						  <WAKE_TCS      1>,
+						  <CONTROL_TCS   0>,
+						  <FAST_PATH_TCS 0>;
+			};
+		};
+	};
+
+	pdc: interrupt-controller@b210000 {
+		compatible = "qcom,sdxbaagha-pdc", "qcom,pdc";
+		reg = <0xb210000 0x30000>;
+		qcom,pdc-ranges = <1 148 6>, <9 156 2>, <17 164 7>,
+				  <26 173 1>, <29 176 1>, <40 187 1>,
+				  <46 193 6>, <52 266 32>, <84 249 1>,
+				  <85 256 1>, <86 315 4>, <90 43 1>,
+				  <91 45 1>, <92 154 2>, <94 158 6>,
+				  <100 171 2>, <102 174 1>, <103 23 7>,
+				  <110 147 1>, <111 31 4>, <115 175 1>,
+				  <116 177 10>, <126 188 5>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <1 13 0xf08>,
@@ -484,6 +524,10 @@
 		qcom,skip-qos;
 	};

+	qcom,sps {
+		compatible = "qcom,msm-sps-4k";
+		qcom,pipe-attr-ee;
+	};
 };

 #include "sdxbaagha-pinctrl.dtsi"
--- a/qcom/sm8150.dtsi
+++ b/qcom/sm8150.dtsi
@@ -351,7 +351,7 @@
 	};

 	chosen: chosen {
-		bootargs = "qcom_dma_heaps.enable_bitstream_contig_heap=y";
+		bootargs = "qcom_dma_heaps.enable_bitstream_contig_heap=y kpti=0 ssbd=force-off";
 	};

 	soc: soc { };