Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add sdcard support for SA8195"

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qctecmdr
2022-11-18 07:03:45 -08:00
committed by Gerrit - the friendly Code Review server
parent 9e00c30704 f840480802
commit bc869f6f66
2 changed files with 81 additions and 0 deletions
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18
qcom/sa8195p.dtsi
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@@ -132,6 +132,24 @@
status = "ok";
};
&sdhc_2 {
vdd-supply = <&pm8195_1_l10>;
qcom,vdd-voltage-level = <2950000 2960000>;
qcom,vdd-current-level = <200 800000>;
vdd-io-supply = <&pm8195_1_l2>;
qcom,vdd-io-voltage-level = <1808000 2960000>;
qcom,vdd-io-current-level = <200 22000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>;
status = "ok";
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4";
vdda-phy-supply = <&pm8195_3_l5>;

63
qcom/sdmshrike.dtsi
View File

@@ -28,6 +28,7 @@
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS slot */
mmc1 = &sdhc_2; /* SDC2 SD Card slot */
serial0 = &qupv3_se12_2uart;
spi22 = &qupv3_se22_spi;
i2c7 = &qupv3_se20_i2c;
@@ -1574,6 +1575,68 @@
};
};
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-peak-kBps = <1600000 280000>;
opp-avg-kBps = <50000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
opp-peak-kBps = <5600000 1500000>;
opp-avg-kBps = <104000 0>;
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x8804000 0x1000>;
reg-names = "hc_mem";
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
bus-width = <4>;
qcom,restore-after-cx-collapse;
iommus = <&apps_smmu 0x06A0 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc2_opp_table>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
qcom,devfreq,freq-table = <50000000 200000000>;
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <70>;
};
qos1 {
mask = <0xf0>;
vote = <70>;
};
};
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xe00>; /* PHY regs */
reg-names = "phy_mem";