ARM: dts: msm: Add QUPv3 UART console node for sdxpinn

Enable console support on sdxpinn

Change-Id: I79f149d2bcfe910738a31a1d4172233ac245a783

qcom/sdxpinn-pinctrl.dtsi

@@ -1 +1,42 @@
-&tlmm { };
+&tlmm {
+	qupv3_se1_2uart_pins: qupv3_se1_2uart_pins {
+		qupv3_se1_2uart_tx_active: qupv3_se1_2uart_tx_active {
+			mux {
+				pins = "gpio12";
+				function = "qup_se1_l2";
+			};
+
+			config {
+				pins = "gpio12";
+				drive-strength= <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_2uart_rx_active: qupv3_se1_2uart_rx_active {
+			mux {
+				pins = "gpio13";
+				function = "qup_se1_l3";
+			};
+
+			config {
+				pins = "gpio13";
+				drive-strength= <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_2uart_sleep: qupv3_se1_2uart_sleep {
+			mux {
+				pins = "gpio12", "gpio13";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio12", "gpio13";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
+};

qcom/sdxpinn-qupv3.dtsi

@@ -0,0 +1,28 @@
+&soc {
+	/* QUPv3_0 wrapper instance */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x9c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		ranges;
+		status = "ok";
+
+		/*PORed Debug UART Instance */
+		qupv3_se1_2uart: qcom,qup_uart@984000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0x984000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_2uart_tx_active>, <&qupv3_se1_2uart_rx_active>;
+			pinctrl-1 = <&qupv3_se1_2uart_sleep>;
+			status = "disabled";
+		};
+	};
+};

qcom/sdxpinn-rumi.dtsi

@@ -5,3 +5,7 @@
 &memtimer {
 	clock-frequency = <500000>;
 };
+
+&qupv3_se1_2uart {
+	qcom,rumi_platform;
+};

qcom/sdxpinn.dtsi

@@ -17,7 +17,9 @@
 
 	chosen: chosen { };
 
-	aliases { };
+	aliases {
+		serial0 = &qupv3_se1_2uart;
+	};
 
 	cpus {
 		#address-cells = <2>;
@@ -376,3 +378,8 @@
 #include "ipcc-test-sdxpinn.dtsi"
 #include "sdxpinn-regulators.dtsi"
 #include "sdxpinn-pinctrl.dtsi"
+#include "sdxpinn-qupv3.dtsi"
+
+&qupv3_se1_2uart {
+	status = "ok";
+};