mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:04:24 +00:00
ARM: dts: msm: Add ARM SMMU devices for SDMSHRIKE
Add the set of devices that describe the APPS and graphics SMMU register spaces and various properties for SDMSHRIKE. Change-Id: I7928f5da868235c8a1a4abbcac5a0bd427413926
This commit is contained in:
Shreyas K K
396
qcom/msm-arm-smmu-sdmshrike.dtsi
Normal file
396
qcom/msm-arm-smmu-sdmshrike.dtsi
Normal file
@@ -0,0 +1,396 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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kgsl_smmu: kgsl-smmu@2ca0000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x2ca0000 0x10000>,
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<0x2cc2000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,dynamic;
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qcom,use-3-lvl-tables;
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#global-interrupts = <2>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gpu_cx_gdsc>;
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clock-names = "gcc_gpu_memnoc_gfx_clk",
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"gcc_gpu_snoc_dvm_gfx_clk",
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"gpu_cc_ahb_clk";
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clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
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gfx_0_tbu: gfx_0_tbu@2cc5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x2cc5000 0x1000>,
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<0x2cc2200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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qcom,iova-width = <49>;
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};
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gfx_1_tbu: gfx_1_tbu@2cc9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x2cc9000 0x1000>,
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<0x2cc2208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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qcom,iova-width = <49>;
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};
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gfx_2_tbu: gfx_2_tbu@2ccd000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x2ccd000 0x1000>,
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<0x2cc2210 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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qcom,iova-width = <49>;
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};
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gfx_3_tbu: gfx_3_tbu@2cd1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x2cd1000 0x1000>,
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<0x2cc2218 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0xC00 0x400>;
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qcom,iova-width = <49>;
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};
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};
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apps_smmu: apps-smmu@15000000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x15000000 0x100000>,
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<0x15182000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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#global-interrupts = <1>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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anoc_1_tbu: anoc_1_tbu@15185000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15185000 0x1000>,
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<0x15182200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,iova-width = <36>;
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};
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anoc_2_tbu: anoc_2_tbu@15189000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15189000 0x1000>,
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<0x15182208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,iova-width = <36>;
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};
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mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x1518d000 0x1000>,
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<0x15182210 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
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qcom,active-only;
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interconnects = <&mmss_noc MASTER_MDP0
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&mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
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qcom,iova-width = <32>;
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};
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mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15191000 0x1000>,
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<0x15182218 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0xc00 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
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qcom,active-only;
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interconnects = <&mmss_noc MASTER_MDP0
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&mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
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qcom,iova-width = <32>;
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};
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compute_dsp_1_tbu: compute_dsp_1_tbu@15195000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15195000 0x1000>,
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<0x15182220 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1000 0x400>;
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qcom,active-only;
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interconnects = <&compute_noc MASTER_NPU
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&compute_noc SLAVE_CDSP_MEM_NOC>;
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qcom,iova-width = <32>;
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};
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compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15199000 0x1000>,
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<0x15182228 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1400 0x400>;
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qcom,active-only;
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interconnects = <&compute_noc MASTER_NPU
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&compute_noc SLAVE_CDSP_MEM_NOC>;
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qcom,iova-width = <32>;
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};
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adsp_tbu: adsp_tbu@1519d000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x1519d000 0x1000>,
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<0x15182230 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1800 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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||||
qcom,iova-width = <32>;
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||||
};
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anoc_pcie: anoc_pcie@151a1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151a1000 0x1000>,
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<0x15182238 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1c00 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>;
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clock-names = "gcc_aggre_noc_pcie_tbu_clk";
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clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,iova-width = <36>;
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||||
};
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||||
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mnoc_sf_0_tbu: mnoc_sf_0_tbu@151a5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151a5000 0x1000>,
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<0x15182240 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2000 0x400>;
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||||
qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
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qcom,active-only;
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interconnects = <&mmss_noc MASTER_CAMNOC_SF
|
||||
&mmss_noc SLAVE_MNOC_SF_MEM_NOC>;
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||||
qcom,iova-width = <32>;
|
||||
};
|
||||
};
|
||||
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dma_dev@0x0 {
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||||
compatible = "qcom,iommu-dma";
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||||
memory-region = <&system_cma>;
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||||
};
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||||
|
||||
iommu_test_device {
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compatible = "qcom,iommu-debug-test";
|
||||
|
||||
kgsl_iommu_test_device {
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||||
compatible = "qcom,iommu-debug-usecase";
|
||||
iommus = <&kgsl_smmu 0x7 0>;
|
||||
};
|
||||
|
||||
kgsl_iommu_coherent_test_device {
|
||||
compatible = "qcom,iommu-debug-usecase";
|
||||
iommus = <&kgsl_smmu 0x9 0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
apps_iommu_test_device {
|
||||
compatible = "qcom,iommu-debug-usecase";
|
||||
iommus = <&apps_smmu 0x21 0>;
|
||||
};
|
||||
|
||||
apps_iommu_coherent_test_device {
|
||||
compatible = "qcom,iommu-debug-usecase";
|
||||
iommus = <&apps_smmu 0x23 0>;
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&kgsl_smmu {
|
||||
qcom,actlr =
|
||||
/* All CBs of GFX: +15 deep PF */
|
||||
<0x0 0x3ff 0x303>,
|
||||
<0x400 0x3ff 0x303>,
|
||||
<0x800 0x3ff 0x303>,
|
||||
<0xc00 0x3ff 0x303>;
|
||||
};
|
||||
|
||||
&apps_smmu {
|
||||
qcom,actlr =
|
||||
/* HF0/1, SF TBU +3 PF */
|
||||
<0x800 0x3ff 0x103>,
|
||||
<0xc00 0x3ff 0x103>,
|
||||
<0x2000 0x3ff 0x103>,
|
||||
|
||||
/* NPU SIDs: +15 deep PF */
|
||||
<0x1480 0x7 0x303>,
|
||||
<0x1080 0x7 0x303>;
|
||||
};
|
||||
@@ -485,7 +485,7 @@
|
||||
};
|
||||
|
||||
/* global autoconfigured region for contiguous allocations */
|
||||
linux,cma {
|
||||
system_cma: linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
@@ -1216,6 +1216,7 @@
|
||||
#include "sa8195-regulator.dtsi"
|
||||
#include "sm8150-slpi-pinctrl.dtsi"
|
||||
#include "sa8195-gdsc.dtsi"
|
||||
#include "msm-arm-smmu-sdmshrike.dtsi"
|
||||
|
||||
&emac_gdsc {
|
||||
status = "ok";
|
||||
|
||||
Reference in New Issue
Block a user