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https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: msm: Add interconnect property for Khaje
Add interconnect support for usb, qseecom, qcedev, sdhci, ipa and qcrypto for Khaje. Change-Id: Icf18e27c33237995d960ab4bc1dc49223b86520b
This commit is contained in:
Chetan C R
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Gerrit - the friendly Code Review server
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c4976ef418
commit
e0f025c92e
@@ -44,6 +44,22 @@
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0x1a4>; /* GSI_IF_STS */
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qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
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interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
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interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
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<&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;
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qcom,interconnect-values-nom = /* NOMINAL Votes */
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<240000 700000>,
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<0 2400>,
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<0 40000>;
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qcom,interconnect-values-svs = /* SVS Votes */
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<240000 700000>,
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<0 2400>,
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<0 40000>;
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dwc3@4e00000 {
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compatible = "snps,dwc3";
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reg = <0x4e00000 0xe000>;
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107
qcom/khaje.dtsi
107
qcom/khaje.dtsi
@@ -1907,6 +1907,8 @@
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qcom,fde-key-size;
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qcom,appsbl-qseecom-support;
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qcom,commonlib64-loaded-by-uefi;
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interconnect-names = "data_path";
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interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
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clock-names =
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"core_clk_src", "core_clk",
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"iface_clk", "bus_clk";
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@@ -1931,8 +1933,10 @@
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reg = <0x1b53000 0x1000>;
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qcom,msm-rng-iface-clk;
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qcom,no-qrng-config;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "iface_clk";
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interconnect-names = "data_path";
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interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_HWKM_CORE>;
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clock-names = "km_clk_src";
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clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
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};
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qcom_tzlog: tz-log@c125720 {
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@@ -1954,6 +1958,8 @@
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qcom,ce-device = <0>;
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qcom,ce-hw-shared;
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qcom,bam-ee = <0>;
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interconnect-names = "data_path";
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interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
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clock-names =
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"core_clk_src", "core_clk",
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"iface_clk", "bus_clk";
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@@ -2001,6 +2007,8 @@
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qcom,bam-ee = <0>;
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qcom,ce-hw-shared;
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qcom,clk-mgmt-sus-res;
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interconnect-names = "data_path";
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interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
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clock-names =
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"core_clk_src", "core_clk",
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"iface_clk", "bus_clk";
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@@ -2520,6 +2528,42 @@
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qcom,ice-clk-rates = <300000000 100000000>;
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interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>;
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interconnect-names = "sdhc-ddr","cpu-sdhc";
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qcom,msm-bus,name = "sdhc1";
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qcom,msm-bus,num-cases = <9>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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/* No vote */
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<0 0>, <0 0>,
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/* 400 KB/s*/
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<1046 1600>,
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<1600 1600>,
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/* 20 MB/s */
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<20480 80000>,
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<80000 80000>,
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/* 25 MB/s */
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<25600 250000>,
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<50000 133320>,
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/* 50 MB/s */
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<51200 250000>,
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<65000 133320>,
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/* 100 MB/s */
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<102400 250000>,
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<65000 133320>,
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/* 200 MB/s */
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<204800 800000>,
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<200000 300000>,
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/* 400 MB/s */
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<204800 800000>,
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<200000 300000>,
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/* Max. bandwidth */
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<1338562 4096000>,
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<1338562 4096000>;
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qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
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100750000 200000000 400000000 4294967295>;
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/* Add support for gcc hw reset */
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resets = <&gcc GCC_SDCC1_BCR>;
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reset-names = "core_reset";
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@@ -2558,6 +2602,42 @@
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<&gcc GCC_SDCC2_APPS_CLK>;
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clock-names = "iface", "core";
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interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>;
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interconnect-names = "sdhc-ddr","cpu-sdhc";
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qcom,msm-bus,name = "sdhc2";
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qcom,msm-bus,num-cases = <8>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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/* No vote */
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<0 0>, <0 0>,
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/* 400 KB/s*/
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<1046 3200>,
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<1600 1600>,
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/* 20 MB/s */
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<52286 250000>,
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<80000 133320>,
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/* 25 MB/s */
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<65360 250000>,
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<100000 133320>,
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/* 50 MB/s */
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<130718 250000>,
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<133320 133320>,
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/* 100 MB/s */
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<261438 250000>,
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<150000 133320>,
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/* 200 MB/s */
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<261438 800000>,
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<300000 300000>,
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/* Max. bandwidth */
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<1338562 4096000>,
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<1338562 4096000>;
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qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
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100750000 200000000 4294967295>;
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qcom,devfreq,freq-table = <50000000 202000000>;
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/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
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qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
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qcom,vbias-skip-wa;
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@@ -2705,7 +2785,6 @@
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vote = <26>;
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perf;
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};
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qos1 {
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mask = <0xf0>;
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vote = <26>;
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@@ -3409,6 +3488,7 @@
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ddr_dcvs_sp: sp {
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compatible = "qcom,dcvs-path";
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qcom,dcvs-path-type = <0>;
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interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI_CH0>;
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};
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};
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};
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@@ -3531,6 +3611,27 @@
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qcom,max_num_smmu_cb = <3>;
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clocks = <&rpmcc RPM_SMD_IPA_CLK>;
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clock-names = "core_clk";
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qcom,interconnect,num-cases = <5>;
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qcom,interconnect,num-paths = <3>;
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interconnects = <&system_noc MASTER_IPA &bimc SLAVE_EBI_CH0>,
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<&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_IPA_CFG>;
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interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa";
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/* No vote */
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qcom,no-vote =
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<0 0 0 0 0 0>;
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/* SVS2 */
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qcom,svs2 =
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<80000 465000 80000 68570 80000 30>;
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/* SVS */
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qcom,svs =
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<80000 2000000 80000 267461 80000 109890>;
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/* NOMINAL */
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qcom,nominal =
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<206000 4000000 206000 712961 206000 491520>;
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/* TURBO */
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qcom,turbo =
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<206000 5598900 206000 1436481 206000 491520>;
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qcom,bus-vector-names =
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"MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
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@@ -131,6 +131,9 @@
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<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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qcom,actlr =
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@@ -145,6 +148,10 @@
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<0xc782200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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interconnects = <&bimc MASTER_AMPSS_M0
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&config_noc SLAVE_IMEM_CFG>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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qcom,iova-width = <36>;
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@@ -159,6 +166,10 @@
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>;
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interconnects = <&mmrt_virt MASTER_MDP_PORT0
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&mmrt_virt SLAVE_SNOC_BIMC_RT>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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qcom,iova-width = <36>;
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@@ -173,6 +184,10 @@
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>;
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interconnects = <&mmnrt_virt MASTER_CAMNOC_SF
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&mmnrt_virt SLAVE_SNOC_BIMC_NRT>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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qcom,iova-width = <32>;
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@@ -187,6 +202,10 @@
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>;
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interconnects = <&bimc MASTER_AMPSS_M0
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&bimc SLAVE_EBI_CH0>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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