Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Update protected-clocks and compatible string for SC8180X"

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qctecmdr
2022-06-26 22:21:39 -07:00
committed by Gerrit - the friendly Code Review server
parent 7abc75357a dabc6d838c
commit e2cec75288
2 changed files with 17 additions and 42 deletions
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2
qcom/sa8195p-regulator.dtsi
View File

@@ -425,7 +425,7 @@
rpmh-regulator-gfxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "gfx.lvl";
VDD_GFX:
VDD_GFX_LEVEL:
S10C_LEVEL: pm8195_2_s10_level: regulator-pm8195-2-s10-level {
regulator-name = "pm8195_2_s10_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;

57
qcom/sdmshrike.dtsi
View File

@@ -707,19 +707,15 @@
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names =
"bi_tcxo",
"bi_tcxo_ao",
"sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
protected-clocks = <GCC_NPU_AXI_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
};
scc: clock-controller@2b10000 {
compatible = "qcom,sa8195-scc";
compatible = "qcom,sc8180x-scc";
reg = <0x2b10000 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
@@ -733,12 +729,9 @@
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src";
clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -749,15 +742,10 @@
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_gdsc-supply = <&npu_core_gdsc>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_NPU_GPLL0_CLK_SRC>,
<&gcc GCC_NPU_AXI_CLK>;
clock-names =
"bi_tcxo",
"gcc_npu_gpll0_div_clk_src",
"gcc_npu_gpll0_clk_src",
"gcc_npu_axi_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_NPU_GPLL0_CLK_SRC>, <&gcc GCC_NPU_AXI_CLK>;
clock-names = "bi_tcxo", "gcc_npu_gpll0_div_clk_src",
"gcc_npu_gpll0_clk_src", "gcc_npu_axi_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -767,11 +755,8 @@
reg = <0xab00000 0x10000>;
reg-names = "cc_base";
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names =
"cfg_ahb_clk",
"bi_tcxo";
clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
clock-names = "cfg_ahb_clk", "bi_tcxo";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -782,13 +767,8 @@
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
clock-names =
"cfg_ahb_clk",
"bi_tcxo",
"sleep_clk";
clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
clock-names = "cfg_ahb_clk", "bi_tcxo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -798,13 +778,8 @@
reg = <0xaf00000 0x20000>;
reg-names = "cc_base";
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
clock-names =
"cfg_ahb_clk",
"bi_tcxo",
"sleep_clk";
clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
clock-names = "cfg_ahb_clk", "bi_tcxo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};