Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
2
0
Fork 0
mirror of https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees synced 2026-02-01 09:04:24 +00:00
Code Issues Packages Projects Releases Wiki Activity

dt-bindings: regulator: Add documentation for GDSC DT properties

Browse Source 
Add documentation for sw-reset, hw-ctrl-addr, domain-addr,
collapse-vote, skip-disable, support-cfg-gdscr and mboxes GDSC
DT properties.

Change-Id: Ibebe06c40b74a396cdd765ae5e3a5dd771dce128
This commit is contained in:
Kalpak Kawadkar
2022-07-30 11:46:24 +05:30
parent 55a66f72a2
commit e744f5bc1b
1 changed files with 23 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
bindings/regulator/gdsc-regulator.txt
View File

@@ -60,6 +60,27 @@ Optional properties:
enabled by an entity external to HLOS.
- qcom,no-config-gdscr: Presence denotes HW only supports a single register
per GDSC.
- qcom,collapse-vote: If present, GDSC will be controlled by votable register.
We need to pass the phandle of the register along with
the bit number of respective GDSC.
- sw-reset: If present, supports asynchronous resets for GDSC. We need to pass
the phandles of reset registers while using the property.
- domain-addr: If present, supports reset for voltage rail of GDSC. We pass
the phandle of the register while using the property.
- hw-ctrl-addr: If present, separate register will be there to poll for GDSC
status. While using the property, need to pass the phandle
of the register.
- qcom,skip-disable: Boolean flag indicating that the gdsc must not be
physically disabled upon a software disable request.
Instead, the GDSC will be disabled by always-on
processor (AOP) upon entering system sleep. The AOP
will also perform a special reset sequence for the GDSC
upon resuming the system sleep.
- qcom,support-cfg-gdscr: If present, the GDSC power on/down polling status is
read through GDSC configuration register.
- mboxes: Mailbox tuple containing QMP mailbox phandle and channel identifier.
If this is specified, then a QMP message should be sent
to enable the GDSC instead of setting SW_COLLAPSE=0.
Example:
gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
@@ -68,4 +89,6 @@ Example:
parent-supply = <&pm8841_s4>;
reg = <0xfd8c4024 0x4>;
clock-names = "core_clk";
mboxes = <&qmp_aop 0>;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
};